Philips scn2651 DATASHEETS

Philips Semiconductors Product specification

SCN2651Programmable communications interface (PCI)

1994 Apr 27 853-1067 12793

DESCRIPTION

The Philips Semiconductors SCN2651 PCI is a universal synchronous/asynchronous data communications controller chip designed for microcomputer systems. It interfaces directly to the Philips Semiconductors SCN2650 microprocessor and may be used in a polled or interrupt driven system environment. The SCN2651 accepts programmed instructions from the microprocessor and supports many serial data communication disciplines, synchronous and asynchronous, in the full or half-duplex mode.

The PCI serializes parallel data characters received from the microprocessor for transmission. Simultaneously, it can receive serial data and convert it into parallel data characters for input to the microcomputer.

The SCN2651 contains a baud rate generator which can be programmed to either accept an external clock or to generate internal transmit or receive clocks. Sixteen different baud rates can be selected under program control when operating in the internal clock mode.

The PCI is constructed using Philips Semiconductors n-channel silicon gate depletion load technology and is packaged in a 28-pin DIP.

FEATURES

•Synchronous operation

– 5- to 8-bit characters – Single or double SYN operation – Internal character synchronization – Transparent or non-transparent mode – Automatic SYN or DLE-SYN insertion – SYN or DLE stripping – Odd, even, or no parity – Local or remote maintenance loopback mode – Baud rate: DC to 1Mbps (1X clock)

•Asynchronous operation

– 5- to 8-bit characters – 1, 1-1/2 or 2 stop bits – Odd, even, or no parity – Parity, overrun and framing error detection – Line break detection and generation – False start bit detection – Automatic serial echo mode – Local or remote maintenance loopback mode – Baud rate: DC to 1Mbps

(1X clock) DC to 62.5kbps (16X clock) DC to 15.625kbps (64X clock)

PIN CONFIGURATIONS

23 22 21 20 19 18

16 15

28 27

10 11

26 25

D1 D0

RxC DTR

RTS DSR RESET BRCLK TxD TxEMT/DSCHG

CTS

DCD TxRDYRxRDY

R/W

TxC

GND

RxD

DIP

TOP VIEW

SD00049

OTHER FEATURES

•Internal or external baud rate clock

•16 internal rates – 50 to 19,200 baud

•Double buffered transmitter and receiver

•Full or half duplex operation

•TTL compatible inputs and outputs

•Single 5V power supply

•No system clock required

•28-pin dual in-line package

APPLICATIONS

•Intelligent terminals

•Network processors

•Front-end processors

•Remote data concentrators

•Computer to computer links

•Serial peripherals

ORDERING CODE

VCC = 5V +5%

PACKAGES

Commercial

Industrial

DWG #

28-Pin Plastic Dual In-Line Package (DIP) SCN2651CC1N28 Not available SOT117-2

0°C to +70°C -40°C to +85°C

Philips Semiconductors Product specification

SCN2651Programmable communications interface (PCI)

1994 Apr 27

BLOCK DIAGRAM

DATA BUS

D0–D7

RESET

R/W

DATA BUS

BUFFER

OPERATION CONTROL

MODE REGISTER 1

BAUD RATE

GENERATOR

AND

CLOCK CONTROL

SYN/DLE CONTROL

SYN 1 REGISTER SYN 2 REGISTER

DLE REGISTER

TRANSMITTER

TRANSMIT DATA

TxD

MODE REGISTER 2

COMMAND REGISTER

STATUS REGISTER

BRCLK

TxC

RxC

DSR

MODEM

CONTROL

DCD CTS RTS DTR

TxEMT/*

DSCHG

HOLDING REGISTER

TRANSMIT

SHIFT REGISTER

TxRDY

RECEIVE

RECEIVE DATA

RECEIVER

RxD

RxRDY

SHIFT REGISTER

HOLDING REGISTER

(27, 28, 1, 2, 5, 6, 7, 8)

(21) (12) (10) (13) (11)

(20)

(9)

(25)

(22) (16) (17) (23) (24) (18)

(15)

(19)

(14)

(3)

SD00050

ABSOLUTE MAXIMUM RATINGS

SYMBOL

PARAMETER RATING UNIT

Operating ambient temperature

Note 4 °C

STG

Storage temperature -65 to +150 °C All voltages with respect to ground

-0.5 to +6.0

NOTES:

1. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or at any other condition above those indicated in the operation section of this specification is not implied.

2. For operating at elevated temperatures, the device must be derated based on +150°C maximum junction temperature.

3. This product includes circuitry specifically designed for the protection of its internal devices from the damaging effect of excessive static charge. Nonetheless, it is suggested that conventional precautions be taken to avoid applying any voltages larger than the rated maxima.

4. Parameters are valid over operating temperature range unless otherwise specified. See ordering code table for applicable temperature range and operating supply range.

CAPACITANCE

= 25°C, V

= 0V

LIMITS

SYMBOL

PARAMETER

TEST CONDITIONS

Min Typ Max

UNIT

Capacitance

OUT

I/O

Input Output Input/Output

= 1MHz

Unmeasured pins tied to ground

20 20 20

pF pF pF

Philips Semiconductors Product specification

SCN2651Programmable communications interface (PCI)

1994 Apr 27

DC ELECTRICAL CHARACTERISTICS

1, 2, 3

LIMITS

SYMBOL

PARAMETER

TEST CONDITIONS

Min Typ Max

UNIT

Input voltage

Low High

2.0

0.8

V V

Output voltage

Low High

IOL = 1.6mA

= -100µA 2.4

0.4

V V

Input leakage current VIN = 0 to 5.25V -10 10 µA

3-State output leakage current

Data bus high Data bus low

VO = 4.0V

= 0.45V

-10

10 10

µA µA

Power supply current 150 mA

NOTES:

1. Parameters are valid over operating temperature range unless otherwise specified. See ordering code table for applicable temperature range and operating supply range.

2. All voltage measurements are referenced to ground. All time measurements are at the 50% level for inputs (except t

BRH

and t

BRL

) and at

0.8V and 2.0V for outputs. Input levels for testing are 0.45V and 2.4V .

3. Typical values are at +25°C, typical supply voltages and typical processing parameters.

AC ELECTRICAL CHARACTERISTICS

1, 2, 3

LIMITS

SYMBOL PARAMETER TEST CONDITIONS Min Typ Max UNIT

Pulse width

RES

Reset Chip enable

1000

300

ns ns

Set-up and hold time

RXS

RXH

Address setup Address hold R

/W control setup

/W control hold Data setup for write Data hold for write RX data setup RX data hold

20 20 20 20

225

0 300 350

ns ns ns ns ns ns ns ns

CED

Data delay time for read Data bus floating time for read CE

to CE delay

= 100pF

700

250 150

ns ns ns

Input clock frequency

BRG

R/T

Baud rate generator TxC

or RxC

1.0dc5.0688 5.0738

1.0

MHz MHz

Clock width

BRH

BRL

R/TH

R/TL

Baud rate high Baud rate low TxC

or RxC high

TxC

or RxC low

70 500 500

ns ns ns ns

TXD

TCS

TxD delay from falling edge of TxC Skew between TxD changing and falling edge of TxC output

= 100pF

650 ns

NOTES:

1. Parameters are valid over operating temperature range unless otherwise specified. See ordering code table for applicable temperature range and operating supply range.

2. All voltage measurements are referenced to ground. All time measurements are at the 50% level for inputs (except t

BRH

and t

BRL

) and at

0.8V and 2.0V for outputs. Input levels for testing are 0.45V and 2.4V .

3. Typical values are at +25°C, typical supply voltages and typical processing parameters.

4. Parameter applies when internal transmitter clock is used.

5. Under test conditions of 5.0688MHz, f

BRG

, t

BRH

, and t

BRL

measured at VIH and VIL respectively.

6. t

R/T

and t

R/TL

shown for all modes except local loopback. For local loopback mode f

R/T

= 0.7MHz and t

R/TL

= 700ns min.

Philips Semiconductors Product specification

SCN2651Programmable communications interface (PCI)

1994 Apr 27

PIN DESCRIPTION

Pin No. Symbol Name and Function Type

27, 28, 1, 2, 5-8 D0 – D

8-Bit data bus I/O

21 RESET Reset I

12, 10 A0–A

Internal register select lines I 13 R/W Read or write command I 11 CE Chip enable input I 22 DSR Data set ready I 24 DTR Data terminal ready O 23 RTS Request to send O 17 CTS Clear to send I 16 DCD Data carrier detected I 18 TxEMT/DSCHG Transmitter empty or data set change O

9 TxC Transmitter clock I/O 25 RxC Receiver clock I/O 19 TxD Transmitter data O

3 RxD Receiver data I 15 TxRDY Transmitter ready O 14 RxRDY Receiver ready O 20 BRCLK Baud rate generator clock I 26 V

+5V supply I

4 GND Ground I

Table 1. Baud Rate Generator Characteristics

Crystal Frequency = 5.0688MHz

Baud

Rate

Theoretical

Frequency

16X Clock

Actual

Frequency

16X Clock

Percent

Error

Divisor

50 0.8kHz 0.8kHz – 6336 75 1.2 1.2 – 4224

110 1.76 1.76 – 2880

134.5 2.152 2.1523 0.016 2355 150 2.4 2.4 – 2112 300 4.8 4.8 – 1056 600 9.6 9.6 – 528

1200 19.2 19.2 – 264 1800 28.8 28.8 – 176 2000 32.0 32.081 0.253 158 2400 38.4 38.4 – 132

NOTE: *Error at 19200 can be reduced to zero by using crystal frequency 4.9152MHz. 16X clock is used in asynchronous mode. In synchronous mode, clock multiplier is 1X.

BLOCK DIAGRAM

The PCI consists of six major sections. These are the transmitter, receiver, timing, operation control, modem control and SYN/DLE control. These sections communicate with each other via an internal data bus and an internal control bus. The internal data bus interfaces to the microprocessor data bus via a data bus buffer.

Operation Control

This functional block stores configuration and operation commands from the CPU and generates appropriate signals to various internal sections to control the overall device operation. It contains read and write circuits to permit communications with the microprocessor via

the data bus and contains mode registers 1 and 2, the command register, and the status register. Details of register addressing and protocol are presented in the PCI programming section of this data sheet.

Timing

The PCI contains a baud rate generator (BRG) which is programmable to accept external transmit or receive clocks or to divide an external clock to perform data communications. The unit can generate 16 commonly used baud rates, any one of which can be selected for full-duplex operation. See Table 1.

Receiver

The receiver accepts serial data on the RxD pin, converts this serial input to parallel format, checks for bits or characters that are unique to the communication technique and sends an “assembled” character to the CPU.

Transmitter

The transmitter accepts parallel data from the CPU, converts it to a serial bit stream, inserts the appropriate characters or bits (based on the communication technique) and outputs a composite serial stream of data on the TxD output pin.

Modem Control

The modem control section provides interfacing for three input signals and three output signals used for “handshaking” and status indication between the CPU and a modem.

SYN/DLE Control

This section contains control circuitry and three 8-bit registers storing the SYN1, SYN2, and DLE characters provided by the CPU. These registers are used in the synchronous mode of operation to provide the characters required for synchronization, idle fill and data transparency.

Philips Semiconductors Product specification

SCN2651Programmable communications interface (PCI)

1994 Apr 27

INTERFACE SIGNALS

The PCI interface signals can be grouped into two types: the CPU-related signals (shown in Table 2), which interface the SCN2651 to the microprocessor system, and the device-related signals (shown in Table 3), which are used to interface to the communications device or system.

OPERATION

The functional operation of the SCN2651 is programmed by a set of control words supplied by the CPU. These control words specify items such as synchronous or asynchronous mode, baud rate, number of bits per character, etc. The programming procedure is described in the PCI programming section of the data sheet.

After programming, the PCI is ready to perform the desired communications functions. The receiver performs serial to parallel conversion of data received from a modem or equivalent device. The transmitter converts parallel data received from the CPU to a serial bit stream. These actions are accomplished within the framework specified by the control words.

Receiver

The SCN2651 is conditioned to receive data when the DCD input is low and the RxEN bit in the command register is true. In the asynchronous mode, the receiver looks for a high to low transition of the start bit on the RxD input line. If a transition is detected, the state of the RxD line is sampled again after a delay of one-half of a bit-time. If RxD is now high, the search for a valid start bit is begun again. If RxD is still low, a valid start bit is assumed and the receiver continues to sample the input line at one bit time intervals until the proper number of data bits, the parity bit, and one stop bit(s) have

been assembled. The data is then transferred to the receive data holding register, the RxRDY bit in the status register is set, and the RxRDY

output is asserted. If the character length is less than 8 bits, the high order unused bits in the holding register are set to zero. The parity error, framing error, and overrun error status bits are strobed into the status register on the positive going edge of RxC corresponding to the received character boundary. If a break condition is detected (RxD is low for the entire character as well as the stop bit[s]), only one character consisting of all zeros (with the FE status bit set) will be transferred to the holding register. The RxD input must return to a high condition before a search for the next start bit begins.

When the PCI is initialized into the synchronous mode, the receiver first enters the hunt mode on a 0 to 1 transition of RxEN (CR2). In this mode, as data is shifted into the receiver shift register a bit at a time, the contents of the register are compared to the contents of the SYN1 register. If the two are not equal, the next bit is shifted in and the comparison is repeated. When the two registers match, the hunt mode is terminated and character assembly mode begins. If single SYN operation is programmed, the SYN detect status bit is set. If double SYN operation is programmed, the first character assembled after SYN1 must be SYN2 in order for the SYN detect bit to be set. Otherwise, the PCI returns to the hunt mode. (Note that the sequence SYN1–SYN1–SYN2 will not achieve synchronization.) When synchronization has been achieved, the PCI continues to assemble characters and transfer them to the holding register, setting the RxRDY status bit and asserting the RxRDY

output each time a character is transferred. The PE and OE status bits are set as appropriate. Further receipt of the appropriate SYN sequence sets the SYN detect status bit. If the SYN stripping mode is

Table 2. CPU-Related Signals

PIN NAME

NO.

INPUT/

OUTPUT

FUNCTION

26 I +5V supply input

GND 4 I Ground

RESET 21 I

A high on this input performs a master reset on the SCN2651. This signal asynchronously terminates any device activity and clears the mode, command and status registers. The device assumes the idle state and remains there until initialized with the appropriate control words.

A1 – A

10, 12 I Address lines used to select internal PCI registers.

R/W 13 I Read command when low, write command when high.

CE 11 I

Chip enable command. When low, indicates that control and data lines to the PCI are valid and that the operation specified by the R

W, A1 and A0 inputs should be performed. When high, places the D0–D7 lines

in the 3-State condition.

D7 – D

8, 7, 6, 5, 2, 1,

28, 27

I/O

8-bit, three-state data bus used to transfer commands, data and status between PCI and the CPU. D0 is the least significant bit, D

the most significant bit.

TxRDY 15 O

This output is the complement of status register bit SR0. When low, it indicates that the transmit data holding register (THR) is ready to accept a data character from the CPU. It goes high when the data character is loaded. This output is valid only when the transmitter is enabled. It is an open drain output which can be used as an interrupt to the CPU.

RxRDY 14 O

This output is the complement of status register bit SR1. When low, it indicates that the receive data holding register (RHR) has a character ready for input to the CPU. It goes high when the RHR is read by the CPU, and also when the receiver is disabled. It is an open drain output which can be used as an interrupt to the CPU.

TxEMT/DS CHG

18 O

This output is the complement of status register bit SR2. When low, it indicates that the transmitter has completed serialization of the last character loaded by the CPU, or that a change of state of the DSR

DCD

inputs has occurred. This output goes high when the status register is read by the CPU, if the TxEMT condition does not exist. Otherwise, the THR must be loaded by the CPU for this line to go high. It is an open drain output which can be used as an interrupt to the CPU.

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