Philips SC68C752B Technical data

SC68C752B

5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOs and Motorola µP interface

Rev. 03 — 29 November 2005 Product data sheet

1. General description

The SC68C752B is a dual Universal Asynchronous Receiver/Transmitter (UART) with 64-byte FIFOs, automatic hardware/software ﬂow control, and data rates up to 5 Mbit/s. The SC68C752B offers enhanced features. It has a Transmission Control Register (TCR) that stores receiver FIFO threshold levels to start/stop transmission during hardware and software ﬂow control. With the FIFO Rdy register, the software gets the status of TXRDY/RXRDY for all four ports in one access. On-chip status registers provide the user with error indications, operational status, and modem interface control. System interrupts may be tailored to meet user requirements. An internal loopback capability allows on-board diagnostics.

The UART transmits data, sent to it over the peripheral 8-bit bus, on the TX signal and receives characters on the RX signal. Characters can be programmed to be 5 bits, 6 bits, 7 bits, or 8 bits. The UART has a 64-byte receive FIFO and transmit FIFO and can be programmed to interrupt at different trigger levels. The UART generates its own desired baud rate based upon a programmable divisor and its input clock. It can transmit even, odd, or no parity and 1, 1.5, or 2 stop bits. The receiver can detect break, idle, or framing errors, FIFO overﬂow, and parity errors. The transmitter can detect FIFO underﬂow. The UART also contains a software interface for modem control operations, and has software ﬂow control and hardware ﬂow control capabilities.

2. Features

The SC68C752B is available in LQFP48 and HVQFN32 packages.

■ Dual channel with Motorola µP interface

■ Up to 5 Mbit/s data rate

■ 64-byte transmit FIFO

■ 64-byte receive FIFO with error ﬂags

■ Programmable and selectable transmit and receive FIFO trigger levels for DMA and

interrupt generation

■ Software/hardware ﬂow control

◆ Programmable Xon/Xoff characters

◆ Programmable Auto-RTS and Auto-CTS

■ Optional data ﬂow resume by Xon any character

■ DMA signalling capability for both received and transmitted data

■ Supports 5 V, 3.3 V and 2.5 V operation

■ 5 V tolerant inputs

■ Software selectable baud rate generator

Philips Semiconductors

■ Prescaler provides additional divide-by-4 function

■ Industrial temperature range (−40 °C to +85 °C)

■ Fast data bus access time

■ Programmable Sleep mode

■ Programmable serial interface characteristics

◆ 5-bit, 6-bit, 7-bit, or 8-bit characters

◆ Even, odd, or no parity bit generation and detection

◆ 1, 1.5, or 2 stop bit generation

■ False start bit detection

■ Complete status reporting capabilities in both normal and Sleep mode

■ Line break generation and detection

■ Internal test and loopback capabilities

■ Fully prioritized interrupt system controls

■ Modem control functions (CTS, RTS, DSR, DTR, RI, and CD)

3. Ordering information

SC68C752B

5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOs

Table 1: Ordering information

Type number Package

Name Description Version

SC68C752BIB48 LQFP48 plastic low proﬁle quad ﬂat package; 48 leads;

body 7 × 7 × 1.4 mm

SC68C752BIBS HVQFN32 plastic thermal enhanced very thin quad ﬂat package;

no leads; 32 terminals; body 5 × 5 × 0.85 mm

SOT313-2

SOT617-1

Product data sheet Rev. 03 — 29 November 2005 2 of 49

Philips Semiconductors

4. Block diagram

SC68C752B

5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOs

D0 to D7

R/W

RESET

A0 to A3

DATA BUS

AND

CONTROL

LOGIC

SELECT

LOGIC

AND

CONTROL SIGNALS

INTERCONNECT BUS LINES

TRANSMIT

FIFO

FLOW

CONTROL

LOGIC

RECEIVE

FIFO

FLOW

CONTROL

LOGIC

TRANSMIT

SHIFT

RECEIVE

SHIFT

TXA, TXB

RXA, RXB

DTRS, DTRB RTSA, RTSB OPA, OPB

MODEM

TXRDYA, TXRDYB

IRQ

RXRDYA, RXRDYB

INTERRUPT

CONTROL

LOGIC

CLOCK AND

BAUD RATE

GENERATOR

XTAL2XTAL1

CONTROL

LOGIC

002aab017

CTSA, CTSB RIA, RIB CDA, CDB DSRA, DSRB

Fig 1. Block diagram of SC68C752B

Product data sheet Rev. 03 — 29 November 2005 3 of 49

Philips Semiconductors

5. Pinning information

5.1 Pinning

SC68C752B

5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOs

RIA

DSRA

CTSA

n.c.

4847464544434241403938

D5 RESET

D6 DTRB

D7 DTRA

RXB RTSA

RXA OPA

TXRDYB RXRDYA

6 7

TXA IRQ

TXB n.c.

OPB A0

CS A1

A3 A2

n.c. n.c.

1314151617181920212223

XTAL1 D4

XTAL2 D3

Fig 2. Pin conﬁguration for LQFP48

terminal 1

index area

1 24

D6 RESET

2 23

D7 RTSA

3 22

RXB OPA

4 21

RXA IRQ

5 20

TXA n.c.

6 19

TXB A0

7 18

OPB

8 17

SC68C752BIB48

GND D0

RXRDYB TXRDYA

DSRB

R/W D2

CDB D1

D5D4D3D2D1D0V 32313029282726

SC68C752BIBS

10111213141516

XTAL1

XTAL2

Transparent top view

R/W

GND

n.c.

RIB CDA

RTSB

CTSB

CTSA 25

CTSB

36 35 34 33 32 31 30 29 28 27 26 25

002aab018

GND

A1 A2

002aac014

Fig 3. Pin conﬁguration for HVQFN32

Product data sheet Rev. 03 — 29 November 2005 4 of 49

Philips Semiconductors

SC68C752B

5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOs

5.2 Pin description

Table 2: Pin description

Symbol Pin Type Description

LQFP48 HVQFN32

A0 28 19 I Address 0 select bit. Internal registers address selection. A1 27 18 I Address 1 select bit. Internal registers address selection. A2 26 17 I Address 2 select bit. Internal registers address selection. A3 11 9 I Address 3. A3 is used to select Channel A or Channel B. A logic LOW

selects Channel A, and a logic HIGH selects Channel B. (See

CDA, CDB 40, 16 - I Carrier Detect (active LOW). These inputs are associated with

individual UART ChannelA and Channel B. A logic LOW on these pins indicates that a carrier has been detected by the modem for that channel. The state of these inputs is reﬂected in the Modem Status Register (MSR).

CS 10 8 I Chip Select (active LOW). This pin enables data transfers between the

user CPU and the SC68C752B for the channel(s) addressed. Individual UART sections (A, B) are addressed by A3. See

CTSA, CTSB 38, 23 25, 15 I Clear to Send (active LOW). These inputs are associated with

individual UART Channel A and Channel B. A logic 0 (LOW) on the pins indicates the modem or data set is ready to accept transmit data from the SC68C752B. Status can be tested by reading MSR[4]. These pins only affect the transmit and receive operations when Autofunction is enabled via the Enhanced Feature Register EFR[7] for hardware ﬂow control operation.

D0 to D7 44, 45, 46,

47, 48, 1, 2, 3

DSRA, DSRB 39, 20 - I Data Set Ready (active LOW). These inputs are associated with

DTRA, DTRB 34, 35 - O Data Terminal Ready (active LOW). These outputs are associated with

GND 17, 24 13 I Signal and power ground. IRQ 30 21 O Interrupt Request. Interrupts from UART Channel A and Channel B are

27, 28, 29, 30, 31, 32, 1, 2

I/O Data bus (bidirectional). These pins are the 8-bit, 3-state data bus for

transferring information to or from the controlling CPU. D0 is the least signiﬁcant bit and the ﬁrst data bit in a transmit or receive serial data stream.

individual UART ChannelA and Channel B. A logic 0 (LOW) on these pins indicates the modem or data set is powered-on and is ready for data exchange with the UART. The state of these inputs is reﬂected in the Modem Status Register (MSR).

individual UART ChannelA and Channel B. A logic 0 (LOW) on these pins indicates that the SC68C752B is powered-on and ready.Thesepins can be controlled via the Modem Control Register. Writing a logic 1 to MCR[0] will set the The output of these pins will be a logic 1 after writing a logic 0 to MCR[0], or after a reset.

wire-ORed internally to function as a single IRQ interrupt. This pin transitions to a logic 0 (if enabled by the Interrupt Enable Register) whenever a UART channel(s) requires service. Individual channel interrupt status can be determined by addressing each channel through its associated internal register, using resistor must be connected between this pin and V

DTR output to logic 0 (LOW), enabling the modem.

CS and A3. An external pull-up

Table 3.

Table 3.)

CTS

Product data sheet Rev. 03 — 29 November 2005 5 of 49

Philips Semiconductors

SC68C752B

5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOs

Table 2: Pin description

Symbol Pin Type Description

LQFP48 HVQFN32

R/W 15 12 I A logic LOW on this pin will transfer the contents of the data bus (D[0:7])

n.c. 12, 25, 29,3714, 20 - not connected

OPA, OPB 32, 9 22, 7 O User deﬁned outputs. This function is associated with individual

RESET 36 24 I Reset (active LOW). This pin will reset the internal registers and all the

RIA, RIB 41, 21 - I Ring Indicator (active LOW). These inputs are associated with

RTSA, RTSB 33, 22 23, 16 O Request to Send (active LOW). These outputs are associated with

RXA, RXB 5, 4 4, 3 I Receive data input. These inputs are associated with individual serial

RXRDYA, RXRDYB

TXA, TXB 7, 8 5, 6 O Transmit data A, B. These outputs are associated with individual serial

TXRDYA, TXRDYB

31, 18 - O Receive Ready (active LOW).

43, 6 - O Transmit Ready (active LOW).

…continued

from an external CPU to an internal register that is deﬁned by address bits A[0:2]. A logic HIGH on this pin will load the contents of an internal register deﬁned by address bits A[0:2] on the SC68C752B data bus (D[0:7]) for access by an external CPU.

Channel A and Channel B. The state of these pins is deﬁned by the user through the software settings of MCR[3]. MCR[3] is set to a logic 1. logic 0. The output of these two pins is HIGH after reset.

outputs. The UART transmitter output and the receiver input will be disabled during reset time. RESET is an active LOW input.

individual UART ChannelA and Channel B. A logic 0 on these pins indicates the modem has received a ringing signal from the telephone line. A LOW-to-HIGH transition on these input pins generates a modem status interrupt, if enabled. The state of these inputs is reﬂected in the Modem Status Register (MSR).

individual UART ChannelA and Channel B. A logic 0 on the indicates the transmitter has data ready and waiting to send. Writing a logic 1 in the Modem Control Register MCR[1] will set this pin to a logic 0, indicating data is available. After a reset these pins are set to a logic 1. These pins only affect the transmit and receive operations when Auto-

RTS function is enabled via the Enhanced Feature Register

(EFR[6]) for hardware ﬂow control operation.

channel data to the SC68C752B. During the local Loopback mode, these RX input pins are disabled and TX data is connected to the UART RX input internally.

the trigger level has been reached or the FIFO has at least one character. It goes HIGH when the RX FIFO is empty.

transmit channel data from the SC68C752B. During the local Loopback mode, the TX output pin is disabled and TX data is internally connected to the UART RX input.

there are at least a trigger level number of spaces available or when the FIFO is empty. It goes HIGH when the FIFO is full or not empty.

OPA/OPB is a logic 1 when MCR[3] is set to a

RXRDYA or RXRDYB goes LOW when

TXRDYA or TXRDYB go LOW when

OPA/OPB is a logic 0 when

RTS pin

Product data sheet Rev. 03 — 29 November 2005 6 of 49

Philips Semiconductors

SC68C752B

5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOs

Table 2: Pin description

Symbol Pin Type Description

LQFP48 HVQFN32

XTAL1 13 10 I Crystal or external clock input. Functions as a crystal input or as an

XTAL2 14 11 O Output of the crystal oscillator or buffered clock. (See also XTAL1.)

19, 42 26 I Power supply input.

…continued

external clock input. A crystal can be connected between XTAL1 and XTAL2 to form an internal oscillator circuit (see an external clock can be connected to this pin to provide custom data rates.

XTAL2 is used as a crystal oscillator output or a buffered clock output.

Table 3: Channel selection using CS pin

CS A3 UART channel

1 - none 0 0 Channel A 0 1 Channel B

Figure 13). Alternatively,

Product data sheet Rev. 03 — 29 November 2005 7 of 49

Philips Semiconductors

6. Functional description

The UART will perform serial-to-parallel conversion on data characters received from peripheral devices or modems, and parallel-to-parallel conversion on data characters transmitted by the processor. The complete status of each channel of the SC68C752B UART can be read at any time during functional operation by the processor.

The SC68C752B can be placed in an alternate mode (FIFO mode) relieving the processor of excessive software overhead by buffering received/transmitted characters. Both the receiver and transmitter FIFOs can store up to 64 bytes (including three additional bits of error status per byte for the receiver FIFO) and have selectable or programmable trigger levels. Primary outputs RXRDY and TXRDY allow signalling of DMA transfers.

The SC68C752B has selectable hardware ﬂow control and software ﬂow control. Hardware ﬂow control signiﬁcantly reduces software overhead and increases system efﬁciency by automatically controlling serial data ﬂow using the RTS output and CTS input signals. Software ﬂow control automatically controls data ﬂow by using programmable Xon/Xoff characters.

The UART includes a programmable baud rate generator that can divide the timing reference clock input by a divisor between 1 and (216− 1).

SC68C752B

5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOs

6.1 Trigger levels

The SC68C752B provides independent selectable and programmable trigger levels for both receiver and transmitter DMA and interrupt generation. After reset, both transmitter and receiver FIFOs are disabled and so, in effect, the trigger level is the default value of one byte. The selectable trigger levels are available via the FCR. The programmable trigger levels are available via the Trigger Level Register (TLR).

6.2 Hardware ﬂow control

Hardware ﬂow control is comprised of Auto-CTS and Auto-RTS. Auto-CTS and Auto-RTS can be enabled/disabled independently by programming EFR[7:6].

With Auto-CTS, CTS must be active before the UART can transmit data. Auto-RTSonly activates the RTSoutput when there is enough room in the FIFO to receive

data and de-activates the RTS output when the RX FIFO is sufﬁciently full. The halt and resume trigger levels in the TCR determine the levels at which RTS is activated/deactivated.

If both Auto-CTS and Auto-RTS are enabled, when RTS is connected to CTS, data transmission does not occur unless the receiver FIFO has empty space. Thus, overrun errors are eliminated during hardware ﬂow control. If not enabled, overrun errors occur if the transmit data rate exceeds the receive FIFO servicing latency.

Product data sheet Rev. 03 — 29 November 2005 8 of 49

Philips Semiconductors

SC68C752B

5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOs

UART 1 UART 2

SERIAL TO

PARALLEL

FIFO

FLOW

CONTROL

D7 to D0

PARALLEL TO SERIAL

FIFO

FLOW

CONTROL

RX TX

RTS CTS

TX RX

CTS RTS

Fig 4. Auto ﬂow control (Auto-RTS and Auto-CTS) example

6.2.1 Auto-RTS

Auto-RTSdata ﬂow control originates in the receiver block (see Figure 1 “Block diagram of

SC68C752B” on page 3). Figure 5 shows RTS functional timing. The receiver FIFO trigger

levelsused in Auto-RTS are stored in the TCR. RTS is active if the RX FIFO level is below the halt trigger level in TCR[3:0]. When the receiver FIFO halt trigger level is reached, RTS is de-asserted. The sending device (for example, another UART) may send an additional byte after the trigger level is reached (assuming the sending UART has another byte to send) because it may not recognize the de-assertion of RTS until it has begun sending the additional byte. RTS is automatically reasserted once the receiver FIFO reaches the resume trigger level programmed via TCR[7:4]. This re-assertion allows the sending device to resume transmission.

PARALLEL TO SERIAL

FIFO

FLOW

CONTROL

D7 to D0

SERIAL TO

PARALLEL

FIFO

FLOW

CONTROL

002aaa228

Start byte N Start byte N + 1 StartStop StopRX

RTS

R/W

(1) N = receiver FIFO trigger level. (2) The two blocks in dashed lines cover the case where an additional byte is sent, as described in Section 6.2.1.

NN + 112

002aab086

Fig 5. RTS functional timing

Product data sheet Rev. 03 — 29 November 2005 9 of 49

Philips Semiconductors

6.2.2 Auto-CTS

The transmitter circuitry checks CTS before sending the next data byte. When CTS is active, the transmitter sends the next byte. To stop the transmitter from sending the following byte, CTS must be de-asserted before the middle of the last stop bit that is currently being sent. The Auto-CTS function reduces interrupts to the host system. When ﬂow control is enabled, CTS level changes do not trigger host interrupts because the device automatically controls its own transmitter. Without Auto-CTS, the transmitter sends any data present in the transmit FIFO and a receiver overrun error may result.

SC68C752B

5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOs

Start byte 0 to 7 StopTX

CTS

(1) When CTS is LOW, the transmitter keeps sending serial data out. (2) When CTS goes HIGH before the middle of the last stop bit of the current byte, the transmitter ﬁnishes sending the current

byte, but is does not send the next byte.

(3) When CTS goes from HIGH to LOW, the transmitter begins sending data again.

Fig 6. CTS functional timing

Start byte 0 to 7 Stop

002aaa227

6.3 Software ﬂow control

Software ﬂow control is enabled through the Enhanced Feature Register and the Modem Control Register. Different combinations of software ﬂow control can be enabled by setting different combinations of EFR[3:0]. Table 4 shows software ﬂow control options.

Table 4: Software ﬂow control options (EFR[0:3])

EFR[3] EFR[2] EFR[1] EFR[0] TX, RX software ﬂow controls

0 0 X X no transmit ﬂow control 1 0 X X transmit Xon1, Xoff1 0 1 X X transmit Xon2, Xoff2 1 1 X X transmit Xon1, Xon2, Xoff1, Xoff2 X X 0 0 no receive ﬂow control X X 1 0 receiver compared Xon1, Xoff1 X X 0 1 receiver compares Xon2, Xoff2 1011transmit Xon1, Xoff1

receiver compares Xon1 and Xon2, Xoff1 and Xoff2

0111transmit Xon2, Xoff2

receiver compares Xon1 and Xon2, Xoff1 and Xoff2

1111transmit Xon1, Xon2, Xoff1, Xoff2

receiver compares Xon1 and Xon2, Xoff1 and Xoff2

Product data sheet Rev. 03 — 29 November 2005 10 of 49

Philips Semiconductors

There are two other enhanced features relating to software ﬂow control:

• Xon Any function (MCR[5]): Operation will resume after receiving any character

after recognizing the Xoff character. It is possible that an Xon1 character is recognized as an Xon Any character, which could cause an Xon2 character to be written to the RX FIFO.

• Special character (EFR[5]): Incoming data is compared to Xoff2. Detection of the

special character sets the Xoff interrupt (IIR[4]) but does not halt transmission. The Xoff interrupt is cleared by a read of the IIR. The special character is transferredto the RX FIFO.

6.3.1 Receive ﬂow control

When software ﬂow control operation is enabled, the SC68C752B will compare incoming data with Xoff1/Xoff2 programmed characters (in certain cases, Xoff1 and Xoff2 must be received sequentially). When the correct Xoff character are received, transmission is halted after completing transmission of the current character. Xoff detection also sets IIR[4] (if enabled via IER[5]) and causes IRQ to go HIGH.

To resume transmission, an Xon1/Xon2 character must be received (in certain cases Xon1 and Xon2 must be received sequentially). When the correct Xon characters are received, IIR[4] is cleared, and the Xoff interrupt disappears.

SC68C752B

5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOs

6.3.2 Transmit ﬂow control

Xoff1/Xoff2 character is transmitted when the RX FIFO has passed the HALTtrigger level programmed in TCR[3:0].

Xon1/Xon2 character is transmitted when the RX FIFO reaches the RESUME trigger level programmed in TCR[7:4].

The transmission of Xoff/Xon(s) follows the exact same protocol as transmission of an ordinary byte from the FIFO. This means that even if the word length is set to be 5, 6, or 7 characters, then the 5, 6, or 7 least signiﬁcant bits of Xoff1/Xoff2, Xon1/Xon2 will be transmitted. (Note that the transmission of 5, 6, or 7 bits of a character is seldom done, but this functionality is included to maintain compatibility with earlier designs.)

It is assumed that software ﬂow control and hardware ﬂow control will never be enabled simultaneously. Figure 7 shows an example of software ﬂow control.

Product data sheet Rev. 03 — 29 November 2005 11 of 49

Philips Semiconductors

6.3.3 Software ﬂow control example

SC68C752B

5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOs

UART2UART1

Fig 7. Software ﬂow control example

6.3.3.1 Assumptions

UART1 is transmitting a large text ﬁle to UART2. Both UARTs are using software ﬂow control with single character Xoff (0F) and Xon (0D) tokens. Both have Xoff threshold (TCR[3:0] = F) set to 60, and Xon threshold (TCR[7:4] = 8) set to 32. Both have the interrupt receive threshold (TLR[7:4] = D) set to 52.

TRANSMIT FIFO

PARALLEL-TO-SERIAL

SERIAL-TO-PARALLEL

Xon1 WORD

Xon2 WORD

Xoff1 WORD

Xoff2 WORD

data

Xoff–Xon–Xoff

compare

programmed

Xon-Xoff

characters

RECEIVE FIFO

SERIAL-TO-PARALLEL

PARALLEL-TO-SERIAL

Xon1 WORD

Xon2 WORD

Xoff1 WORD

Xoff2 WORD

002aaa229

UART1 begins transmission and sends 52 characters, at which point UART2 will generate an interrupt to its processor to service the RX FIFO, but assume the interrupt latency is fairly long. UART1 will continue sending characters until a total of 60 characters have been sent. At this time, UART2 will transmit a 0Fh to UART1, informing UART1 to halt transmission. UART1 will likely send the 61st character while UART2 is sending the Xoff character. Now UART2 is serviced and the processor reads enough data out of the RX FIFO that the level drops to 32. UART2 will now send a 0Dh to UART1, informing UART1 to resume transmission.

Product data sheet Rev. 03 — 29 November 2005 12 of 49

Philips Semiconductors

6.4 Reset

Table 5 summarizes the state of register after reset.

Table 5: Register reset functions

Interrupt Enable Register Interrupt Identiﬁcation Register FIFO Control Register Line Control Register Modem Control Register Line Status Register Modem Status Register Enhanced Feature Register Receiver Holding Register Transmitter Holding Register Transmission Control Register Trigger Level Register

SC68C752B

5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOs

RESET all bits cleared RESET bit 0 is set; all other bits cleared RESET all bits cleared RESET reset to 0001 1101 (1Dh) RESET all bits cleared RESET bits 5 and 6 set; all other bits cleared RESET bits 0 to 3 cleared; bits 4 to 7 input signals RESET all bits cleared RESET pointer logic cleared RESET pointer logic cleared RESET all bits cleared RESET all bits cleared

Remark: Registers DLL, DLH, SPR, XON1, XON2, XOFF1, XOFF2 are not reset by the top-level reset signal RESET, that is, they hold their initialization values during reset.

Table 6 summarizes the state of registers after reset.

Table 6: Signal

Signal Reset control Reset state

TX RTS RESET HIGH DTR RESET HIGH RXRDY RESET HIGH TXRDY RESET LOW

RESET functions

RESET HIGH

Product data sheet Rev. 03 — 29 November 2005 13 of 49

Philips Semiconductors

5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOs

6.5 Interrupts

The SC68C752B has interrupt generation and prioritization (six prioritized levels of interrupts) capability. The Interrupt Enable Register (IER) enables each of the six types of interrupts and the IRQ signal in response to an interrupt generation. The IER can also disable the interrupt system by clearing bits 0:3, 5:7. When an interrupt is generated, the IIR indicates that an interrupt is pending and provides the type of interrupt through IIR[5:0]. Table 7 summarizes the interrupt control functions.

Table 7: Interrupt control functions

IIR[5:0] Priority

level

000001 None none none none 000110 1 receiver line status OE, FE, PE, or BI errors occur in

001100 2 RX time-out stale data in RX FIFO read RHR 000100 2 RHR interrupt DRDY (data ready)

000010 3 THR interrupt TFE (THR empty)

000000 4 modem status MSR[3:0] = 0 read MSR 010000 5 Xoff interrupt receive Xoff character(s)/special

100000 6 CTS, RTS

Interrupt type Interrupt source Interrupt reset method

FE, PE, BI: all erroneous

characters in the RX FIFO

(FIFO disable) RX FIFO above trigger level (FIFO enable)

(FIFO disable) TX FIFO passes above trigger level (FIFO enable)

character RTSpin or CTS pin change state from

active (LOW) to inactive (HIGH)

characters are read from the RX FIFO.

OE: read LSR

read RHR

read IIR or a write to the THR

receive Xon character(s)/Read of IIR

read IIR

SC68C752B

It is important to note that for the framing error, parity error, and break conditions, LSR[7] generates the interrupt. LSR[7] is set when there is an error anywhere in the RX FIFO, and is cleared only when there are no more errors remaining in the FIFO. LSR[4:2] always represent the error status for the received character at the top of the RX FIFO. Reading the RX FIFO updates LSR[4:2] to the appropriate status for the new character at the top of the FIFO. If the RX FIFO is empty, then LSR[4:2] are all zeros.

For the Xoff interrupt, if an Xoff ﬂow character detection caused the interrupt, the interrupt is cleared by an Xon ﬂow character detection. If a special character detection caused the interrupt, the interrupt is cleared by a read of the IIR.

Product data sheet Rev. 03 — 29 November 2005 14 of 49

Philips Semiconductors

6.5.1 Interrupt mode operation

In Interrupt mode (if any bit of IER[3:0] is 1) the processor is informed of the status of the receiver and transmitter by an interrupt signal, IRQ. Therefore, it is not necessary to continuously poll the Line Status Register (LSR) to see if any interrupt needs to be serviced. Figure 8 shows Interrupt mode operation.

SC68C752B

5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOs

PROCESSOR

Fig 8. Interrupt mode operation

6.5.2 Polled mode operation

In Polled mode (IER[3:0] = 0000) the status of the receiver and transmitter can be checkedby polling the Line Status Register (LSR). This mode is an alternative to the FIFO Interrupt mode of operation where the status of the receiver and transmitter is automatically known by means of interrupts sent to the CPU. Figure 9 shows FIFO Polled mode operation.

R/W

IRQ

R/W

IIR

IER

1111

THR RHR

002aab096

IIR

PROCESSOR

IER

0000

THR RHR

002aab097

Fig 9. FIFO Polled mode operation

Product data sheet Rev. 03 — 29 November 2005 15 of 49

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