Philips SC68C562C1A, SC68C562C1N Datasheet

INTEGRATED CIRCUITS
SC68C562
CMOS dual universal serial communications controller (CDUSCC)
Product specification Supersedes data of 1994 Apr 27 IC19 Data Handbook
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Philips Semiconductors Product specification
CMOS Dual universal serial communications controller (CDUSCC)
DESCRIPTION
The Philips Semiconductors SC68C562 Dual Universal Serial Communications Controller (CDUSCC) is a single-chip CMOS-LSI communications device that provides two independent, multi-protocol, full-duplex receiver/transmitter channels in a single package. It supports bit-oriented and character-oriented (byte count and byte control) synchronous data link controls as well as asynchronous protocols. The SC68C562 interfaces to the 68000 MPUs via asynchronous bus control signals and is capable of program-polled, interrupt driven, block-move or DMA data transfers.
The SC68C562 is hardware (pin) and software (Register) compatible with SCN68562 (NMOS version). It will automatically configure to NMOS DUSCC register map on power-up or reset.
The operating mode and data format of each channel can be programmed independently. Each channel consists of a receiver, a transmitter, a 16-bit multifunction counter/timer, a digital phase-locked loop (DPLL), a parity/CRC generator and checker, and associated control circuits. The two channels share a common bit rate generator (BRG), operating directly from a crystal or an external clock, which provides 16 common bit rates simultaneously. The operating rate for the receiver and transmitter of each channel can be independently selected from the BRG, the DPLL, the counter/timer, or from an external 1X or 16X clock.
This makes the CDUSCC well suited for dual speed channel applications. Data rates up to 10Mb/s are supported.
Each transmitter and each receiver is serviced by a 16 byte FIFO. The receiver FIFO also stores 9 status bits for each character received; the transmit FIFO is able to store transmitter commands with each byte. This permits reading and writing of up to 16 bytes at a time, thus minimizing the
potential for transmitter underrun, receiver overrun and reducing interrupt or DMA overhead.
In addition, a flow control capability is provided to disable a remote transmitter when the FIFO of the local receiving device is full. Two modem control inputs (DCD and CTS) and three modem control outputs (RTS and two general purpose) are provided. Because the modem control inputs are general purpose in nature, they can be optionally programmed for other functions. This document contains the electrical specifications for the SC68C562. Refer to the CMOS Dual Universal Serial Communications Controller (CDUSCC) User Manual for a complete operational description of this product.
FEA TURES
Full hardware and software upward compatibility with previous
NMOS device
General Features
Dual full-duplex synchronous/ asynchronous receiver and
transmitter
Low power CMOS process
Multiprotocol operation
– BOP: HDLC/ADCCP, SDLC, SDLC loop, X.25 or X.75 link level,
etc.
COP: BISYNC, DDCMPASYNC: 5–8 bits plus optional parity
Sixteen character receiver and transmitter FIFOs
0 to 10MHz data rate
Programmable bit rate for each receiver and transmitter selectable
from:
19 fixed rates: 50 to 64k baudOne user-defined rate derived from programmable
counter/timer
External 1X or 16X clockDigital phase-locked loop
Parity and FCS (frame check sequence LRC or CRC) generation
and checking
Programmable data encoding/decoding: NRZ, NRZI, FM0, FM1,
Manchester
Programmable channel mode: full- and half-duplex, auto-echo, or
local loopback
Programmable data transfer mode: polled, interrupt, DMA, wait
DMA interface
– Compatible with the Philips Semiconductors SCB68430 Direct
Memory Access Interface (DMAI) and other DMA controllers
Single- or dual-address dual transfersHalf- or full-duplex operationAutomatic frame termination on counter/timer terminal count or
DMA DONE
Transmit path clear status
Interrupt capabilities
Daisy chain optionVector output (fixed or modified by status)Programmable internal prioritiesInterrupt at any FIFO fill levelMaskable interrupt conditions
FIFO’d status bits
Watchdog timer
Multi-function programmable 16-bit counter/timer
Bit rate generatorEvent counterCount received or transmitted charactersDelay generatorAutomatic bit length measurement
Modem controls
RTS, CTS, DCD, and up to four general I/O pins per channelCTS and DCD programmable auto-enables for Tx and RxProgrammable interrupt on change of CTS or DCD
On-chip oscillator for crystal
TTL compatible
Single +5V power supply
Asynchronous Mode Features
Character length: 5 to 8 bits
Odd or even parity, no parity, or force parity
Up to two stop bits programmable in 1/16-bit increments
SC68C562
1998 Sep 04 853-1682 19973
2
Philips Semiconductors Product specification
DESCRIPTION
DWG #
SYMBOL
PARAMETER
UNIT
CMOS Dual universal serial communications controller (CDUSCC)
1X or 16X Rx and Tx clock factors
Parity, overrun, and framing error detection
False start bit detection
Start bit search 1/2-bit time after framing error detection
Break generation with handshake for counting break characters
Detection of start and end of received break
Character compare with optional interrupt on match
Transmits up to 10Mb/s at 1X and receive up to 1Mb/s at 16X
data rates
Character-Oriented Protocol Features
Character length: 5 to 8 bits
Odd or even parity, no parity, or force parity
LRC or CRC generation and checking
Optional opening PAD transmission
One or two SYN characters
External sync capability
SYN detection and optional stripping
SYN or MARK line fill on underrun
Idle in MARK or SYNs
Parity, FCS, overrun, and underrun error detection
BISYNC Features
EBCDIC or ASCII header, text and control messages
SYN, DLE stripping
EOM (end of message) detection and transmission
Auto transparent mode switching
Auto hunt after receipt of EOM sequence (with closing PAD check
after EOT or NAK)
Control character sequence detection for both transparent and
normal text
Bit-Oriented Protocol Features
Character length: 5 to 8 bits
Detection and transmission of residual character: 0–7 bits
Automatic switch to programmed character length for I field
Zero insertion and deletion
Optional opening PAD transmission
Detection and generation of FLAG, ABORT, and IDLE bit patterns
Detection and generation of shared (single) FLAG between
frames
Detection of overlapping (shared zero) FLAGs
ABORT, ABORT-FLAGs, or FCS FLAGs line fill on underrun
Idle in MARK or FLAGs
Secondary address recognition including group and global
address
Single- or dual-octet secondary address
Extended address and control fields
Short frame rejection for receiver
Detection and notification of received end of message
CRC generation and checking
SDLC loop mode capability
SC68C562
ORDERING INFORMATION
VCC = +5V ±10%,
TA = 0 to +70°C
Serial Data Rate = 10Mbps Maximum
48-Pin Plastic Dual In-Line Package (DIP) SC68C562C1N Not available SOT240-1 52-Pin Plastic Leaded Chip Carrier (PLCC) Package SC68C562C1A SC68C562A8A SOT238-3
ABSOLUTE MAXIMUM RATINGS
T
A
T
STG
V
CC
V
S
1998 Sep 04
Operating ambient temperature Storage temperature -65 to +150 -65 to +150 °C Voltage from VCC to GND Voltage from any pin to ground
1
RATING
COMMERCIAL INDUSTRIAL
2
3
3
0 to +70 -40 to +85 °C
–0.5 to +7.0 –0.5 to +7.0 V
–0.5 to VCC +0.5 –0.5 to VCC +0.5 V
3
VCC = +5V ±10%, TA = –40 to +85°C
Serial Data Rate =
8Mbps Maximum
Philips Semiconductors Product specification
CMOS Dual universal serial communications controller (CDUSCC)
PIN CONFIGURATIONS
INDEX
CORNER
Pin Function Pin Function
1 IACKN 27 CSN 2 A3 28 R/WN 3 A2 29 DONEN 4A1 30D3 5 RTxDAKBN/ 31 D2
6 IRQN 33 D0 7NC 34NC 8 RESETN 35 CTSAN/LCAN 9 RTSBN/ 36 TxDRQAN/
10 TRxCB 37 RTxDRQAN/ 11 RTxCB GPO1AN 12 DCDBN/ 38 TxDAKAN/
13 NC 39 TxDA 14 RxDB 40 RxDA 15 TxDB 41 NC 16 TxDAKBN/ 42 DCDAN/
17 RTxDRQBN/ 43 RTxCA 18 TxDRQBN/ 45 RTSAN/ 19 CTSBN/LCBN 46 X2/IDCN
20 D7 47 X1/CLK 21 D6 48 RTxDAKAN/ 22 D5 GPI1AN 23 D4 49 A6 24 DTACKN 50 A5 25 DTCN 51 A4
26 GND 52 V
IACKN
RTxDAKBN/
GPI1BN
IRQN
RESETN
RTSBN/
SYNOUTBN
TRxCB RTxCB
DCDBN/
SYNIBN
RxDB
TxDB
TxDAKBN/
GPI2BN
RTxDRQBN/
GPO1BN
TxDRQBN/
GPO2BN/RTSBN
CTSBN/LCBN
DTACKN
DTCN
GND
1 2
A3
3
A2
4
A1
5 6 7 8
9 10 11 12 13 14 15 16 17 18
D7
19
D6
20
D5
21
D4
22 23
24
N PACKAGE
DIP
48
V
DD
47
A4
46
A5
45
A6 RTxDAKAN/
44
GPI1AN
43
X1/CLK
42
X2/IDCN RTSAN/
41
SYNOUTAN
40
TRxCA
39
RTxCA DCDAN/
38
SYNIAN
37
Rxda
36
TxDA TxDAKAN/
35
GPI2AN RTxDRQAN/
34
GPO1AN TxDRQAN/
33
GPO2AN/RTSAN
32
CTSAN/LCAN
31
D0
30
D1
29
D2
28
D3
27
DONEN
26
R/WN
25
CSN
SC68C562
A PACKAGE
7
8
PLCC
20
21
TOP VIEW
GPI1BN 32 D1
SYNOUTBN GPO2AN/RTSAN
SYNIBN GPI2AN
GPI2BN SYNIAN GPO1BN 44 TRxCA GPO2BN/RTSBN SYNOUTAN
47
1
46
34
33
DD
SD00222
1998 Sep 04
4
Philips Semiconductors Product specification
CMOS Dual universal serial communications controller (CDUSCC)
BLOCK DIAGRAM
DTACKN
RWN
A1-A6
CSN
RESETN
RTxDRQAN/GPO1AN RTxDRQBN/GPO1BN
TxDRQAN/GPO2AN TxDRQBN/GPO2BN RTxDAKAN/GPI1AN RTxDAKBN/GPI1BN
TxDAKAN/GPI2AN TxDAKBN/GPI2BN
DTCN
DONEN
TRxCA/B
RTxCA/B RTSBN/SYNOUTBN RTSAN/SYNOUTAN
CTSA/BN DCDBN/SYNIBN DCDAN/SYNIAN
D0-D7
DMA INTERFACE
BUS
BUFFER
A7 CONTROL
LOGIC
MPU
INTERFACE
SPECIAL
FUNCTION
PINS
INTERFACE/ OPERATION
CONTROL
ADDRESS
DECODE
R/W
DECODE
DMA
CONTROL
CCRA/B PCRA/B
RSRA/B TRSRA/B ICTSRA/B
GSR CMR1A/B CMR2A/B
OMRA/B TRCR A/B FTLR A/B
TRMR A/B
CID
CONTROL
INTERNAL BUS
CHANNEL MODE
AND TIMING A/B
DPLL CLK
MUX A/B
DPLL A/B
BRG
COUNTER/ TIMER A/B
C/T CLK
MUX A/B
CTCRA/B CTPRHA/B CTPRLA/B
CTHA/B CTLA/B
TRANSMIT A/B
TRANS CLK
MUX
TPRA/B TTRA/B
TX SHIFT
REG
TRANSMIT
16 DEEP
FIFO
TELRA/B
CRC
GEN
SPEC CHAR GEN LOGIC
SC68C562
TxD A/B
1998 Sep 04
IRQN
IACKN
X1/CLK
X2/IDCN
INTERRRUPT
CONTROL
ICRA/B IERA/B
IVR
IVRM
IER1 IER2
IER3
OSCILLATOR
DUSCC
LOGIC
RECEIVER A/B
RCVR CLK
MUX
RPRA/B RTRA/B S1RA/B S2RA/B
RCVR
SHIFT REG RECEIVER
16 DEEP
FIFO
RFLRA/B
CRC
ACCUM
BISYNC
COMPARE
LOGIC
RxD A/B
SD00253
5
Philips Semiconductors Product specification
MNEMONIC
TYPE
NAME AND FUNCTION
CMOS Dual universal serial communications controller (CDUSCC)
PIN DESCRIPTION
PIN NO.
DIP PLCC
A1–A6 4-2,
D0–D7 31-28,
R/WN 26 28 I Read/Write: A high input indicates a read cycle and a low indicates a write cycle when
CSN 25 27 I Chip Select: Active-low input. When active, data transfers between the CPU and the
IRQN 6 6 O Interrupt Request: Active-low, open-drain. This output is asserted upon occurrence of
IACKN 1 1 I Interrupt Acknowledge: Active-low. When IACKN is asserted, the CDUSCC responds
X1/CLK 43 47 I Crystal or External Clock: When using the crystal oscillator, the crystal is connected
X2/IDCN 42 46 O Crystal or Interrupt Daisy Chain: When a crystal is used as the timing source, the crystal
RESETN 7 8 I Master Reset: Active-low. A low on this pin resets the transmitters and receivers and
RxDA, RxDB 37, 12 40, 14 I Channel A (B) Receiver Serial Data Input: The least significant bit is received first. If
TxDA, TxDB 36, 13 39, 15 O Channel A (B) Transmitter Serial Data Output: The least significant bit is transmitted
RTxCA, RTxCB 39, 10 43, 11 I/O Channel A (B) Receiver/Transmitter Clock: As an input, it can be programmed to
TRxCA, TRxCB 40, 9 44, 10 I/O Channel A (B) Transmitter/Receiver Clock: As an input, it can supply the receiver,
CTSA/BN, LCA/BN
47-45
21-18
32, 17 35, 19 I/O Channel A (B) Clear-to-Send Input or Loop Control Output: Active-low. The signal
4-2,
51-49
33-30,
23-20
I Address Lines: Active-high. Address inputs which specify which of the internal registers
is accessed for read/write operation.
I/O Bidirectional Data Bus: Active-high, 3-State. Bit 0 is the LSB and bit 7 is the MSB. All
data, command and status transfers between the CPU and the CDUSCC take place over this bus. The data bus is enabled when CSN and R/WN or during interrupt acknowledge cycles and single address DMA acknowledge cycles.
CEN is active.
CDUSCC are enabled on D0–D7 as controlled by R/WN and A1–A6 inputs. When CSN is high, the data lines are placed in the 3-State condition (except during interrupt acknowledge cycles and single address DMA transfers).
any enabled interrupting condition. The CPU can read the general status register to determine the interrupting condition(s), or can respond with an interrupt acknowledge cycle to cause the CDUSCC to output an interrupt vector on the data bus.
by either forcing the bus into high-impedance, placing a vector number, call instruction or zero on the data bus. The vector number can be modified or unmodified by the status. If no interrupt is pending, IACKN is ignored and the data bus placed in high-impedance.
between pins X1 and X2. If a crystal is not used, an external clock is supplied at this input. This clock is used to drive the internal bit rate generator, as an optional input to the counter/timer or DPLL, and to provide other required clocking signals. When a crystal is used, a capacitor must be connected from this pin to ground.
is connected between pins X1 and X2. This pin can be programmed to provide an interrupt daisy chain active-low output which propagates the IACKN signal to lower priority devices, if no active interrupt is pending. This pin should be left floating when an external clock is used on X1 and X2 is not used as an interrupt daisy chain output. When a crystal is used, a capacitor must be connected from this pin to ground.
resets the registers shown in Table 1 of the CDUSCC Users’ Guide. Reset is asynchronous, i.e., no clock is required.
external receiver clock is specified for the channel, the input is sampled on the rising edge of the clock.
first. This output is in the marking (high) condition when the transmitter is disabled or when the channel is operating in local loopback mode. If external transmitter clock is specified for the channel, the data is shifted on the falling edge of the clock.
supply the receiver, transmitter, counter/timer, or DPLL clock. As an output, it can supply the counter/timer output, the transmitter shift clock (1X), or the receiver sampling clock (1X).
transmitter, counter/timer, or DPLL clock. As an output, it can supply the counter/timer output, the DPLL output, the transmitter shift clock (1X), the receiver sampling clock (1X), the transmitter BRG clock (16X), The receiver BRG clock (16X), or the internal system clock (X1 ÷ 2).
can be programmed to act as an enable for the transmitter when not in loop mode. The CDUSCC detects logic level transitions on this input and can be programmed to generate an interrupt when a transition occurs. When operating in the BOP loop mode, this pin be­comes a loop control output which is asserted and negated by CDUSCC commands. This output provides the means of controlling external loop interface hardware to go on-line and off-line without disturbing operation of the loop.
SC68C562
1998 Sep 04
6
Philips Semiconductors Product specification
MNEMONIC
TYPE
NAME AND FUNCTION
CMOS Dual universal serial communications controller (CDUSCC)
PIN DESCRIPTION (Continued)
PIN NO.
DIP PLCC
DCDA/BN, SYNIA/BN
RTxDRQA/BN, GPO1A/BN
TxDRQA/BN, GPO2A/BN, RTSA/BN
RTxDAKA/BN, GPI1A/BN
TxDAKA/BN, GPI2A/BN
DONEN 27 29 I/O Done: Active-low, open-drain. DONEN can be used and is active in both DMA and
RTSA/BN, SYNOUTA/BN
DTACKN 22 24 O Data T ransfer Acknowledge: Active-low, 3-state. DTACKN is asserted on a write cycle to
DTC 23 25 I Device Transfer Complete: Active-low. DTCN is asserted by the DMA controller to
V
CC
GND 24 26, 13,
38, 11 42, 12 I Channel A (B) Data Carrier Detected or External Sync Input: The function of this pin is
programmable. As a DCD active-low input, it acts as an enable for the receiver or can be used as a general purpose input. For the DCD function, the CDUSCC detects logic level transitions on this pin and can be programmed to generate an interrupt when a transition occurs. As an active-low external sync input, it is used in COP mode to obtain character synchronization for the receiver without receipt of a SYN character. This mode can be used in disc or tape controller applications or for the optional byte timing lead in X.21.
34, 15 37, 17 O Channel A (B) Receiver/Transmitter DMA Service Request or General Purpose
Output: Active-low. For half-duplex DMA operation, this output indicates to the DMA controller that one or more characters are available in the receiver FIFO (when the receiver is enabled) or that the transmit FIFO is not full (when the transmitter is enabled). For full-duplex DMA operation, this output indicates to the DMA controller that data is available in the receiver FIFO. In non-DMA mode, this pin is a general purpose output that can be asserted and negated under program control.
33, 16 36, 18 O Channel A (B) Transmitter DMA Service Request, General Purpose Output, or
Request-to-Send: Active-low. For full-duplex DMA operation, this output indicates to the DMA controller that the transmit FIFO is not full and can accept more data. When not in full-duplex DMA mode, this pin can be programmed as a general purpose or a Request-to-Send output, which can be asserted and negated under program control.
44, 5 48, 5 I Channel A (B) Receiver/Transmitter DMA Acknowledge or General Purpose Input:
Active-low. For half-duplex single address operation, this input indicates to the CDUSCC that the DMA controller has acquired the bus and that the requested bus cycle (read receiver FIFO when the receiver is enabled or load transmitter FIFO when the transmitter is enabled) is beginning. For full-duplex single address DMA operation, this input indicates to the CDUSCC that the DMA controller has acquired the bus and that the requested read receiver FIFO bus cycle is beginning. Because the state of this input can be read under program control, it can be used as a general purpose input when not in single address DMA mode.
35, 14 38, 16 I Channel A (B) Transmitter DMA Acknowledge or General Purpose Input: Active-low.
When the channel is programmed for full-duplex single address DMA operation, this input is asserted to indicate to the CDUSCC that the DMA controller has acquired the bus and that the requested load transmitter FIFO bus cycle is beginning. Because the state of this input can be read under program control, it can be used as a general purpose input when not in full-duplex single address DMA mode.
non-DMA modes. As an input, DONEN indicates the last DMA transfer cycle to the TxFIFO. As an output, DONEN indicates either the last DMA transfer from the RxFIFO or that the transmitted character count has reached terminal count.
41, 8 45, 9 O Channel A (B) Sync Detect or Request-to-Send: Active-low. If programmed as a sync
output, it is asserted one bit time after the specified sync character (COP or BISYNC modes) or a FLAG (BOP modes) is detected by the receiver. As a Request-to-Send modem control signal, it functions as described previously for the TxDRQN/RTSN pin.
indicate that the data on the bus has been latched, and on a read cycle or interrupt acknowledge cycle to indicate valid data is on the bus. In a write bus cycle, input data is latched by the assertion (falling edge) of DTACKN or by the negation (rising edge) of CSN, whichever occurs first. The signal is negated when completion of the cycle is indicated by negation of CSN or IACKN input, and returns to the inactive state (3-state) a short period after it is negated. In single address DMA mode, input data is latched by the assertion (falling edge) of DTCN or by the negation (rising edge) of the DMA acknowledge input, whichever occurs first. DTACK is negated when completion of the cycle is indicated by the assertion of DTCN or negation of DMA acknowledge inputs (whichever occurs first), and returns to the inactive state (3-state) a short period after it is negated. When inactive, DTACKN requires an external pull-up resistor.
indicate that the requested data transfer is complete.
48 34, 52 I +5V Power Input
I Signal and Power Ground Input
41, 7
SC68C562
1998 Sep 04
7
Philips Semiconductors Product specification
SYMBOL
PARAMETER
TEST CONDITIONS
UNIT
CMOS Dual universal serial communications controller (CDUSCC)
DC ELECTRICAL CHARACTERISTICS
V
IL
V
IH
V
OL
V
OH
I
ILX1
I
IHX1
I
SCX2
I
IL
I
L
I
OZH
I
OZL
I
ODL
I
ODH
I
CC
C
IN
C
OUT
C
I/O
NOTES:
1. Stresses above those listed under Abs. Max Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation section of this specification is not implied.
2. Clock may be stopped (DC) for testing purposes or when the CDUSCC is in non-operational modes. Operation down to 0 rate clocks is implied by a full static CMOS design, but is not verified in testing or characterization.
3. This product includes circuitry specifically designed for the protection of its internal devices from damaging effects of excessive static charge. Nonetheless, it is suggested that conventional precautions be taken to avoid applying any voltages larger than the rated maxima.
4. Parameters are valid over specified temperature and voltage range.
5. All voltage measurements are referenced to ground (GND). For testing, all inputs except X1/CLK swing between 0.2V and 3.0V with a transi­tion time of 20ns maximum. For X1/CLK, this swing is between 0.2V and 4.4V . All time measurements are referenced at input volta ges of
0.2V and 3.0V and output voltages of 0.8V and 2.0V , as appropriate.
6. See Figure 18 for test conditions for outputs.
7. Tests for open drain outputs are intended to guarantee switching of the output transistor. To include noise margin this response is measured from the switching signal midpoint to 0.2 V above the required output level.
8. Execution of the valid command (after it is latched) requires a minimum of three rising edges of X1 (see Figure 19).
9. These values were no explicitly tested; they are guaranteed by design and characterization data.
10.X1/CLK and X2 are not tested with a crystal installed.
11.X1/CLK frequency must be at least as fast as the faster of the receiver or transmitter data rate.
12.The X1 clock drives DTACKN, Baud Rate Generator, command register and the update of the FIFO fill level encoders. The Command Register requires three X1 clocks between two commands; FIFO fill level encoding requires 2.5 to 3.5 X1 cycles.
13.The 68562 bus interface may be operated in two modes; a 68000 compatible mode with automatic DTACK generation and a short chip select mode. DTACKN should not be used externally in the short chip select mode. The DTACKN signal is generated by the assertion of the chip select, and data is latched by assertion of DTACKN or by de-assertion of the chip select, whichever comes first. In single address DMA, the DTACK signal will be de-asserted by the assertion of the DTCN or from the de-assertion of the TxDAKN, whichever occurs first.
14.Also includes X2/IDCN pin in IDC mode.
15.In case of 3-state output, output levels V
16.V
Input low voltage: All except X1/CLK
X1/CLK Input high voltage: All except X1/CLK
X1/CLK Output low voltage:
All except IRQN
IRQN Output high voltage:
14
7
14
(Except open drain outputs)
X1/CLK input low current X1/CLK input high current
10
10
X2 short circuit current (X2 mode) X1 open VIN = 0
Input low current RESETN, DTCN, TxDAKA/BN, RTxDAKA/BN
Input leakage current
Output off current high, 3-State data bus
Output off current low , 3-State data bus
Open drain output low current in off state: DONEN, DTACKN (3-state)
6
Open drain output high current in off state:
IRQN DONEN, IRQN, DTACKN (3-state)
Power supply current
16
(See Figure 17 for graphs) Input capacitance
Output capacitance Input/output capacitance
= 0 to VCC, Rx/Tx at 10MHz and X1 at 10MHz
O
9
9
9
4, 5
TA = 0 to +70°C, –40 to +85C, VCC = 5.0V 10%
0 to 70C
–40 to 85C
IOL = 5.3mA (Comm), 4.8mA I
OL
(Indus)
= 8.8mA (Comm), 7.8mA
(Indus)
I
= -400µA
OH
VIN = 0, X2 = GND
VIN = VCC, X2 = GND
VIN = V
CC
VIN = 0 -15 –0.5 µA
VIN = 0 to V
–40 to 85C
VIN = V
–40 to 85C
VIN = 0
–40 to 85C
CC,
0 to 70C
CC,
0 to 70C
,
0 to 70C
VIN = 0
VIN = V
CC
0 to 70C
–40 to 85C
VCC = GND = 0 VCC = GND = 0 V
= GND = 0
CC
+ 0.2 are considered float or high impedance.
OL
LIMITS
Min Typ Max
2.0
2.3
0.8xV
CC
VCC–0.5
–150 0.0
-1
–10
-1
–10
-15
-1
–1
SC68C562
0.8
0.8
V
0.5
0.5
150 –15
+15
+1
+10
+1
+10
-0.5
+1
25 80
95 10
15 20
CC
V V V V V
V V
V
µA µA
mA mA
µA
µA µA
µA µA
µA µA
µA
mA
pF pF pF
1998 Sep 04
8
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