Philips SAA7345 User Manual

INTEGRATED CIRCUITS

DATA SH EET

SAA7345

CMOS digital decoding IC with
RAM for Compact Disc

Product specification
Supersedes data of 1996 Jan 09
File under Integrated Circuits, IC01

1998 Feb 16

Philips Semiconductors Product specification

CMOS digital decoding IC with RAM for
Compact Disc

FEATURES

• Integrated data slicer and clock regenerator

• Digital Phase-Locked Loop (PLL)

• Demodulator and Eight-to-Fourteen Modulation (EFM)

decoding

• Subcoding microcontroller serial interface

• Integrated programmable motor speed control

• Error correction and concealment functions

• Embedded Static Random Access Memory (SRAM) for

de-interleave and First-In First-Out (FIFO)

• FIFO overflow concealment for rotational shock
resistance

• Digital audio interface [European Broadcasting Union
(EBU)]

• 2 to 4 times oversampling integrated digital filter

• Audio data peak level detection

• Versatile audio data serial interface

• Digital de-emphasis filter

• Kill interface for Digital-to-Analog Converter (DAC)

deactivation during digital silence

• Double speed mode

• Compact Disc Read Only Memory (CD-ROM) modes

• A single speed only version is available

(SAA7345GP/SS).

SAA7345

GENERAL DESCRIPTION

The SAA7345 incorporates the CD signal processing
functions of decoding and digital filtering. The device is
equipped with on-board SRAM and includes additional
features to reduce the processing required in the analog
domain.

Supply of this Compact Disc IC does not convey an implied
license under any patent right to use this IC in any
Compact Disc application.

QUICK REFERENCE DATA

SYMBOL PARAMETER MIN. TYP. MAX. UNIT

V

DD

I

DD

f

xtal

T

amb

T

stg

ORDERING INFORMATION

TYPE

NUMBER

SAA7345GP QFP44 plastic quad flat package; 44 leads (lead length 2.35 mm); body

1998 Feb 16 2

supply voltage 3.4 5.0 5.5 V
supply current − 22 50 mA
crystal frequency 8 16.9344 or

33.8688
operating ambient temperature −40 − +85 °C
storage temperature −55 − +125 °C

PACKAGE

NAME DESCRIPTION VERSION

14 × 14 × 2.2 mm

35 MHz

SOT205-1

Philips Semiconductors Product specification

CMOS digital decoding IC with RAM for
Compact Disc

BLOCK DIAGRAM

V

V

SSA

DDA

11 12 15 16 44 43

8

HFIN

HFREF

ISLICE

IREF

TEST1
TEST2

CRIN

CROUT

CL11

CLA

CL16

CL

DA

RAB

PORE

9

PLL

FRONT-

7

END

10
6

5
13
14
1

TIMING

29
17

31

MICRO-

30

CONTROLLER

INTERFACE

32

28

DIGITAL

PLL

EFM

DEMODULATOR

SRAM

RAM

ADDRESSER

Q - CHANNEL

CRC CHECK

Q - CHANNEL

REGISTER

VERSATILE PINS

INTERFACE

3 4 26 25 24 27
V1 V2

V

DD1

V

SS1

SUBCODE

PROCESSOR

SAA7345

PEAK

DETECT

V

V

DD2

MOTOR

CONTROL

ERROR

CORRECTOR

FLAGS

AUDIO

KILL

KILLV3 V4 V5

SS2

EBU

INTER-

FACE

SERIAL

DATA

INTER-

FACE

MGA371 - 2

SAA7345

MOTO1

22
23

MOTO2

CFLG

33

2

DOBM

21

SCLK
WCLK

20
19

DATA

18

MISC

Fig.1 Block diagram.

1998 Feb 16 3

Philips Semiconductors Product specification

CMOS digital decoding IC with RAM for
Compact Disc

PINNING

SYMBOL PIN DESCRIPTION

CL11 1 11.2896 or 5.6448 MHz clock output (3-state); (divide-by-3)
DOBM 2 bi-phase mark output (externally buffered; 3-state)
V1 3 versatile input pin
V2 4 versatile input pin
TEST2 5 test input; this pin should be tied LOW
TEST1 6 test input; this pin should be tied LOW
ISLICE 7 current feedback output from data slicer
HFIN 8 comparator signal input
HFREF 9 comparator common-mode input
IREF 10 reference current pin (nominally
V
V

DDA
SSA

11 analog supply voltage; note 1

12 analog ground; note 1
CRIN 13 crystal/resonator input
CROUT 14 crystal/resonator output
V
V

DD1
SS1

15 digital supply to input and output buffers; note 1

16 digital ground to input and output buffers; note 1
CL16 17 16.9344 MHz system clock output
MISC 18 general purpose DAC output (3-state)
DATA 19 serial data output (3-state)
WCLK 20 word clock output (3-state)
SCLK 21 serial bit clock output (3-state)
MOTO1 22 motor output 1; versatile (3-state)
MOTO2 23 motor output 2; versatile (3-state)
V5 24 versatile output pin
V4 25 versatile output pin
V3 26 versatile output pin (open-drain)
KILL 27 kill output; programmable (open-drain)
PORE 28 power-on reset enable input (active LOW)
CLA 29 4.2336 MHz microcontroller clock output
DA 30 interface data I/O line
CL 31 interface clock input line
RAB 32 interface R/

W and acknowledge input
CFLG 33 correction flag output (open-drain)
n.c. 34 to 42 no internal connection
V
V

SS2
DD2

43 digital ground to internal logic; note 1
44 digital supply voltage to internal logic; note 1

1

⁄2VDD)

SAA7345

Note

1. All supply pins must be connected to the same external power supply.

1998 Feb 16 4

Philips Semiconductors Product specification

CMOS digital decoding IC with RAM for
Compact Disc

Pins 34 to 42 (inclusive)

have no internal connection

SS2

DD2

V

V

CL11

DOBM

V1

V2
TEST2
TEST1
ISLICE

HFIN

HFREF

IREF

V

DDA

44

1
2
3
4
5
6
7
8

9
10
11

41

40

43

42

39

SAA7345

SAA7345

38

37

36

35

34

33

CFLG

32

RAB

31

CL

30

DA

29

CLA

28

PORE

27

KILL

26

V3

25

V4

24

V5

23

MOTO2

12

13

14

15

16

SSA

V

CRIN

DD1

V

CROUT

SS1

V

Fig.2 Pin configuration.

17

CL16

18

MISC

19

DATA

20

WCLK

21

SCLK

22

MOTO1

MGA359 - 1

1998 Feb 16 5

Philips Semiconductors Product specification

CMOS digital decoding IC with RAM for
Compact Disc

FUNCTIONAL DESCRIPTION
Demodulator

RAME SYNC PROTECTION

F
This circuit will detect the frame synchronization signals.

Two synchronization counters are used in the SAA7345:

1. The coincidence counter which is used to detect the
coincidence of successive syncs. It generates a Sync
coincidence signal if 2 syncs are 588 ±1 EFM clocks
apart.

2. The main counter is used to partition the EFM signal
into 17-bit words. This counter is reset when:

a) A Sync coincidence is generated.
b) A sync is found within ±6 EFM clocks of its

expected position.

The Sync coincidence signal is also used to generate the
Lock signal which will go active HIGH when 1 Sync
coincidence is found. It will reset to LOW when, during 61
consecutive frames, no Sync coincidence is found. This
Lock signal is accessed via the status signal when the
status control register (address 0010) is set to X100. See
section on “Microcontroller interface” .

Data Slicer and Clock Regenerator

The SAA7345 has an integrated slice level comparator
which is clocked by the crystal frequency clock. The slice
level is controlled by an internal current source applied to
an external capacitor under the control of the digital
phase-locked loop (DPLL).

SAA7345

Regeneration of the bit clock is achieved with an internal
fully digital PLL. No external components are required and
the bit clock is not output. The PLL has two microcontroller
control registers (addresses 1000 and 1001) for
bandwidth and equalization.

For certain applications an off-track input is necessary. If
this flag is HIGH, the SAA7345 will assume that the servo
is following on the wrong track, and will flag all incoming
HF data as incorrect. The off-track is input via the V1 pin
when the versatile pins interface register (address 1100)
bit 0 is set to logic 1.

EFM demodulation

The 14-bit EFM data and subcode words are decoded into
8-bit symbols.

Subcode data processing

Q-

CHANNEL PROCESSING

The 96-bit Q-channel word is accumulated in an internal
buffer. Sixteen bits are used to perform a Cyclic
Redundancy Check (CRC). If the data is good, the
SUBQREADY-I signal will go LOW. SUBQREADY-I can
be read via the status signal when the status control
register (address 0010) is set to X000 (normal reset
condition). Good Q-channel data may be read via the
microcontroller interface.

HF

input

2.2 nF

2.2 kΩ

22 kΩ

100 nF

V

47 pF

22 nF

SSA

V

SSA

HFIN

HFREF

I

ref

ISLICE

1/2V

Fig.3 Data slicer showing typical application components.

1998 Feb 16 6

DD

100 µA

100 µA

crystal

clock

DQ

V

SS

V

DD

DPLL

MGA368 - 1

Philips Semiconductors Product specification

CMOS digital decoding IC with RAM for
Compact Disc

OTHER SUBCODE CHANNELS
Data of the other subcode channels (Q-to-W) may be read

via the V4 pin if the versatile pins interface register
(address 1101) is set to XX01.

The format is similar to RS232. The subcode sync word is
formed by a pause of 200 µs minimum. Each subcode byte
starts with a logic 1 followed by 7 bits (Q-to-W). The gap
between bytes is variable between 11.3 µs and 90 µs.

The subcode data is also available in the EBU output
(DOBM) in a similar format.

Microcontroller interface

The SAA7345 has a 3-line microcontroller interface which
is compatible with the digital servo IC TDA1301.

RITING DATA TO SAA7345

W
The SAA7345 has thirteen 4-bit programmable

configuration registers as shown in Table 2. These can be
written to via the microcontroller interface using the
protocol shown in Fig.5.

SAA7345

Write operation sequence

• RAB is held LOW by the microcontroller to hold the
SAA7345 DA pin at high-impedance.

• Microcontroller data is clocked into the internal shift
register on the LOW-to-HIGH clock transition CL.

• Data D (3 : 0) is latched into the appropriate control
register [address bits A (3 : 0)] on the LOW-to-HIGH
transition of RAB with CL HIGH.

• If more data is clocked into SAA7345 before the
LOW-to-HIGH transition of RAB then only the last 8 bits
are used.

• If less data is clocked into SAA7345, unpredictable
operation will result.

• If the LOW-to-HIGH transition of RAB occurs with CL
LOW, the command will be disregarded.

200 µs

min

W96 1 Q1 R1 S1 T1 U1 V1 W1 1 Q2

11.3
µs

11.3 µs min
90 µs max

Fig.4 Subcode format and timing at V4 pin.

RAB

(microcontroller)

CL

(microcontroller)

DA

(microcontroller)

DA (SAA7345)

A3 A2 A1 A0 D3 D2 D1 D0

high impedance

Fig.5 Microcontroller WRITE timing.

MGA369

MGA379 - 1

1998 Feb 16 7

Philips Semiconductors Product specification

CMOS digital decoding IC with RAM for

SAA7345

Compact Disc

WRITING DATA TO SAA7345; REPEAT MODE
The same command can be repeated several times (e.g. for fade function) by applying extra RAB pulses as shown in

Fig.6.

RAB

(microcontroller)

CL

(microcontroller)

DA

(microcontroller)

DA (SAA7345)

Note that CL must stay HIGH between RAB pulses.

A3 A2 A1 A0 D3 D2 D1 D0

high impedance

MGA380 - 1

Fig.6 Microcontroller WRITE timing; repeat mode.

EADING STATUS INFORMATION FROM SAA7345

R
There are several internal status signals which can be made available on the DA line (Table 1).

Table 1 Internal status signals.

SIGNAL DESCRIPTION

SUBQREADY-I LOW if new subcode word is ready in Q-channel register.
MOTSTART1 HIGH if motor is turning at 75% or more of nominal speed.
MOTSTART2 HIGH if motor is turning at 50% or more of nominal speed.
MOTSTOP HIGH if motor is turning at 12% or less of nominal speed.
PLL Lock HIGH if Sync coincidence signals are found.
V1 Follows input on V1 pin.
V2 Follows input on V2 pin.
MOTOR-OV HIGH if the motor servo output stage saturates.

The status signal to be output is selected by status control register (address 0010). The timing for reading the status
signal is shown in Fig.7.

Status read operation sequence

• Write appropriate data to register 0010 to select required status signal.

• With RAB LOW; set CL LOW.

• Set RAB HIGH; this will instruct the SAA7345 to output status signal on DA.

1998 Feb 16 8

Philips Semiconductors Product specification

CMOS digital decoding IC with RAM for

SAA7345

Compact Disc

RAB

(microcontroller)

CL

(microcontroller)

DA

(microcontroller)

DA (SAA7345)

Fig.7 SAA7345 status READ timing.

READING Q-CHANNEL SUBCODE FROM SAA7345
To read Q-channel subcode from SAA7345, the SUBQREADY-I signal should be selected as status signal. The subcode

read timing is shown in Fig.8.

high impedance

STATUS

MGA381 - 1

Read subcode operation sequence

• Monitor SUBQREADY-I status signal.

• When this signal is LOW, and up to 2.3 ms after its LOW-to-HIGH transition, it is permitted to read subcode.

• Set CL LOW, SAA7345 will output first subcode bit (Q1).

• After subcode read starts, the microcontroller may take as long as it wants to terminate read operation.

• SAA7345 will output consecutive subcode bits after each HIGH-to-LOW transition of CL.

• When enough subcode has been read (1 to 96 bits), stop reading by pulling RAB LOW.

RAB

(microcontroller)

CL

(microcontroller)

CRC

OK

Q1 Q2 Q3 Qn–1DA (SAA7345)

STATUS

Qn–2 Qn

MGA382 - 1

Fig.8 SAA7345 Q-channel subcode READ timing.

EAK DETECTOR OUTPUT

P
In place of the CRC-bits (bits 81 to 96), the peak detector information is added to the Q-channel data. The peak

information corresponds to the highest audio level (absolute value) and is measured on positive peaks. Only the most
significant 8 bits of the peak level are given, in unsigned notation. Bits 81 to 88 contain the LEFT peak value
(bit 88 = MSB) and bits 89 to 96 contain the RIGHT channel (bit 96 = MSB). Value is reset after reading Q-channel data.

1998 Feb 16 9

Philips Semiconductors Product specification

CMOS digital decoding IC with RAM for
Compact Disc

BEHAVIOUR OF THE SUBQREADY-I SIGNAL
When the CRC of the Q-channel word is good, and no

subcode is being read, the SUBQREADY-I signal will react
as shown in Fig.9.

When the CRC is good and subcode is being read, the
timing in Fig.10 applies.

If t1 (SUBQREADY-I LOW to end of subcode read) is
below 2.6 ms, then t2= 13.1 ms (i.e. the microcontroller
can read all subcode frames if it completes the read
operation within 2.6 ms after subcode ready).

If this criterion is not met, it is only possible to guarantee

will be below 26.2 ms (approximately).

that t

3

If subcode frames with failed CRCs are present, the t2 and
t3 times will be increased by 13.1 ms for each defective
subcode frame.

SAA7345

S

HARING THE MICROCONTROLLER INTERFACE

When the RAB pin is held LOW by the microcontroller, it is
permitted to put any signal on the DA and CL lines
(SAA7345 will set output DA to high-impedance). Under
this circumstance these lines may be used for another
purpose (e.g. TDA1301 microcontroller interface Data and
Clock line, see Fig.11).

RAB

(microcontroller)

CL

(microcontroller)

DA (SAA7345)

RAB

(microcontroller)

CL

(microcontroller)

high

impedance

CRC OK CRC OK

10.8 ms 15.4 ms

READ start allowed

2.3
ms

Fig.9 SUBQREADY-I timing when no subcode is read.

t

t

1

Q1 Q2 Q3 QnDA (SAA7345)

2

MGA373 - 1

t

3

MGA374 - 1

Fig.10 SUBQREADY-I timing when subcode is being read.

1998 Feb 16 10

Philips Semiconductors Product specification

CMOS digital decoding IC with RAM for

SAA7345

Compact Disc

TDA1301 SAA7345

SIDA

SICL

SILD

I/O

O

MICROCONTROLLER

O
O

Fig.11 SAA7345 microcontroller interface application diagram.

Table 2 Command registers.
The ‘INITIAL’ column shows the power-on reset state

REGISTER ADDRESS DATA FUNCTION INITIAL

Fade and Attenuation 0 0 0 0 X 0 0 0 Mute Reset

X 0 1 X Attenuate
X 0 0 1 Full Scale
X 1 0 0 Step Down
X 1 0 1 Step Up

Motor mode 0 0 0 1 X 0 0 0 Motor off mode Reset

X 0 0 1 Motor brake mode 1
X 0 1 0 Motor brake mode 2
X 0 1 1 Motor start mode 1
X 1 0 0 Motor start mode 2
X 1 0 1 Motor jump mode
X 1 1 1 Motor play mode
X 1 1 0 Motor jump mode 1
1 X X X anti-windup active
0 X X X anti-windup off Reset

Status control 0 0 1 0 X 0 0 0 status = SUBQREADY-I Reset

X 0 0 1 status = MOTSTART1
X 0 1 0 status = MOTSTART2
X 0 1 1 status = MOTSTOP
X 1 0 0 status = PLL Lock
X 1 0 1 status = V1
X 1 1 0 status = V2
X 1 1 1 status = MOTOR-OV
0 X X X L channel first at DAC (WCLK normal) Reset
1 X X X R channel first at DAC (WCLK inverted)

DACLRAB

MGA361 - 1

1998 Feb 16 11

Philips Semiconductors Product specification

CMOS digital decoding IC with RAM for

SAA7345

Compact Disc

REGISTER ADDRESS DATA FUNCTION INITIAL

DAC output 00 1 1 1 0 1 0 I2S CD-ROM mode

1 0 1 1 EIAJ; CD-ROM mode

110 X I

1111 I
1110 I

0 0 0 X EIAJ; 16-bit; 4f

0 0 1 1 EIAJ; 16-bit; 2f
0 0 1 0 EIAJ; 16-bit; f

0 1 0 X EIAJ; 18-bit; 4f

0 1 1 1 EIAJ; 18-bit; 2f
0 1 1 0 EIAJ; 18-bit; f

Motor gain 0 1 0 0 X 0 0 0 Motor gain G = 3.2 Reset

X 0 0 1 Motor gain G = 4.0
X 0 1 0 Motor gain G = 6.4
X 0 1 1 Motor gain G = 8.0
X 1 0 0 Motor gain G = 12.8
X 1 0 1 Motor gain G = 16.0
X 1 1 0 Motor gain G = 25.6
X 1 1 1 Motor gain G = 32.0

Motor bandwidth 0 1 0 1 X X 0 0 Motor f

X X 0 1 Motor f
X X 1 0 Motor f
X X 1 1 Motor f
0 0 X X Motor f
0 1 X X Motor f
1 0 X X Motor f

Motor output configuration 0 1 1 0 X X 0 0 Motor power maximum 37% Reset

X X 0 1 Motor power maximum 50%
X X 1 0 Motor power maximum 75%
X X 1 1 Motor power maximum 100%
0 0 X X MOTO1, MOTO2 pins 3-state Reset
0 1 X X Motor Pulse Width Modulation (PWM) mode
1 0 X X Motor Pulse Density Modulation (PDM) mode
1 1 X X Motor Compact Disc Video (CDV) mode

2

S; 4fs mode Reset

2

S; 2fs mode

2

S; fs mode

s
s

s

s
s

s

= 0.5 Hz Reset

4

= 0.7 Hz

4

= 1.4 Hz

4

= 2.8 Hz

4

= 0.85 Hz Reset

3

= 1.71 Hz

3

= 3.42 Hz

3

1998 Feb 16 12

Philips Semiconductors Product specification

CMOS digital decoding IC with RAM for
Compact Disc

REGISTER ADDRESS DATA FUNCTION INITIAL

Loop BW

(Hz)

PLL loop filter bandwidth 1 0 0 0 0 0 0 0 1640 525 8400

0 0 0 1 3279 263 16800
0 0 1 0 6560 131 33600
0 1 0 0 1640 1050 8400
0 1 0 1 3279 525 16800
0 1 1 0 6560 263 33600
1 0 0 0 1640 2101 8400
1 0 0 1 3279 1050 16800 Reset
1 0 1 0 6560 525 33600
1 1 0 0 1640 4200 8400
1 1 0 1 3279 2101 16800
1 1 1 0 6560 1050 33600

PLL loop filter equalization 1 0 0 1 0 0 0 1 PLL 30 ns over-equalization

0 0 1 0 PLL 15 ns over-equalization
0 0 1 1 PLL nominal equalization Reset
0 1 0 0 PLL 15 ns under-equalization
0 1 0 1 PLL 30 ns under-equalization

EBU output 1 0 1 0 X X 0 0 EBU data before concealment

X X 1 0 EBU data after concealment and fade Reset
X X 1 1 EBU off − output LOW
X 0 X X Level II clock accuracy (<1000 × 10
X 1 X X Level III clock accuracy (>1000 × 10
0 X X X Flags in EBU off Reset
1 X X X Flags in EBU on

Speed control 1 0 1 1 1 X X X double-speed mode

0 X X X single-speed mode Reset
X 0 X X 33.869 MHz crystal present Reset
X 1 X X 16.934 MHz crystal present
X X 0 0 standby 1: ‘CD-STOP’ mode (note 1) Reset
X X 1 0 standby 2: ‘CD-PAUSE’ mode (note 1)
X X 1 1 operating mode

Versatile pins interface 1 1 0 0 X X X 1 off-track input at V1

X X X 0 no off-track input (V1 may be read via status) Reset
X X 0 X Kill-L at KILL output, Kill-R at V3 output
X 0 1 X V3 = 0; single Kill output Reset
X 1 1 X V3 = 1; single Kill output

Internal BW

(Hz)

Low-pass

BW (Hz)

−6

) Reset

−6

)

SAA7345

1998 Feb 16 13

Philips Semiconductors Product specification

CMOS digital decoding IC with RAM for
Compact Disc

REGISTER ADDRESS DATA FUNCTION INITIAL

Versatile pins interface 1 1 0 1 0 0 0 0 4-line motor (using V4, V5)

X X 0 1 Q-to-W subcode at V4
X X 1 0 V4 = 0
X X 1 1 V4 = 1 Reset
0 1 X X de-emphasis signal at V5
10 X X V5=0
1 1 X X V5 = 1 Reset

Note

1. Standby modes = CL, DA and RAB; normal operation.
a) MISC, SCLK, WCLK, DATA, CL11 and DOBM; 3-state.
b) CRIN, CROUT, CL16 and CLA; normal operation.
c) V1, V2, V3, V4 and V5; normal operation.
d) MOTO1 and MOTO2 - in standby 2 ‘CD-PAUSE’; normal operation.
e) MOTO1 and MOTO2 - in standby 1 ‘CD-STOP’; held LOW in PWM mode; 3-state in PDM mode.

SAA7345

Error corrector

The error corrector carries out t = 2, e = 0 error corrections
on both C1 (32 symbol) and C2 (28 symbol) frames. Four
symbols are used from each frame as parity symbols. The
strategy t = 2, e = 0 means that the error corrector can
correct two erroneous symbols per frame and detect all
erroneous frames.

The error corrector also contains a flag controller. Flags
are assigned to symbols when the error corrector cannot
ascertain if the symbols are definitely good. C1 generates
output flags which are read (after de-interleaving) by C2,
to help in the generation of C2 output flags.

The C2 output flags are used by the interpolator for
concealment of non-correctable errors. They are also
output via the EBU signal (DOBM) and the MISC output

2

S for CD-ROM applications.

with I
The flags output pin CFLG provides information on the

state of all error correction and concealment flags.

Audio functions

D

E-EMPHASIS AND PHASE LINEARITY

When de-emphasis is detected in the Q-channel subcode,
the digital filter automatically includes a de-emphasis filter
section. When de-emphasis is not required, a phase
compensation filter section controls the phase linearity of
the digital oversampling filter to ≤±1° within the band
0 to 16 kHz.

IGITAL OVERSAMPLING FILTER

D
The SAA7345 contains a 2 to 4 times oversampling filter.

The filter specification of the 4 × oversampling filter is
given in Table 2 and shown in Fig.12.

These attenuations do not include the sample and hold at
the DAC output or the DAC post filter.

When using the oversampling filter, the output level is
scaled −0.5 dB down, to avoid overflow on full-scale
sinewave inputs (0 to 20 kHz).

1998 Feb 16 14

Philips Semiconductors Product specification

CMOS digital decoding IC with RAM for
Compact Disc

Table 3 Digital filter passband characteristics

PASSBAND ATTENUATION

0 to 19 kHz ≤ 0.001 dB

19 to 20 kHz ≤ 0.03 dB

Table 4 Digital filter stopband characteristics.

STOPBAND ATTENUATION

24 kHz ≥ 25 dB
24 to 27 kHz ≥ 38 dB
27 to 35 kHz ≥ 40 dB
35 to 64 kHz ≥ 50 dB
64 to 68 kHz ≥ 31 dB

68 kHz ≥ 35 dB
69 to 88 kHz ≥ 40 dB

20

SAA7345

MGA385

magnitude

(dB)

0

20

40

60

010 30

20

40

frequency (kHz)

50

Fig.12 Digital filter characteristics.

ONCEALMENT

C
A 1-sample linear interpolator becomes active if a single sample is flagged as erroneous but cannot be corrected. The

erroneous sample is replaced by a level midway between the preceding and following samples. Left and right channels
have independent interpolators.

If more than one consecutive non-correctable sample is found, the last good sample is held. A 1-sample linear
interpolation is then performed before the next good sample (see Fig.13).

1998 Feb 16 15

Philips Semiconductors Product specification

CMOS digital decoding IC with RAM for
Compact Disc

Interpolation Hold Interpolation

OK Error OK Error Error Error OK OK

Fig.13 Concealment mechanism.

MUTE,ATTENUATION AND FADE
A digital level controller is present on the SAA7345 which

performs the functions of soft mute, attenuation and fade.

Mute and Attenuation

Soft mute is activated by sending the Mute command to
the fade control register (address 0000, data X000). The
signal will reduced to zero in up to 128 steps (depending
on the current position of the fade control), taking a
maximum of 3 ms.

Attenuation (−12 dB) is activated by sending the Attenuate
command to the fade control register (data X01X).

Attenuation and mute are cancelled by sending the Full
Scale command to the fade control register (data X001). It
will take 3 ms to ramp the output from mute to the full-scale
level.

Fade

The audio output level is determined by the value of the
internal fade counter.

SAA7345

MGA372

To control the fade counter in a continuous way, the
step-up and step-down commands are available (fade
control register data X101 and X100). They will increment
or decrement the counter by 1 for each register write
operation.

• When issuing more than 1 step-up or step-down
command in sequence, the write repeat mode may be
used (see Fig.6).

• A pause of at least 22 µs is necessary between any two
step-up or step-down commands.

• When a step-up command is given when the fade
counter is already at its full-scale value, the counter will
not increment.

DAC Interface

The SAA7345 is compatible with a wide range of
Digital-to-Analog Converters. Eleven formats are
supported and are shown in Table 5.

All formats are MSB first. f
mode and 88.2 kHz in double-speed mode.

is 44.1 kHz in single-speed

s

Level

• The counter is preset to 128 by the Full Scale command
if no oversampling is required.

• The counter is preset to 120 (−0.5 dB scaling) by the Full
Scale command if either 2fs or 4fs oversampling is
programmed in the DAC output register (address 0011).

• The counter is preset to 32 by the Attenuate command.

• The counter is preset to 0 by the Mute command.

1998 Feb 16 16

counter

---------------------­128

maximum level×=

Philips Semiconductors Product specification

CMOS digital decoding IC with RAM for
Compact Disc

Table 5 DAC interface formats

MODE

DAC CONTROL

REGISTER DATA

1 1010 f
2 1011 f
3 1110 f
4 0010 f
5 0110 f
6000X 4f
7010X 4f
8110X 4f

9 0011 2f
10 0111 2f
11 1111 2f

Note

1. n = disc speed.

2. EIAJ is the abbreviation for: Electronic Industries Associated of Japan.

SAMPLE

FREQUENCY

s
s
s
s
s

s
s
s
s
s
s

BITS SCLK (MHz) FORMAT INTERPOLATION

16 2.1168 × n
16 2.1168 × n
16 2.1168 × n
16 2.1168 × n
18 2.1168 × n
16 8.4672 × n
18 8.4672 × n
18 8.4672 × n
16 4.2336 × n
18 4.2336 × n
18 4.2336 × n

(1)
(1)
(1)
(1)
(1)

(1)
(1)
(1)
(1)
(1)
(1)

SAA7345

CD-ROM (I2S) no
CD-ROM (EIAJ)
Philips I2S − 16 bits yes
EIAJ − 16 bits yes
EIAJ − 18 bits yes
EIAJ − 16 bits yes
EIAJ − 18 bits yes
Philips I2S − 18 bits yes
EIAJ − 16 bits yes
EIAJ − 18 bits yes
Philips I2S − 18 bits yes

(2)

no

1998 Feb 16 17

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1998 Feb 16 18

SCLK

Philips Semiconductors Product specification

CMOS digital decoding IC with RAM for

Compact Disc

WCLK

CD-ROM
MODE ONLY

SCLK

WCLK

15

LEFT CHANNEL DATA (WCLK NORMAL POLARITY)

LSB VALID MSB VALID LSB VALID MSB VALIDMISC

0

150DATA

MGA383

Fig.14 Philips I2S data format (16-bit word length shown).

17

LEFT CHANNEL DATA

0

170DATA

MISC

MGA384

SAA7345

Fig.15 EIAJ data format (18-bit word length shown).

Philips Semiconductors Product specification

CMOS digital decoding IC with RAM for

SAA7345

Compact Disc

EBU interface

The biphase-mark digital output signal at pin DOBM is in accordance with the format defined by the
specification.

Three different modes can be selected via the EBU output control register (address 1010).

Table 6 EBU output modes

EBU CONTROL

REGISTER DATA

XX11 DOBM pin held LOW −
XX00 data taken before concealment, mute and fade HIGH if data is non-correctable

XX10 data taken after concealment, mute and fade HIGH if data is non-correctable

F

ORMAT

The digital audio output consists of 32-bit words (subframes) transmitted in biphase-mark code (two transitions for a
logic 1 and one transition for a logic 0). Words are transmitted in blocks of 384 (see Table 7).

EBU OUTPUT AT DOBM PIN EBU VALIDITY FLAG (BIT 28)

(concealment flag)

(concealment flag)

“IEC 958

”

Table 7 EBU word format

WORD BITS FUNCTION

Sync 0 to 3 −
Auxiliary 4 to 7 not used; normally zero
Error flags 4 CFLG error and interpolation flags when bit 3 of EBU control

register is set to logic 1
Audio sample 8to 27 first 4 bits not used (always zero)
Validity flag 28 valid = logic 0
User data 29 used for subcode data (Q-to-W)
Channel status 30 control bits and category code
Parity bit 31 even parity for bits 4 to 30

SYNC
The sync word is formed by violation of the biphase rule

and therefore does not contain any data. Its length is
equivalent to 4 data bits. The three different sync patterns
indicate the following situations:

• Sync B:
– Start of a block (384 words), word contains left

sample.

• Sync M:
– Word contains left sample (no block start).

• Sync W:
– Word contains right sample.

AUDIO SAMPLE
Left and right samples are transmitted alternately.

V

ALIDITY FLAG

Audio samples are flagged (bit 28 = logic 1) if an error has
been detected but was non-correctable. This flag remains
the same even if data is taken after concealment.

U

SER DATA

Subcode bits Q-to-W from the subcode section are
transmitted via the user data bit. This data is asynchronous
with the block rate.

1998 Feb 16 19

Philips Semiconductors Product specification

CMOS digital decoding IC with RAM for

SAA7345

Compact Disc

CHANNEL STATUS
The channel status bit is the same for left and right words. Therefore a block of 384 words contains 192 channel status

bits. The category code is always CD. The bit assignment is shown in Table 8.

Table 8 EBU channel status

WORD BITS FUNCTION

Control 0 to 3 copy of CRC checked Q-channel control bits 0 to 3;

bit 2 is logic 1 when copy permitted;

bit 3 is logic 1 when recording has pre-emphasis
Reserved mode 4 to 7 always zero
Category code 8 to 15 CD: bit 8 = logic 1; all other bits = logic 0
Clock accuracy 28 to 29 set by EBU control register:

00 = Level II

01 = Level III
Remaining 16 to 27 and 30 to 191 always zero

KILL circuit

The KILL circuit detects digital silence by testing for an
all-zero or all-ones data word in the left or right channel
before the digital filter. The output is switched active LOW
when silence has been detected for at least 200 ms. Two
modes are available, selected by the versatile pins register
(address 1100):

1-

PIN KILL MODE

Active LOW signal on KILL pin when digital silence has
been detected on both LEFT and RIGHT channels for
200 ms.

2-

PIN KILL MODE

Independent digital silence detection for left and right
channels. The KILL pin is active LOW when digital silence
has been detected in the LEFT channel for 200 ms, and V3
is active LOW when digital silence has been detected in
the RIGHT channel for 200 ms.

When MUTE is active then the KILL output is forced LOW.

Several output modes are supported:

1. Pulse Density, 2-line (true complement output), 1 MHz
sample frequency.

2. PWM output, 2-line, 22.05 kHz modulation frequency.

3. PWM-output, 4-line, 22.05 kHz modulation frequency.

4. CDV motor mode.

The modes are selected via the motor output configuration
register (address 0110).

P

ULSE DENSITY MODE

In the Pulse Density mode the motor output pin MOTO1 is
the pulse density modulated motor output signal. A 50%
duty cycle corresponds with the motor not actuated, higher
duty cycles mean acceleration, lower mean braking.

In this mode, the MOTO2 signal is the inverse of the
MOTO1 signal. Both signals change state only on the
edges of a 1 MHz internal clock signal.

Possible application diagrams are shown in Fig.16.

Spindle motor control

The spindle motor speed is controlled by a fully integrated
digital servo. Address information from the internal
±8 frame FIFO and disc speed information are used to
calculate the motor control output signals.

1998 Feb 16 20

Philips Semiconductors Product specification

CMOS digital decoding IC with RAM for

SAA7345

Compact Disc

22 kΩ

22 kΩ

10 nF

V

DD

V

22 kΩ

SS

+
–

22 kΩ

M

+

SS

–

22 kΩ

22 kΩ

10 nF

V

SS

V

+
–

M

V

DD

MOTO1

MOTO1

Fig.16 Motor pulse density application diagrams.

PWM MODE,2-LINE
In the PWM mode the motor acceleration signal is put in pulse-width modulation form on the MOTO1 output and the

motor braking signal is pulse-width modulated on the MOTO2 output.

22 kΩ

10 nF

V

SS

V

SS

MOTO2

MGA363 - 1

Figure 17 shows the timing and Fig.18 a typical application diagram.

t 240 ns

dead

MOTO1

MOTO2

t = 45 µs

rep

Accelerate Brake

Fig.17 Motor 2-line PWM mode timing.

+

M

10 Ω

100 nF

MGA366

MOTO1 MOTO2

Fig.18 Motor 2-line PWM mode application diagram.

1998 Feb 16 21

V

SS

MGA365 - 2

Philips Semiconductors Product specification

CMOS digital decoding IC with RAM for

SAA7345

Compact Disc

PWM MODE,4-LINE
Using two extra outputs from the Versatile Pins Interface, it is possible to use the SAA7345 with a 4-input motor bridge.
Figure 19 shows the timing and Fig.20 a typical application diagram.

t = 45 µs t 240 ns

rep

MOTO1

MOTO2

V4

V5

Accelerate Brake

Fig.19 Motor 4-line PWM mode timing.

dead

t = 240 ns

ovl

MGA367 - 1

+

V4

MOTO1

10 Ω

M

100 nF

V

SS

V5

MOTO2

MGA364 - 2

Fig.20 Motor 4-line PWM mode application diagram.

CDV

MODE

In the CDV motor mode, the FIFO position will be put in pulse-width modulated form on the MOTO1 pin (carrier frequency
300 Hz) and the PLL frequency signal will be put in pulse-density modulated form on the MOTO2 pin (carrier frequency

4.23 MHz). The integrated motor servo is disabled in this mode.
Remark:

The PWM signal on MOTO1 corresponds to a total memory space of 20 frames, therefore the nominal FIFO position
(half-full) will result in a PWM output of 60%.

1998 Feb 16 22

Philips Semiconductors Product specification

CMOS digital decoding IC with RAM for

SAA7345

Compact Disc

OPERATION MODES
The motor servo has the operation modes as shown in Table 9 and is controlled by the motor mode register

(address 0001).

Table 9 Operation modes.

MODE DESCRIPTION

Start mode 1 Disc is accelerated by applying a positive voltage to the spindle motor. No decisions are involved

and the PLL is reset. No disc speed information is available for the microcontroller.

Start mode 2 The disc is accelerated as in Start mode 1, however the PLL will monitor the disc speed. When the

disc reaches 75% of its nominal speed, the controller will switch to Jump mode. The motor status
signals are valid (register 0010).

Jump mode Motor servo enabled but FIFO kept reset at 50%. The audio is muted but it is possible to read the

subcode.
Jump mode 1 Similar to Jump mode but motor integrator is kept at zero. Used for long jumps.
Play mode FIFO released after resetting to 50%. Audio mute released.
Stop mode 1 Disc is braked by applying a negative voltage to the motor. No decisions are involved.
Stop mode 2 The disc is braked as in Stop mode 1, but the PLL will monitor the disc speed. As soon as the disc

reaches 12% of its nominal speed, the MOTSTOP status signal will go HIGH and switch the motor

servo to off mode.
Off mode Motor not steered.

POWER LIMIT
In Start mode 1, Start mode 2, Stop mode 1 and Stop

mode 2, a fixed positive or negative voltage is applied to
the motor. This voltage can be programmed as a
percentage of the maximum possible voltage via the motor
output configuration register (address 0110) to limit
current drain during start and stop. The following power
limits are possible:

• 100% of maximum (no power limit)

• 75% of maximum

• 50% of maximum

• 37% of maximum.

OOP CHARACTERISTICS

L
The gain and cross-over frequencies of the motor control

loop can be programmed via the motor gain and bandwidth
registers (addresses 0100 and 0101). The possible
parameter values are as follows:

Gain: 3.2, 4.0, 6.4, 8.0 12.8, 16, 26.6 or 32.
Cross-over frequency, f4: −0.5, −0.7, −1.4 or −2.8 Hz.
Cross-over frequency, f3: −0.85, −1.71 or −3.42 Hz.

OVERFLOW

FIFO
If FIFO overflow occurs during Play mode (e.g. as a result

of motor shock), the FIFO will be automatically reset
to 50% and the audio interpolator is activated to minimize
the effect of data loss.

1998 Feb 16 23

Philips Semiconductors Product specification

CMOS digital decoding IC with RAM for
Compact Disc

MGA362 - 2

G

fBW

f

4

3

Fig.21 Motor servo mode diagram.

Versatile pins interface

The SAA7345 has five pins that can be reconfigured for different applications as shown in Table 10.

f

SAA7345

Table 10Versatile pins

SYMBOL PIN TYPE

CONTROL
REGISTER

ADDRESS

CONTROL

REGISTER

DATA

FUNCTION

V1 3 input 1 1 0 0 X X X 1 off-track input (from digital servo)

X X X 0 input may be read via status register

(address 0010 data X101)

V2 4 input −−input may be read via status register

(address 0010 data X110)

V3 26 output 1 1 0 0 X X 0 X kill output for right channel

X 0 1 X output = logic 0
X 1 1 X output = logic 1

V4 25 output 1 1 0 1 0 0 0 0 4-line motor drive (using V4 and V5)

X X 0 1 Q-to-W subcode output
X X 1 0 output = logic 0
X X 1 1 output = logic 1

V5 24 output 1 1 0 1 0 1 X X de-emphasis output (active HIGH)

1 0 X X output = logic 0
1 1 X X output = logic 1

1998 Feb 16 24

Philips Semiconductors Product specification

CMOS digital decoding IC with RAM for

SAA7345

Compact Disc

Flags Output (CFLG) (open drain output)

A 1-bit flag signal is available at the CFLG pin. This signal shows the status of the error corrector and interpolator and is
updated every frame (7.35 kHz).

handbook, full pagewidth

CFLG

Table 11Meaning of flag bits.

F1 F2 F3 F4 F5 F6 F7 MEANING

0 X X X X X X no absolute time sync

1 X X X X X X absolute time sync
X 0 0 X X X X C1 frame contained no errors
X 0 1 X X X X C1 frame contained 1 error
X 1 0 X X X X C1 frame contained 2 errors
X 1 1 X X X X C1 frame non-correctable
X X X 0 0 X X C2 frame contained no errors
X X X 0 1 X X C2 frame contained 1 error
X X X 1 0 X X C2 frame contained 2 errors
X X X 1 1 X X C2 frame non-correctable
X X X X X 0 0 no interpolations
X X X X X 0 1 at least one 1-sample interpolation
X X X X X 1 0 at least one hold and no interpolations
X X X X X 1 1 at least one hold and one 1-sample interpolation

11.3
µs

F1 F2 F3 F4 F5 F6 F7 F1

45.4 µs

MGA370

Fig.22 Flags output timing.

ABSOLUTE TIME SYNC
The first flag bit (F1) is the absolute time sync signal. It is

the FIFO-passed subcode-sync and relates the position of
the subcode-sync to the audio data (DAC output).

The flag may be used for special purposes such as
synchronization of different players.

F

LAGS AT EBU OUTPUT

The CFLG flags are available on bit 4 of the EBU data
format when bit 3 of the EBU output control register
(address 1010) is set to logic 1.

1998 Feb 16 25

Double speed mode

Double speed mode is programmed via the Speed control
register (address 1011). It is possible to program double
speed independent of clock frequency, but optimum
performance is achieved with a 33.8688 MHz crystal or a
ceramic resonator.

Philips Semiconductors Product specification

CMOS digital decoding IC with RAM for

SAA7345

Compact Disc

LIMITING VALUES

In accordance with the Absolute Maximum Rating System (IEC 134).

SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT

V

DD

V

I(max)

V

O

I

O

T

amb

T

stg

V

es1

V

es2

Notes

1. All V

2. Equivalent to discharging a 100 pF capacitor via a 1.5 kΩ series resistor with a rise time of 15 ns.

3. Equivalent to discharging a 200 pF capacitor via a 2.5 µH series inductor.

supply voltage note 1 −0.5 +6.5 V
maximum input voltage −0.5 VDD+ 0.5 V
output voltage −0.5 +6.5 V
output current (continuous) −±20 mA
operating ambient temperature −40 +85 °C
storage temperature −55 +125 °C
electrostatic handling note 2 −2000 +2000 V
electrostatic handling note 3 −200 +200 V

and VSS connections must be made externally to the same power supply.

DD

CHARACTERISTICS

= 3.4 to 5.5 V; VSS= 0 V; T

V

DD

= −40 to +85 °C; unless otherwise specified.

amb

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

Supply

V

DD

I

DD

Analog Front End (V

f

clk

V

th

Analog Front End (V

f

clk

V

tpt

supply voltage 3.4 5.0 5.5 V
supply current VDD=5V − 22 50 mA

= 4.5 to 5.5 V); comparator inputs HFIN and HFREF

DD

clock frequency 8 − 35 MHz
switching thresholds 1.2 − VDD− 0.4 V

= 3.4 to 5.5 V); comparator inputs HFIN and HFREF

DD

clock frequency 8 − 20 MHz
HFIN input voltage level − 1.0 − V

Digital inputs CL and RAB

V

IL

V

IH

I

LI

C

I

LOW level input voltage −0.3 − 0.3V
HIGH level input voltage 0.7V
input leakage current VI= 0 to V

DD

−10 − +10 µA

DD

− VDD+ 0.3 V

DD

V

input capacitance −−10 pF

1998 Feb 16 26

Philips Semiconductors Product specification

CMOS digital decoding IC with RAM for

SAA7345

Compact Disc

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

Digital inputs PORE, V1 and V2

V

thr

V

thf

V

hys

R

PU

C

I

t

rw

switching threshold voltage rising −−0.8V
switching threshold voltage falling 0.2V
hysteresis voltage − 0.33V
input pull-up resistance VI=0V − 50 − kΩ
input capacitance −−10 pF
reset pulse width PORE only 1 −−µs

Digital outputs CL16 and CLA

V

OL

V

OH

C

L

t

r

t

f

LOW level output voltage IOL= 1 mA 0 − 0.4 V
HIGH level output voltage IOH= −1mA VDD− 0.4 − V
load capacitance −−50 pF
output rise time CL= 20 pF; note 1 −−15 ns
output fall time CL= 20 pF; note 1 −−15 ns

Digital outputs V4 and V5

V

OL

V

OH

C

L

t

r

t

f

LOW level output voltage VDD= 4.5 to 5.5 V;

HIGH level output voltage VDD= 4.5 to 5.5 V;

load capacitance −−50 pF
output rise time CL= 20 pF; note 1 −−15 ns
output fall time CL= 20 pF; note 1 −−15 ns

Open-drain output CFLG

V

OL

I

OL

C

L

t

f

LOW level output voltage IOL= 1 mA 0 − 0.4 V
LOW level output current −−2mA
load capacitance −−50 pF
output fall time CL= 20 pF; note 1 −−30 ns

Open-drain outputs KILL and V3

V

OL

I

OL

C

L

t

f

LOW level output voltage IOL= 1 mA 0 − 0.4 V
LOW level output current −−2mA
load capacitance −−50 pF
output fall time CL= 20 pF; note 1 −−15 ns

IOL=10mA
V

= 3.4 to 5.5 V;

DD

IOL=5mA

IOH= −10 mA
V

= 3.4 V to 5.5 V;

DD

IOH = −5 mA

DD

DD

−−V

− V

DD

DD

0 − 1.0 V

0 − 1.0 V

VDD− 1 − V

VDD− 1 − V

DD

DD

V

V

V

V

1998 Feb 16 27

Philips Semiconductors Product specification

CMOS digital decoding IC with RAM for

SAA7345

Compact Disc

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

3-state outputs MISC, SCLK, WCLK, DATA and CL11

V

OL

V

OH

C

L

t

r

t

f

I

LI

3-state outputs MOTO1, MOTO2 and DOBM

V

OL

V

OH

C

L

t

r

t

f

I

LI

Digital input/output DA

V

IL

V

IH

I

LI

C

I

V

OL

V

OH

C

L

t

r

t

f

Crystal oscillator input CRIN (external clock)

g

m

R

O

C

I

I

LI

Crystal oscillator output CROUT (see Fig.26)
f

xtal

C

fb

C

O

LOW level output voltage IOL= 1 mA 0 − 0.4 V
HIGH level output voltage IOH= −1mA VDD− 0.4 − V

DD

V
load capacitance −−50 pF
output rise time CL= 20 pF; note 1 −−15 ns
output fall time CL= 20 pF; note 1 −−15 ns
3-state leakage current VI= 0 to V

DD

LOW level output voltage VDD= 4.5 to 5.5 V;

−10 − +10 µA

0 − 1.0 V

IOL=10mA
V

= 3.4 to 5.5 V;

DD

0 − 1.0 V

IOL=5mA

HIGH level output voltage VDD= 4.5 to 5.5 V;

VDD− 1 − V

DD

V

IOH= −10 mA

= 3.4 to 5.5 V;

V

DD

VDD− 1 − V

DD

V

IOH= −5mA
load capacitance −−50 pF
output rise time CL= 20 pF; note 1 −−10 ns
output fall time CL= 20 pF; note 1 −−10 ns
3-state leakage current VI= 0 to V

DD

LOW level input voltage −0.3 − 0.3V
HIGH level input voltage 0.7V
3-state leakage current VI= 0 to V

DD

−10 − +10 µA

V

DD

DD

− VDD+ 0.3 V

−10 − +10 µA

input capacitance −−10 pF
LOW level output voltage IOL= 1 mA 0 − 0.4 V
HIGH level output voltage IOH= −1mA VDD− 0.4 − V

DD

V
load capacitance −−50 pF
output rise time CL= 20 pF; note 1 −−15 ns
output fall time CL= 20 pF; note 1 −−15 ns

mutual conductance at start-up − 4 − mS
output resistance at start-up − 11 − kΩ
input capacitance −−10 pF
input leakage current −10 − +10 µA

crystal frequency 8 16.9344 35 MHz
feedback capacitance −−5pF
output capacitance −−10 pF

1998 Feb 16 28

Philips Semiconductors Product specification

CMOS digital decoding IC with RAM for

SAA7345

Compact Disc

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

I2S timing

CLOCK OUTPUT SCLK (see Fig.23)
t

cy

t

H

t

L

t

su

t

h

2

S timing (double speed)

I

output clock period sample rate = f

clock HIGH time sample rate = f

clock LOW time sample rate = f

set-up time sample rate = f

hold time sample rate = f

sample rate = 2f
sample rate = 4f

sample rate = 2f
sample rate = 4f

sample rate = 2f
sample rate = 4f

sample rate = 2f
sample rate = 4f

sample rate = 2f
sample rate = 4f

s

s
s

s

s
s

s

s
s

s

s
s

s

s
s

− 472.4 − ns

− 236.2 − ns

− 118.1 − ns

166 −−ns
83 −−ns
42 −−ns
166 −−ns
83 −−ns
42 −−ns
95 −−ns
48 −−ns
24 −−ns
95 −−ns
48 −−ns
24 −−ns

CLOCK OUTPUT SCLK (see Fig.23)
t

cy

t

H

t

L

t

su

t

h

output clock period sample rate = f

clock HIGH time sample rate = f

clock LOW time sample rate = f

set-up time sample rate = f

hold time sample rate = f

sample rate = 2f
sample rate = 4f

sample rate = 2f
sample rate = 4f

sample rate = 2f
sample rate = 4f

sample rate = 2f
sample rate = 4f

sample rate = 2f
sample rate = 4f

s

s
s

s

s
s

s

s
s

s

s
s

s

s
s

− 236.2 − ns

− 118.1 − ns

− 59.1 − ns

83 −−ns
42 −−ns
21 −−ns
83 −−ns
42 −−ns
21 −−ns
48 −−ns
24 −−ns
12 −−ns
48 −−ns
24 −−ns
12 −−ns

1998 Feb 16 29

Philips Semiconductors Product specification

CMOS digital decoding IC with RAM for

SAA7345

Compact Disc

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

Microcontroller interface timing (see Figs 24 and 25)

NPUTS CL AND RAB

I
t

L

t

H

t

r

t

f

EAD MODE

R
t

dRD

t

dRZ

t

pd

RITE MODE

W
t

suD

t

hD

t

suCR

t

dWZ

input LOW time single speed 500 −−ns

double speed 260 −−ns

input HIGH time single speed 500 −−ns

double speed 260 −−ns
rise time single speed −−480 ns
fall time double speed −−240 ns

delay time RAB to DA valid 0 − 50 ns
delay time RAB to DA

0 − 50 ns

high-impedance
propagation delay CL to DA single speed 700 − 980 ns

double speed 340 − 500 ns

set-up time DA to CL single speed; note 2 −700 −−ns

double speed; note 2 −340 −−ns
hold time CL to DA single speed −−980 ns

double speed −−500 ns
set-up time CL to RAB single speed 260 −−ns

double speed 140 −−ns
delay time DA high-impedance

50 −−ns

to RAB

Notes

1. Timing reference voltage levels are 0.8 V and VDD− 0.8 V.

2. Negative set-up time means that data may change after clock transition.

SCLK

WCLK
DATA
MISC

clock period t

t

h

cy

t

L

t

su

V – 0.8 V

DD

0.8 V

Fig.23 I2S timing.

1998 Feb 16 30

t

H

V – 0.8 V

DD

0.8 V

MGA376 - 1

Philips Semiconductors Product specification

CMOS digital decoding IC with RAM for
Compact Disc

t

r

RAB

CL

DA (SAA7345)

high impedance

t

dRD

t

r

t

f

t

L

t

pd

t

H

V – 0.8 V

DD

0.8 V

V – 0.8 V

DD

0.8 V

t

f

V – 0.8 V

DD

0.8 V

t

dRZ

MGA377 - 1

SAA7345

RAB

CL

DA

(microcontroller)

Fig.24 Microcontroller timing; READ mode.

t

suCR

t

r

V – 0.8 V

DD

0.8 V

t

suD

t

f

t

L

V – 0.8 V

DD

0.8 V

t

H

t

hD

t

r

t

dWZ

high impedance

t

H

t

f

V – 0.8 V

DD

0.8 V

t

L

MGA378 - 1

Fig.25 Microcontroller timing; WRITE mode.

1998 Feb 16 31

Philips Semiconductors Product specification

CMOS digital decoding IC with RAM for
Compact Disc

APPLICATION INFORMATION

33.8688 MHz

1 nF

(3rd overtone)

CRYSTAL

10 pF

16.9344 MHz
CRYSTAL

3.3
µH

10 pF

100

kΩ

100

kΩ

2.2
kΩ

CRIN

CROUT

V

DDA

V

SSA

CRIN

SAA7345

CROUT

100
kΩ

MGA360 - 1

2.2
kΩ

2.2
kΩ

V

DDA

V

SSA

CRIN

CROUT

V

DDA

V

SSA

33 pF

33.8688

CERAMIC

GENERATOR

5 pF

33 pF

5 pF

Fig.26 Application circuits for crystal oscillator.

1998 Feb 16 32

Philips Semiconductors Product specification

CMOS digital decoding IC with RAM for
Compact Disc

V

V

DD

44 43 42 41 40 39 38 37 36 35 34

V

DD2

1

CL11

2

DOBM

3

V1

4

V2

5

TEST2

6

TEST1

7

ISLICE

8

HFIN

9

HFREF

10

IREF

11

V

DDA

(1)

V

SS2

V

SSA

CRIN

12 13 14 15 16 17 18 19 20 21 22

11 MHz

clock output

X6

HFIN

X8

2.2 nF

R2

22 kΩ

R3

2.2 kΩ

C1

C12

4.7 µF
(63 V)

to DOBM transformer

C2 47 pF

C4

100 nFC3 22 nF

V

R4

2.2 Ω

R6

2.2 Ω

100 nF

C13

DD1

V

CROUT

V

DD

SAA7345

SS1

CL16

V

MISC

DATA

SCLK

WCLK

CFLG

RAB

CL

DA

CLA

PORE

KILL

V3
V4

V5

MOTO2

MOTO1

SAA7345

33
32
31
30
29
28
27
26
25
24
23

micro-

controller

interface

MOTOR

INTERFACE

C6

4.7 µF
(63 V)

(1) Diagram is for a 5 V application. For 3.4 V applications an additional resistor of 150 kΩ should be added between IREF (pin 10) and ground.
(2) For crystal oscillator circuit see Fig.26.

C7

100 nF

C11
100

(2)

nF

X9

clock output

to DAC

16 MHz

MGA375 - 1

Fig.27 Typical SAA7345 application diagram.

1998 Feb 16 33

Philips Semiconductors Product specification

CMOS digital decoding IC with RAM for
Compact Disc

PACKAGE OUTLINE

QFP44: plastic quad flat package; 44 leads (lead length 2.35 mm); body 14 x 14 x 2.2 mm

c

y

X

33 23

34

Z

22

E

A

SAA7345

SOT205-1

e

w M

b

p

v M

B

v M

scale

(1)

eH

H

D

19.2

1

18.2

e

pin 1 index

2.3

2.1

b

0.25

12

11

Z

w M

p

D

H

D

p

0.50

0.25

0.35

0.14

D

0 5 10 mm

(1) (1)(1)

cE

D

14.1

14.1

13.9

13.9

44

1

DIMENSIONS (mm are the original dimensions)

mm

A

max.

2.60

0.25

0.05

UNIT A1A2A3b

Note

1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.

E

A

B

19.2

18.2

H

E

LL

E

2.0

1.2

A

p

A

2

A

1

detail X

Z

D

0.152.35 0.10.3

2.4

1.8

(A )

3

L

p

L

Zywv θ

E

o

2.4

7

o

1.8

0

θ

OUTLINE

VERSION

SOT205-1

IEC JEDEC EIAJ

133E01A

REFERENCES

1998 Feb 16 34

EUROPEAN

PROJECTION

ISSUE DATE

95-02-04
97-08-01

Philips Semiconductors Product specification

CMOS digital decoding IC with RAM for
Compact Disc

SOLDERING
Introduction

There is no soldering method that is ideal for all IC
packages. Wave soldering is often preferred when
through-hole and surface mounted components are mixed
on one printed-circuit board. However, wave soldering is
not always suitable for surface mounted ICs, or for
printed-circuits with high population densities. In these
situations reflow soldering is often used.

This text gives a very brief insight to a complex technology.
A more in-depth account of soldering ICs can be found in
our

“IC Package Databook”

Reflow soldering

Reflow soldering techniques are suitable for all QFP
packages.

The choice of heating method may be influenced by larger
plastic QFP packages (44 leads, or more). If infrared or
vapour phase heating is used and the large packages are
not absolutely dry (less than 0.1% moisture content by
weight), vaporization of the small amount of moisture in
them can cause cracking of the plastic body. For more
information, refer to the Drypack chapter in our

Reference Handbook”

Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
to the printed-circuit board by screen printing, stencilling or
pressure-syringe dispensing before package placement.

Several methods exist for reflowing; for example,
infrared/convection heating in a conveyor type oven.
Throughput times (preheating, soldering and cooling) vary
between 50 and 300 seconds depending on heating
method. Typical reflow peak temperatures range from
215 to 250 °C.

(order code 9398 652 90011).

“Quality

(order code 9397 750 00192).

SAA7345

If wave soldering cannot be avoided, for QFP
packages with a pitch (e) larger than 0.5 mm, the
following conditions must be observed:

• A double-wave (a turbulent wave with high upward

pressure followed by a smooth laminar wave)
soldering technique should be used.

• The footprint must be at an angle of 45° to the board

direction and must incorporate solder thieves
downstream and at the side corners.

During placement and before soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.

Maximum permissible solder temperature is 260 °C, and
maximum duration of package immersion in solder is
10 seconds, if cooled to less than 150 °C within
6 seconds. Typical dwell time is 4 seconds at 250 °C.

A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.

Repairing soldered joints

Fix the component by first soldering two diagonally­opposite end leads. Use only a low voltage soldering iron
(less than 24 V) applied to the flat part of the lead. Contact
time must be limited to 10 seconds at up to 300 °C. When
using a dedicated tool, all other leads can be soldered in
one operation within 2 to 5 seconds between
270 and 320 °C.

Wave soldering

Wave soldering is not recommended for QFP packages.
This is because of the likelihood of solder bridging due to
closely-spaced leads and the possibility of incomplete
solder penetration in multi-lead devices.

CAUTION

Wave soldering is NOT applicable for all QFP
packages with a pitch (e) equal or less than 0.5 mm.

1998 Feb 16 35

Philips Semiconductors Product specification

CMOS digital decoding IC with RAM for

SAA7345

Compact Disc

DEFINITIONS

Data sheet status

Objective specification This data sheet contains target or goal specifications for product development.
Preliminary specification This data sheet contains preliminary data; supplementary data may be published later.
Product specification This data sheet contains final product specifications.

Limiting values

Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.

Application information

Where application information is given, it is advisory and does not form part of the specification.

LIFE SUPPORT APPLICATIONS

These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.

1998 Feb 16 36

Philips Semiconductors Product specification

CMOS digital decoding IC with RAM for
Compact Disc

NOTES

SAA7345

1998 Feb 16 37

Philips Semiconductors Product specification

CMOS digital decoding IC with RAM for
Compact Disc

NOTES

SAA7345

1998 Feb 16 38

Philips Semiconductors Product specification

CMOS digital decoding IC with RAM for
Compact Disc

NOTES

SAA7345

1998 Feb 16 39

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TEL AVIV 61180, Tel. [phone], Fax. [phone]
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20124 MILANO, Tel. [phone], Fax. [phone]
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Tel. [phone], Fax. [phone]
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Tel. [phone], Fax. [phone]
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Mexico: 5900 Gateway East, Suite 200, EL PASO, TEXAS 79905,

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Middle East: see Italy

Netherlands: Postbus 90050, 5600 PB EINDHOVEN, Bldg. VB,

Tel. [phone], Fax. [phone]
New Zealand: 2 Wagener Place, C.P.O. Box 1041, AUCKLAND,

Tel. [phone], Fax. [phone]
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106 Valero St. Salcedo Village, P.O. Box 2108 MCC, MAKATI,
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Romania: see Italy
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Ukraine: PHILIPS UKRAINE, 4 Patrice Lumumba str., Building B, Floor 7,
252042 KIEV, Tel. [phone], Fax. [phone]

United Kingdom: Philips Semiconductors Ltd., 276 Bath Road, Hayes,
MIDDLESEX UB3 5BX, Tel. [phone], Fax. [phone]

United States: 811 East Arques Avenue, SUNNYVALE, CA 94088-3409,
Tel. [phone]

Uruguay: see South America
Vietnam: see Singapore
Yugoslavia: PHILIPS, Trg N. Pasica 5/v, 11000 BEOGRAD,

Tel. [phone], Fax.[phone]

For all other countries apply to: Philips Semiconductors,
International Marketing & Sales Communications, Building BE-p, P.O. Box 218,
5600 MD EINDHOVEN, The Netherlands, Fax. [phone]

© Philips Electronics N.V. 1998 SCA57
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.

The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license
under patent- or other industrial or intellectual property rights.

Internet: http://www.semiconductors.philips.com

Printed in The Netherlands 545102/00/05/pp40 Date of release: 1998Feb 16 Document order number: 9397 750 03314