Philips SAA7114H-V1 Datasheet

DATA SH EET

Preliminary speciﬁcation File under Integrated Circuits, IC22

2000 Mar 15

INTEGRATED CIRCUITS

SAA7114H

PAL/NTSC/SECAM video decoder with adaptive PAL/NTSC comb filter, VBI-data slicer and high performance scaler

2000 Mar 15 2

Philips Semiconductors Preliminary speciﬁcation

PAL/NTSC/SECAM video decoder with adaptive PAL/NTSC comb ﬁlter, VBI-data slicer and high performance scaler

SAA7114H

CONTENTS

1 FEATURES

1.1 Video decoder

1.2 Video scaler

1.3 Vertical Blanking Interval (VBI) data decoder and slicer

1.4 Audio clock generation

1.5 Digital I/O interfaces

1.6 Miscellaneous

2 APPLICATIONS 3 GENERAL DESCRIPTION 4 QUICK REFERENCE DATA 5 ORDERING INFORMATION 6 BLOCK DIAGRAM 7 PINNING 8 FUNCTIONAL DESCRIPTION

8.1 Decoder

8.2 Decoder output formatter

8.3 Scaler

8.4 VBI-data decoder and capture (subaddresses 40H to 7FH)

8.5 Image port output formatter (subaddresses 84H to 87H)

8.6 Audio clock generation (subaddresses 30H to 3FH)

9 INPUT/OUTPUT INTERFACES AND PORTS

9.1 Analog terminals

9.2 Audio clock signals

9.3 Clock and real-time synchronization signals

9.4 Video expansion port (X-port)

9.5 Image port (I-port)

9.6 Host port for 16-bit extension ofvideodata I/O (H-port)

9.7 Basic input and output timing diagrams I-port and X-port

10 BOUNDARY SCAN TEST

10.1 Initialization of boundary scan circuit

10.2 Device identification codes 11 LIMITING VALUES 12 THERMAL CHARACTERISTICS 13 CHARACTERISTICS 14 APPLICATION INFORMATION 15 I2C-BUS DESCRIPTION

15.1 I2C-bus format

15.2 I2C-bus details

15.3 Programming register audio clock generation

15.4 Programming register VBI-data slicer

15.5 Programming register interfaces and scaler part

16 PROGRAMMING START SET-UP

16.1 Decoder part

16.2 Audio clock generation part

16.3 Data slicer and data type control part

16.4 Scaler and interfaces

17 PACKAGE OUTLINE 18 SOLDERING

18.1 Introduction to soldering surface mount packages

18.2 Reflow soldering

18.3 Wave soldering

18.4 Manual soldering

18.5 Suitability of surface mount IC packages for wave and reflow soldering methods

19 DEFINITIONS 20 LIFE SUPPORT APPLICATIONS 21 PURCHASE OF PHILIPS I2C COMPONENTS

2000 Mar 15 3

Philips Semiconductors Preliminary speciﬁcation

PAL/NTSC/SECAM video decoder with adaptive PAL/NTSC comb ﬁlter, VBI-data slicer and high performance scaler

SAA7114H

1 FEATURES

1.1 Video decoder

• Six analog inputs, internal analog source selectors, e.g. 6 × CVBS or (2 × Y/C and 2 × CVBS) or (1 × Y/C and 4 × CVBS)

• Two analog preprocessing channels in differential CMOS style inclusive built-in analog anti-alias filters

• Fully programmable static gain or Automatic Gain Control (AGC) for the selected CVBS or Y/C channel

• Automatic Clamp Control (ACC) for CVBS, Y and C

• Switchable white peak control

• Two 9-bit video CMOS Analog-to-Digital Converters

(ADCs), digitized CVBS or Y/C signals are available on the expansion port

• On-chip line-locked clock generation according

“ITU 601”

• Digital PLL for synchronization and clock generation from all standards and non-standard video sources e.g. consumer grade VTR

• Requires only one crystal (32.11 or 24.576 MHz) for all standards

• Horizontal and vertical sync detection

• Automatic detection of 50 and 60 Hz field frequency,

and automatic switching between PAL and NTSC standards

• Luminance and chrominance signal processing for PAL BGDHIN, combination PAL N, PAL M, NTSC M, NTSC-Japan, NTSC 4.43 and SECAM

• Adaptive 2/4-line comb filter for two dimensional chrominance/luminance separation

– Increasedluminanceandchrominancebandwidthfor

all PAL and NTSC standards

– Reduced cross colour and cross luminance artefacts

• PAL delay line for correcting PAL phase errors

• Independent Brightness Contrast Saturation (BCS)

adjustment for decoder part

• User programmable sharpness control

• Independent gain and offset adjustment for raw data

path.

1.2 Video scaler

• Horizontal and vertical down-scaling and up-scaling to randomly sized windows

• Horizontal and vertical scaling range: variable zoom to

⁄64(icon); it should be noted that the H and V zoom are

restricted by the transfer data rates

• Anti-alias and accumulating filter for horizontal scaling

• Vertical scaling with linear phase interpolation and

accumulating filter for anti-aliasing (6-bit phase accuracy)

• Horizontal phase correct up and down scaling for improved signal quality of scaled data, especially for compression and video phone applications, with 6-bit phase accuracy (1.2 ns step width)

• Two independent programming sets for scaler part, to define two ‘ranges’ per field or sequences over frames

• Fieldwise switching between decoder part and expansion port (X-port) input

• Brightness, contrast and saturation controls for scaled outputs.

1.3 Vertical Blanking Interval (VBI) data decoder

and slicer

• Versatile VBI-data decoder, slicer, clock regeneration and byte synchronization e.g. for World Standard Teletext (WST), North-American Broadcast Text System(NABTS),closecaption,WideScreen Signalling (WSS) etc.

1.4 Audio clock generation

• Generation of a field locked audio master clock to support a constant number of audio clocks per video field

• Generation of an audio serial and left/right (channel) clock signal.

2000 Mar 15 4

Philips Semiconductors Preliminary speciﬁcation

PAL/NTSC/SECAM video decoder with adaptive PAL/NTSC comb ﬁlter, VBI-data slicer and high performance scaler

SAA7114H

1.5 Digital I/O interfaces

• Real-time signal port (R port), inclusive continuous line-locked reference clock and real-time status information supporting RTC level 3.1 (refer to external document

“RTC Functional Specification”

for details)

• Bi-directional expansion port (X-port) with half duplex functionality (D1), 8-bit YUV

– Output from decoder part, real-time and unscaled – Input to scaler part, e.g. video from MPEG decoder

(extension to 16-bit possible)

• Video image port (I-port) configurable for 8-bit data (extension to 16-bit possible) in master mode (own clock), or slave mode (external clock), with auxiliary timing and hand shake signals

• Discontinuous data streams supported

• 32-word × 4-byte FIFO register for video output data

• 28-word × 4-byte FIFO register for decoded VBI output

data

• Scaled 4:2:2, 4:1:1, 4:2:0, 4:1:0 YUV output

• Scaled 8-bit luminance only and raw CVBS data output

• Sliced, decoded VBI-data output.

1.6 Miscellaneous

• Power-on control

• 5 V tolerant digital inputs and I/O ports

• Software controlled power saving standby modes

supported

• Programming via serial I2C-bus, full read-back ability by an external controller, bit rate up to 400 kbits/s

• Boundary scan test circuit complies with the

“IEEE Std.

1149.b1 - 1994”

2 APPLICATIONS

• Desktop video

• Multimedia

• Digital television

• Image processing

• Video phone applications.

3 GENERAL DESCRIPTION

The SAA7114H is a video capture device for applications at the image port of VGA controllers.

The SAA7114H is a combination of a two-channel analog preprocessing circuit including source selection, anti-aliasing filter and ADC, an automatic clamp and gain control, a Clock Generation Circuit (CGC), a digital multi-standard decoder containing two-dimensional chrominance/luminance separation by an adaptive comb filter and a high performance scaler, including variable horizontal and vertical up and down scaling and a brightness, contrast and saturation control circuit.

It is a highly integrated circuit for desktop video applications. The decoder is based on the principle of line-lockedclock decoding and is abletodecode the colour of PAL, SECAM and NTSC signals into ITU 601 compatible colour component values. The SAA7114H accepts as analog inputs CVBS or S-video (Y/C) from TV or VCR sources, including weak and distorted signals. An expansion port (X-port) for digital video (bi-directional halfduplex,D1 compatible) is also supported to connect to MPEG or video phone codec. At the so called image port (I-port) the SAA7114H supports 8 or 16-bit wide output data with auxiliary reference data for interfacing to VGA controllers.

The target application for SAA7114H is to capture and scale video images, to be provided as digital video stream through the image port of a VGA controller, for display via VGA’s frame buffer, or for capture to system memory.

In parallel SAA7114H incorporates also provisions for capturing the serially coded data in the vertical blanking interval (VBI-data). Two principal functions are available:

1. To capture raw video samples, after interpolation to the required output data rate, via the scaler

2. A versatile data slicer (data recovery) unit.

SAA7114H incorporates also a field locked audio clock generation. This function ensures that there is always the same number of audio samples associated with a field, or a set of fields. This prevents the loss of synchronization between video and audio, during capture or playback.

The circuit is I2C-bus controlled (full write/read capability for all programming registers, bit rate up to 400 kbits/s).

2000 Mar 15 5

Philips Semiconductors Preliminary speciﬁcation

PAL/NTSC/SECAM video decoder with adaptive PAL/NTSC comb ﬁlter, VBI-data slicer and high performance scaler

SAA7114H

4 QUICK REFERENCE DATA

Note

1. Power dissipation is measured in CVBS input mode (only one ADC active) and 8-bit image port output mode, expansion port is 3-stated.

5 ORDERING INFORMATION

SYMBOL PARAMETER MIN. TYP. MAX. UNIT

DDD

digital supply voltage 3.0 3.3 3.6 V

DDDC

digital core supply voltage 3.0 3.3 3.6 V

DDA

analog supply voltage 3.1 3.3 3.5 V

amb

operating ambient temperature 0 − 70 °C

A+D

analog and digital power dissipation; note 1 − 0.45 − W

TYPE

NUMBER

PACKAGE

NAME DESCRIPTION VERSION

SAA7114H LQFP100 plastic low proﬁle quad ﬂat package; 100 leads; body 14 × 14 × 1.4 mm SOT407-1

2000 Mar 15 6

Philips Semiconductors Preliminary speciﬁcation

PAL/NTSC/SECAM video decoder with adaptive PAL/NTSC

comb ﬁlter, VBI-data slicer and high performance scaler

SAA7114H

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6 BLOCK DIAGRAM

ll pagewidth

MHB528

FIR-PREFILTER

PRESCALER

AND

SCALER BCS

GENERAL PURPOSE

VBI-DATA SLICER

VIDEO/TEXT

ARBITER

TEXT FIFO

VIDEO

FIFO

PROGRAMMING

ARRAY

A/B

MUX

EVENT CONTROLLER

IMAGE PORT PIN MAPPING

X PORT I/O FORMATTING

EXPANSION PORT PIN MAPPING I/O CONTROL I2C-BUSREAL-TIME OUTPUT

LLC

AI2D

LINE FIFO

BUFFER

VERTICAL

SCALING

HORIZONTAL

FINE

(PHASE)

SCALING

to 8(16) MUX

ITRI

AGND

AI1D

AOUT

AI24

AI23

AI22

AI21

AI12

AI11

XTALO

XTALI

XTOUT

TCK

TMS

TDI

DD(XTAL)

SS(XTAL)

DDD(ICO1)

DDD(ICO6)

33, 43, 58, 68, 83, 93

DDD(EP1)

DDD(EP4)

1, 25, 51, 75

DDA0

DDA2

23, 17, 11

SSD(ICO1)

SSD(ICO3)

38, 63, 88

SSD(EP1)

SSD(EP4)

26, 50, 76, 100

SSA0

SSA2

24, 15, 9

AMXCLK

TDO

AMCLK

ALRCLK

ASCLK

LLC2

RTCO

RTS0

RTS1

XCLK

XDQ

81, 82, 84 to 87 89, 90

XRH

XRV

XRDY

SDA32SCL

TEST5

TEST4

TEST3

TEST2

TEST1

TEST0

64 to 67, 69 to 72

XTRI

chrominance of 16-bit input

BOUNDARY

SCAN

TEST

CLOCK GENERATION

AND

POWER-ON CONTROL

ANALOG

DUAL

ADC

DIGITAL

DECODER

WITH

ADAPTIVE

COMB

FILTER

AUDIO CLOCK

GENERATION

ITRDY

ICLK

IGP1

IGP0

IGPV

IGPH

IDQ

54 to 57, 59 to 62

IPD[7:0

]

HPD[7:0

]

XPD[7:0

]

RES

SAA7114H

TRST

(1)

Fig.1 Block diagram.

(1) The pins RTCO and ALRCLK are used for configuration of the I2C-bus interface

and the definition of the crystal oscillator frequency at RESET (pin strapping).

2000 Mar 15 7

Philips Semiconductors Preliminary speciﬁcation

PAL/NTSC/SECAM video decoder with adaptive PAL/NTSC comb ﬁlter, VBI-data slicer and high performance scaler

SAA7114H

7 PINNING

SYMBOL PIN TYPE DESCRIPTION

DDD(EP1)

1 P external digital pad supply voltage 1 (+3.3 V) TDO 2 O test data output for boundary scan test; note 1 TDI 3 I test data input for boundary scan test; note 1 XTOUT 4 O crystal oscillator output signal; auxiliary signal V

SS(XTAL)

5 P ground for crystal oscillator XTALO 6 O 24.576 MHz (32.11 MHz) crystal oscillator output; not connected if TTL clock

input of XTALI is used

XTALI 7 I input terminal for 24.576 MHz (32.11 MHz) crystal oscillator or connection of

external oscillator with TTL compatible square wave clock signal

DD(XTAL)

8 P supply voltage for crystal oscillator V

SSA2

9 P ground for analog inputs AI2n AI24 10 I analog input 24 V

DDA2

11 P analog supply voltage for analog inputs AI2n (+3.3 V) AI23 12 I analog input 23 AI2D 13 I differential input for ADC channel 2 (pins AI24, AI23, AI22 and AI21) AI22 14 I analog input 22 V

SSA1

15 P ground for analog inputs AI1n AI21 16 I analog input 21 V

DDA1

17 P analog supply voltage for analog inputs AI1n (+3.3 V) AI12 18 I analog input 12 AI1D 19 I differential input for ADC channel 1 (pins AI12 and AI11) AI11 20 I analog input 11 AGND 21 P analog ground connection AOUT 22 O do not connect; analog test output V

DDA0

23 P analog supply voltage (+3.3 V) for internal Clock Generation Circuit (CGC) V

SSA0

24 P ground for internal clock generation circuit V

DDD(EP2)

25 P external digital pad supply voltage 2 (+3.3 V) V

SSD(EP1)

26 P external digital pad supply ground 1 CE 27 I chip enable or reset input (with internal pull-up) LLC 28 O line-locked system clock output (27 MHz nominal) LLC2 29 O line-locked

⁄2clock output (13.5 MHz nominal)

RES 30 O reset output (active LOW) SCL 31 I(/O) serial clock input (I

C-bus) with inactive output path

SDA 32 I/O serial data input/output (I

C-bus)

DDD(ICO1)

33 P internal digital core supply voltage 1 (+3.3 V) RTS0 34 O real-time status or sync information, controlled by subaddresses 11H and 12H;

see Section 15.2.18, 15.2.19 and 15.2.20

RTS1 35 O

2000 Mar 15 8

Philips Semiconductors Preliminary speciﬁcation

PAL/NTSC/SECAM video decoder with adaptive PAL/NTSC comb ﬁlter, VBI-data slicer and high performance scaler

SAA7114H

RTCO 36 (I/)O real-time control output; contains information about actual system clock

frequency, ﬁeld rate, odd/even sequence, decoder status, subcarrier frequency and phase and PAL sequence (see external document

“RTC Functional

Description”

, available on request); the RTCO pin is enabled via I2C-bus

bit RTCE; see notes 2, 3 and Table 34 AMCLK 37 O audio master clock output, up to 50% of crystal clock V

SSD(ICO1)

38 P internal digital core supply ground 1 ASCLK 39 O audio serial clock output ALRCLK 40 (I/)O audio left/right clock output; can be strapped to supply via a 3.3kΩ resistor to

indicate that the default 24.576 MHz crystal (ALRCLK = 0; internal pull-down)

has been replaced by a 32.110 MHz crystal (ALRCLK = 1); see notes 2 and 4 AMXCLK 41 I audio master external clock input ITRDY 42 I target ready input, image port (with internal pull-up) V

DDD(ICO2)

43 P internal digital core supply voltage 2 (+3.3 V) TEST0 44 O do not connect; reserved for future extensions and for testing: scan output ICLK 45 I/O clock output signal for image port, or optional asynchronous back-end clock

input IDQ 46 O output data qualiﬁer for image port (optional: gated clock output) ITRI 47 I(/O) imageportoutput control signal, effects all input portpins inclusive ICLK, enable

and active polarity is under software control (bits IPE in subaddress 87H); output

path used for testing: scan output IGP0 48 O general purpose output signal 0; image port (controlled by subaddresses

84H and 85H) IGP1 49 O general purpose output signal 1; image port (controlled by subaddresses

84H and 85H) V

SSD(EP2)

50 P external digital pad supply ground 2

DDD(EP3)

51 P external digital pad supply voltage 3 (+3.3 V)

IGPV 52 O multi purpose vertical reference output signal; image port (controlled by

subaddresses 84H and 85H) IGPH 53 O multi purpose horizontal reference output signal; image port (controlled by

subaddresses 84H and 85H) IPD7 to IPD4 54 to 57 O image port data outputs V

DDD(ICO3)

58 P internal digital core supply voltage 3 (+3.3 V) IPD3 to IPD0 59 to 62 O image port data output V

SSD(ICO2)

63 P internal digital core supply ground 2 HPD7 to HPD4 64 to 67 I/O host port data I/O, carries UV chrominance information in 16-bit video I/O modes V

DDD(ICO4)

68 P internal digital core supply voltage 4 (+3.3 V) HPD3 to HPD0 69 to 72 I/O host port data I/O, carries UV chrominance information in 16-bit video I/O modes TEST1 73 I do not connect; reserved for future extensions and for testing: scan input TEST2 74 I do not connect; reserved for future extensions and for testing: scan input V

DDD(EP4)

75 P external digital pad supply voltage 4 (+3.3 V) V

SSD(EP3)

76 P external digital pad supply ground 3 TEST3 77 I do not connect; reserved for future extensions and for testing: scan input

SYMBOL PIN TYPE DESCRIPTION

2000 Mar 15 9

Philips Semiconductors Preliminary speciﬁcation

PAL/NTSC/SECAM video decoder with adaptive PAL/NTSC comb ﬁlter, VBI-data slicer and high performance scaler

SAA7114H

Notes

1. In accordance with the

“IEEE1149.1”

standard the pads TDI, TMS, TCK and TRST are input pads with an internal

pull-up transistor and TDO is a 3-state output pad.

2. Pin strapping is done by connecting the pin to supply via a 3.3 kΩ resistor. During the power-up reset sequence the corresponding pins are switched to input mode to read the strapping level. For the default setting no strapping resistor is necessary (internal pull-down).

3. Pin RTCO: operates as I2C-bus slave address pin; RTCO = 0 slave address 42H/43H (default); RTCO = 1 slave address 40H/41H.

4. Pin ALRCLK: 0 = 24.576 MHz crystal (default); 1 = 32.110 MHz crystal.

5. For board design without boundary scan implementation connect the TRST pin to ground.

6. This pin provides easy initialization of the Boundary Scan Test (BST) circuit. TRST can be used to force the Test Access Port (TAP) controller to the TEST_LOGIC_RESET state (normal operation) at once.

TEST4 78 O do not connect; reserved for future extensions and for testing: scan output TEST5 79 I do not connect; reserved for future extensions and for testing: scan input XTRI 80 I X-port output control signal, affects all X-port pins (XPD7 to XPD0, XRH, XRV,

XDQ and XCLK), enable and active polarity is under software control (bits XPE

in subaddress 83H) XPD7 81 I/O expansion port data XPD6 82 I/O expansion port data V

DDD(ICO5)

83 P internal digital core supply voltage 5 (+3.3 V) XPD5 to XPD2 84 to 87 I/O expansion port data V

SSD(ICO3)

88 P internal digital core supply ground 3 XPD1 89 I/O expansion port data XPD0 90 I/O expansion port data XRV 91 I/O vertical reference I/O expansion port XRH 92 I/O horizontal reference I/O expansion port V

DDD(ICO6)

93 P internal digital core supply voltage 6 (+3.3 V) XCLK 94 I/O clock I/O expansion port XDQ 95 I/O data qualiﬁer I/O expansion port XRDY 96 O task ﬂag or ready signal from scaler, controlled by XRQT TRST 97 I test reset input (active LOW), for boundary scan test (with internal pull-up);

notes 5 and 6 TCK 98 I test clock for boundary scan test; note 1 TMS 99 I test mode select input for boundary scan test or scan test; note 1 V

SSD(EP4)

100 P external digital pad supply ground 4

SYMBOL PIN TYPE DESCRIPTION

2000 Mar 15 10

Philips Semiconductors Preliminary speciﬁcation

PAL/NTSC/SECAM video decoder with adaptive PAL/NTSC comb ﬁlter, VBI-data slicer and high performance scaler

SAA7114H

Fig.2 Pin configuration.

handbook, full pagewidth

75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52

8079787776

XTRI

TEST5

TEST4

TEST3

SSD(EP3)

DDD(EP4)

TEST2 TEST1 HPD0 HPD1 HPD2 HPD3 V

DDD(ICO4)

HPD4 HPD5 HPD6 HPD7 V

SSD(ICO2)

IPD0 IPD1 IPD2 IPD3 V

DDD(ICO3)

IPD4 IPD5 IPD6 IPD7 IGPH IGPV V

DDD(EP3)

DDD(EP1)

TDO

TDI

XTOUT

SS(XTAL)

XTALO

XTALI

DD(XTAL)

SSA2

AI24

DDA2

AI23

AI2D

AI22

SSA1

AI21

DDA1

AI12

AI1D

AI11

AGND

AOUT

DDA0

SSA0

DDD(EP2)

SSD(EP4)

TMS

TCK

XRDY

XDQ

XCLK

DDD(ICO6)

XRH

XRV

XPD0

XPD1

SSD(ICO3)

XPD2

XPD3

XPD4

XPD5

DDD(ICO5)

XPD6

XPD7

SCL

SDA

DDD(ICO1)

RTS0

RTS1

RTCO

AMCLK

SSD(ICO1)

ASCLK

ALRCLK

AMXCLK

ITRDY

DDD(ICO2)

TEST0

ICLK

IDQ

ITRI

IGP0

IGP1

SSD(EP2)

SSD(EP1)

LLC

LLC2

100

99989796959493929190898887868584838281

31323334353637383940414243444546474849

SAA7114H

RES

TRST

MHB529

2000 Mar 15 11

Philips Semiconductors Preliminary speciﬁcation

PAL/NTSC/SECAM video decoder with adaptive PAL/NTSC

comb ﬁlter, VBI-data slicer and high performance scaler

SAA7114H

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Table 1 8-bit/16-bit and alternative pin functional conﬁgurations

PIN SYMBOL

8-BIT

INPUT

MODES

16-BIT INPUT

MODES (ONLY

FOR I2C-BUS

PROGRAMMING)

ALTERNATIVE

INPUT

FUNCTIONS

8-BIT

OUTPUT

MODES

16-BIT OUTPUT

MODES (ONLY

FOR I2C-BUS

PROGRAMMING)

ALTERNATIVE

OUTPUT

FUNCTIONS

I/O

CONFIGURATION

PROGRAMMING

BITS

81, 82, 84 to 87, 89, 90

XPD7 to XPD0

D1 data input

Y data input D1

decoder output

XCODE[92H[3]] XPE[1:0]83H[1:0] + pin XTRI

94 XCLK clock

input

gated clock input

decoder clock output

XPE[1:0]83H[1:0] + pin XTRI XPCK[1:0]83H[5:4] XCKS[92H[0]]

95 XDQ data

qualiﬁer input

data qualiﬁer output (HREFand VREF gate)

XDQ[92H[1]] XPE[1:0]83H[1:0] + pin XTRI

96 XRDY input

ready output

active task A/B ﬂag

XRQT[83H[2]] XPE[1:0]83H[1:0] + pin XTRI

92 XRH horizontal

reference input

decoder horizontal reference output

XDH[92H[2]] XPE[1:0]83H[1:0] + pin XTRI

91 XRV vertical

reference input

decoder vertical reference output

XDV[1:0]92H[5:4] XPE[1:0]83H[1:0] + pin XTRI

80 XTRI output

enable input

XPE[1:0]83H[1:0]

64 to 67, 69 to 72

HPD7 to HPD0

UV data input UV scaler output ICODE[93H[7]]

ISWP[1:0]85H[7:6] I8_16[93H[6]] IPE[1:0]87H[1:0] + pin ITRI

2000 Mar 15 12

Philips Semiconductors Preliminary speciﬁcation

PAL/NTSC/SECAM video decoder with adaptive PAL/NTSC

comb ﬁlter, VBI-data slicer and high performance scaler

SAA7114H

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54 to 57, 59 to 62

IPD7 to IPD0

D1 scaler output

Y scaler output ICODE[93H[7]]

ISWP[1:0]85H[7:6] I8_16[93H[6]] IPE[1:0]87H[1:0] + pin ITRI

45 ICLK clock

output

clock input ICKS[1:0]80H[1:0]

IPE[1:0]87H[1:0] + pin ITRI

46 IDQ data

qualiﬁer output

gated clock output

ICKS[3:2]80H[3:2] IDQP[85H[0]] IPE[1:0]87H[1:0] + pin ITRI

42 ITRDY target

ready input

53 IGPH H-gate

output

extended H-gate, horizontal pulses

IDH[1:0]84H[1:0] IRHP[85H[1]] IPE[1:0]87H[1:0] + pin ITRI

52 IGPV V-gate

output

V-sync, vertical pulses

IDV[1:0]84H[3:2] IRVP[85H[2]] IPE[1:0]87H[1:0] + pin ITRI

49 IGP1 general

purpose

IDG1[1:0]84H[5:4] IG1P[85H[3]] IPE[1:0]87H[1:0] + pin ITRI

48 IGP0 general

purpose

IDG0[1:0]84H[7:6] IG0P[85H[4]] IPE[1:0]87H[1:0] + pin ITRI

47 ITRI output

enable input

PIN SYMBOL

8-BIT

INPUT

MODES

16-BIT INPUT

MODES (ONLY

FOR I

C-BUS

PROGRAMMING)

ALTERNATIVE

INPUT

FUNCTIONS

8-BIT

OUTPUT

MODES

16-BIT OUTPUT

MODES (ONLY

FOR I2C-BUS

PROGRAMMING)

ALTERNATIVE

OUTPUT

FUNCTIONS

I/O

CONFIGURATION

PROGRAMMING

BITS

2000 Mar 15 13

Philips Semiconductors Preliminary speciﬁcation

PAL/NTSC/SECAM video decoder with adaptive PAL/NTSC comb ﬁlter, VBI-data slicer and high performance scaler

SAA7114H

8 FUNCTIONAL DESCRIPTION

8.1 Decoder

8.1.1 ANALOG INPUT PROCESSING The SAA7114H offers six analog signal inputs, two analog

main channels with source switch, clamp circuit, analog amplifier, anti-alias filter and video 9-bit CMOS ADC; see Fig.6.

8.1.2 ANALOG CONTROL CIRCUITS The anti-alias filters are adapted to the line-locked clock

frequency via a filter control circuit. The characteristics are shown in Fig.3. During the vertical blanking period, gain and clamping control are frozen.

Fig.3 Anti-alias filter.

handbook, full pagewidth

(dB)

−42 024 68101214

f (MHz)

MGD138

−6

−12

−18

−24

−30

−36

2000 Mar 15 14

Philips Semiconductors Preliminary speciﬁcation

PAL/NTSC/SECAM video decoder with adaptive PAL/NTSC comb ﬁlter, VBI-data slicer and high performance scaler

SAA7114H

8.1.2.1 Clamping

The clamp control circuit controls the correct clamping of the analog input signals. The coupling capacitor is also used to store and filter the clamping voltage. An internal digital clamp comparator generates the information with respect to clamp-up or clamp-down. The clamping levels for the two ADC channels are fixed for luminance (60) and chrominance (128). Clamping time in normal use is set with the HCL pulse at the back porch of the video signal.

8.1.2.2 Gain control

The gain control circuit receives (via the I2C-bus) the static gain levels for the two analog amplifiers or controls one of theseamplifiersautomaticallyviaabuilt-inAutomaticGain Control (AGC) as part of the Analog Input Control (AICO).

The AGC (automatic gain control for luminance) is used to amplify a CVBS or Y signal to the required signal amplitude, matched to the ADCs input voltage range. The AGCactive time is the sync bottom ofthe video signal.

Signal (white) peak control limits the gain at signal overshoots.Theflow charts (see Figs 7 and 8) show more details of the AGC. The influence of supply voltage variation within the specified range is automatically eliminated by clamp and automatic gain control.

Fig.4 Analog line with clamp (HCL) and gain

range (HSY).

handbook, halfpage

HCL

MGL065

HSY

analog line blanking

TV line

255

GAIN CLAMP

Fig.5 Automatic gain range.

handbook, halfpage

analog input level

controlled

ADC input level

maximum

minimum

range 9 dB

0 dB

MHB325

+3 dB

−6 dB

(1 V (p-p) 18/56 Ω)

2000 Mar 15 15

Philips Semiconductors Preliminary speciﬁcation

PAL/NTSC/SECAM video decoder with adaptive PAL/NTSC

comb ﬁlter, VBI-data slicer and high performance scaler

SAA7114H

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MHB530

HOLDG GAFIX WPOFF GUDL0-GUDL2 GAI20-GAI28 GAI10-GAI18 HLNRS UPTCV

MODE 3 MODE 2 MODE 1 MODE 0

HSY

HCL

GLIMB GLIMT WIPA SLTCA

ANALOG CONTROL

VBSL

SOURCE

SWITCH

CLAMP

CIRCUIT

ANALOG

AMPLIFIER

DAC9

ANTI-ALIAS

FILTER

BYPASS

SWITCH

ADC2

SOURCE

SWITCH

CLAMP

CIRCUIT

ANALOG

AMPLIFIER

DAC9

ANTI-ALIAS

FILTER

BYPASS

SWITCH

ADC1

VBLNK SVREF

CROSS MULTIPLEXER

VERTICAL BLANKING CONTROL

CLAMP

CONTROL

GAIN

CONTROL

ANTI-ALIAS

CONTROL

MODE

CONTROL

FUSE [1:0

]

FUSE [1:0

]

AOSL [1:0

]

AGND

CVBS/CHRCVBS/LUM

AD1BYPAD2BYP

9999

AOUT

18 19 20

15 9

13 10, 12,

14, 16

17 11

AI2D

AI12

AI24 to AI21

AI1D AI11

TEST

SELECTOR

AND

BUFFER

DDA1

SSA2

DDA2

SSA1

Fig.6 Analog input processing using the SAA7114H as differential front-end with 9-bit ADC.

2000 Mar 15 16

Philips Semiconductors Preliminary speciﬁcation

PAL/NTSC/SECAM video decoder with adaptive PAL/NTSC comb ﬁlter, VBI-data slicer and high performance scaler

SAA7114H

Fig.7 Gain flow chart.

handbook, full pagewidth

ANALOG INPUT

AMPLIFIER

ANTI-ALIAS FILTER

ADC

LUMA/CHROMA DECODER

HSY

254

248

X = 0

X = 1

−1/LLC2

+1/LLC2 −1/LLC2

+/− 0

+1/F

+1/L

GAIN ACCUMULATOR (18 BITS)

ACTUAL GAIN VALUE 9-BIT (AGV) [−3/+6 dB

]

STOP

HSY

UPDATE

FGV

MHB531

AGV

GAIN VALUE 9-BIT

VBLK

NO ACTION

DAC

gain

HOLDG

X = system variable. Y = (IAGV − FGVI) > GUDL. VBLK = vertical blanking pulse. HSY = horizontal sync pulse. AGV = actual gain value. FGV = frozen gain value.

2000 Mar 15 17

Philips Semiconductors Preliminary speciﬁcation

PAL/NTSC/SECAM video decoder with adaptive PAL/NTSC comb ﬁlter, VBI-data slicer and high performance scaler

SAA7114H

Fig.8 Clamp and gain flow chart.

WIPE = white peak level (254). SBOT = sync bottom level (1). CLL = clamp level [60 Y (128 C)]. HSY = horizontal sync pulse. HCL = horizontal clamp pulse.

handbook, full pagewidth

+ CLAMP − CLAMP

NO CLAMP

10 10

01 10

MGC647

fast − GAIN

slow + GAIN

+ GAIN − GAIN

HCL HSY

ADC

SBOT

WIPE

CLL

ANALOG INPUT

GAIN -><- CLAMP

VBLK

NO BLANKING ACTIVE

2000 Mar 15 18

Philips Semiconductors Preliminary speciﬁcation

PAL/NTSC/SECAM video decoder with adaptive PAL/NTSC

comb ﬁlter, VBI-data slicer and high performance scaler

SAA7114H

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8.1.3 CHROMINANCE AND LUMINANCE PROCESSING

dbook, full pagewidth

MHB532

CVBS-IN

or CHR-IN

CODE

SECS

HUEC

DCVF

QUADRATURE

DEMODULATOR

PAL DELAY LINE

SECAM

RECOMBINATION

PHASE

DEMODULATOR

AMPLITUDE DETECTOR

BURST GATE

ACCUMULATOR

LOOP FILTER

LOW-PASS 1

DOWNSAMPLING

SUBCARRIER

GENERATION 2

FCTC

ACGC

CGAIN[6:0

]

IDEL[3:0

]

INCS

RTCO

UV-

ADJUSTMENT

SECAM

PROCESSING

fH/2 switch signal

ADAPTIVE

COMB FILTER

CCOMB YCOMB

LDEL BYPS

LUFI[3:0

]

CSTD[2:0

]

YDEL[2:0

]

LOW-PASS 2

CHBW

CHROMA

GAIN

CONTROL

INTERPOLATION

LOW-PASS 3

LUBW

QUADRATURE

MODULATOR

CDTO

CSTD[2:0

]

SUBCARRIER

GENERATION 1

CHROMINANCE

INCREMENT

DTO-RESET

SUBCARRIER

INCREMENT

GENERATION

AND

DIVIDER

CHROMINANCE

INCREMENT

DELAY

LDEL YCOMB

SUBTRACTOR

DELAY

COMPENSATION

CVBS-IN

or Y-IN

CHR

LUMINANCE-PEAKING

LOW-PASS,

Y-DELAY ADJUSTMENT

LCBW[2:0

]

Y/CVBS

DBRI[7:0

]

DCON[7:0

]

DSAT[7:0

]

RAWG[7:0

]

RAWO[7:0

]

COLO

BRIGHTNESS

CONTRAST

SATURATION

CONTROL

RAW DATA

GAIN AND

OFFSET

CONTROL

LDEL

YCOMB

Y-OUT/ CVBS OUT

UV-OUT

HREF-OUT

SET_RAW

SET_VBI

SET_RAW

SET_VBI

SET_RAW

SET_VBI

SET_RAW

SET_VBI

Fig.9 Chrominance and luminance processing.

2000 Mar 15 19

Philips Semiconductors Preliminary speciﬁcation

PAL/NTSC/SECAM video decoder with adaptive PAL/NTSC comb ﬁlter, VBI-data slicer and high performance scaler

SAA7114H

8.1.3.1 Chrominance path

The 9-bit CVBS or chrominance input signal is fed to the inputofa quadrature demodulator, where it is multiplied by twotime-multiplexed subcarrier signalsfromthe subcarrier generation block 1 (0° and 90° phase relationship to the demodulator axis). The frequency is dependent on the chosen colour standard.

The time-multiplexed output signals of the multipliers are low-pass filtered (low-pass 1). Eight characteristics are programmable via LCWB3 to LCWB0 to achieve the desired bandwidth for the colour difference signals (PAL, NTSC) or the 0° and 90° FM signals (SECAM).

Thechrominance low-pass 1characteristicalso influences the grade of cross-luminance reduction during horizontal colour transients (large chrominance bandwidth means strong suppression of cross-luminance). If the Y-comb filterisdisabledbyYCOMB = 0thefilterinfluencesdirectly the width of the chrominance notch within the luminance path (large chrominance bandwidth means wide chrominance notch resulting to lower luminance bandwidth).

The low-pass filtered signals are fed to the adaptive comb filter block. The chrominance components are separated from the luminance via a two line vertical stage (four lines for PAL standards) and a decision logic between the filtered and the non-filtered output signals. This block is bypassed for SECAM signals. The comb filter logic can be enabled independently for the succeeding luminance and chrominance processing by YCOMB (subaddress 09H, bit 6) and/or CCOMB (subaddress 0EH, bit 0). It is always bypassed during VBI or raw data lines programmable by the LCRn registers (subaddresses 41H to 57H), see Section 8.2.

TheseparatedUV-componentsarefurtherprocessedbya secondfilterstage(low-pass 2)tomodifythechrominance bandwidth without influence to the luminance path. It’s characteristic is controlled by CHBW (subaddress 10H, bit 3). For the complete transfer characteristic of low-passes 1 and 2 see Figs 10 and 11.

The SECAM processing (bypassed for QUAM standards) contains the following blocks:

• Baseband ‘bell’ filters to reconstruct the amplitude and phase equalized 0° and 90° FM signals

• Phase demodulator and differentiator (FM-demodulation)

• De-emphasis filter to compensate the pre-emphasized input signal, including frequency offset compensation (DB or DR white carrier values are subtracted from the signal, controlled by the SECAM switch signal).

The succeeding chrominance gain control block amplifies or attenuates the UV-signal according to the required ITU 601/656 levels. It is controlled by the output signal from the amplitude detection circuit within the burst processing block.

The burst processing block provides the feedback loop of the chrominance PLL and contains:

• Burst gate accumulator

• Colour identification and killer

• Comparison nominal/actual burst amplitude

(PAL/NTSC standards only)

• Loop filter chrominance gain control (PAL/NTSC standards only)

• Loop filter chrominance PLL (only active for PAL/NTSC standards)

• PAL/SECAM sequence detection, H/2-switch generation.

The increment generation circuit produces the Discrete Time Oscillator (DTO) increment for both subcarrier generation blocks. It contains a division by the increment of the line-locked clock generator to create a stable phase-locked sine signal under all conditions (e.g. for non-standard signals).

The PAL delay line block eliminates crosstalk between the chrominance channels in accordance with the PAL standard requirements. For NTSC colour standards the delay line can be used as an additional vertical filter. If desired, it can be switched off by DCVF = 1. It is always disabledduringVBIorrawdata lines programmable by the LCRn registers (subaddresses 41H to 47H), see Section 8.2. The embedded line delay is also used for SECAM recombination (cross-over switches).

2000 Mar 15 20

Philips Semiconductors Preliminary speciﬁcation

PAL/NTSC/SECAM video decoder with adaptive PAL/NTSC comb ﬁlter, VBI-data slicer and high performance scaler

SAA7114H

handbook, full pagewidth

MHB533

−60

−57

−54

−51

−48

−45

−42

−39

−36

−33

−30

−27

−24

−21

−18

−15

−12

−9

−6

−3

0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 4.0

(dB)

f (MHz)

−60

−57

−54

−51

−48

−45

−42

−39

−36

−33

−30

−27

−24

−21

−18

−15

−12

−9

−6

−3

(dB)

0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 4.0

f (MHz)

(1) (2) (3) (4)

(5) (6) (7) (8)

Fig.10 Transfer characteristics of the chrominance low-pass at CHBW = 0.

(1) LCBW[2:0] = 000. (2) LCBW[2:0] = 010. (3) LCBW[2:0] = 100. (4) LCBW[2:0] = 110.

(5) LCBW[2:0] = 001. (6) LCBW[2:0] = 011. (7) LCBW[2:0] = 101. (8) LCBW[2:0] = 111.

2000 Mar 15 21

Philips Semiconductors Preliminary speciﬁcation

PAL/NTSC/SECAM video decoder with adaptive PAL/NTSC comb ﬁlter, VBI-data slicer and high performance scaler

SAA7114H

handbook, full pagewidth

MHB534

−60

−57

−54

−51

−48

−45

−42

−39

−36

−33

−30

−27

−24

−21

−18

−15

−12

−9

−6

−3

0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 4.0

(dB)

f (MHz)

−60

−57

−54

−51

−48

−45

−42

−39

−36

−33

−30

−27

−24

−21

−18

−15

−12

−9

−6

−3

(dB)

0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 4.0

f (MHz)

(1) (2) (3) (4)

(5) (6) (7) (8)

Fig.11 Transfer characteristics of the chrominance low-pass at CHBW = 1.

(1) LCBW[2:0] = 000. (2) LCBW[2:0] = 010. (3) LCBW[2:0] = 100. (4) LCBW[2:0] = 110.

(5) LCBW[2:0] = 001. (6) LCBW[2:0] = 011. (7) LCBW[2:0] = 101. (8) LCBW[2:0] = 111.

2000 Mar 15 22

Philips Semiconductors Preliminary speciﬁcation

PAL/NTSC/SECAM video decoder with adaptive PAL/NTSC comb ﬁlter, VBI-data slicer and high performance scaler

SAA7114H

8.1.3.2 Luminance path

The rejection of the chrominance components within the 9-bit CVBS or Y input signal is done by subtracting the re-modulated chrominance signal from the CVBS input.

The comb filtered UV-components are interpolated (upsampled) by the low-pass 3 block. It’s characteristic is controlled by LUBW (subaddress 09H, bit 4) to modify the width of the chrominance ‘notch’ without influence to the chrominance path. The programmable frequency characteristics available in conjunction with the LCBW2 to LCBW0 settings can be seen in Figs 12 to 15. Notethatthesefrequencycurves are only valid for Y-comb disabled filter mode (YCOMB = 0). in comb filter mode the frequency response is flat. The centre frequency of the notch is automatically adapted to the chosen colour standard.

The interpolated UV-samples are multiplied by two time-multiplexed subcarrier signals from the subcarrier generation block 2. This second DTO is locked to the first subcarrier generator by an increment delay circuit matched to the processing delay, which is different for PAL and NTSC standards according to the chosen comb filter algorithm. The two modulated signals are finally added to build the re-modulated chrominance signal.

The frequency characteristic of the separated luminance signal can be further modified by the succeeding luminance filter block. It can be configured as peaking (resolution enhancement) or low-pass block by LUFI3 to LUFI0 (subaddress 09H, bits 3 to 0). The 16 resulting frequency characteristics can be seen in Fig.16. The LUFI3 to LUFI0 settings can be used as a user programmable sharpness control.

The luminance filter block also contains the adjustable Y-delay part; programmable by YDEL2 to YDEL0 (subaddress 11H, bits 2 to 0).

2000 Mar 15 23

Philips Semiconductors Preliminary speciﬁcation

PAL/NTSC/SECAM video decoder with adaptive PAL/NTSC comb ﬁlter, VBI-data slicer and high performance scaler

SAA7114H

handbook, full pagewidth

MHB535

−60

−57

−54

−51

−48

−45

−42

−39

−36

−33

−30

−27

−24

−21

−18

−15

−12

−9

−6

−3

0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 4.0 4.2 4.4 4.6 4.8 5.0

(dB)

f (MHz)

−60

−57

−54

−51

−48

−45

−42

−39

−36

−33

−30

−27

−24

−21

−18

−15

−12

−9

−6

−3

0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 4.0 4.2 4.4 4.6 4.8 5.0

(dB)

f (MHz)

(5) (6) (7) (8)

(1) (2) (3) (4)

Fig.12 Transfer characteristics of the luminance notch filter in 3.58 MHz mode (Y-comb filter disabled) at

LUBW = 0.

(1) LCBW[2:0] = 000. (2) LCBW[2:0] = 010. (3) LCBW[2:0] = 100. (4) LCBW[2:0] = 110.

(5) LCBW[2:0] = 001. (6) LCBW[2:0] = 011. (7) LCBW[2:0] = 101. (8) LCBW[2:0] = 111.

2000 Mar 15 24

Philips Semiconductors Preliminary speciﬁcation

PAL/NTSC/SECAM video decoder with adaptive PAL/NTSC comb ﬁlter, VBI-data slicer and high performance scaler

SAA7114H

handbook, full pagewidth

MHB536

0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 4.0 4.2 4.4 4.6 4.8 5.0

−60

−57

−54

−51

−48

−45

−42

−39

−36

−33

−30

−27

−24

−21

−18

−15

−12

−9

−6

−3

(dB)

f (MHz)

−60

−57

−54

−51

−48

−45

−42

−39

−36

−33

−30

−27

−24

−21

−18

−15

−12

−9

−6

−3

0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 4.0 4.2 4.4 4.6 4.8 5.0

(dB)

f (MHz)

(5) (6) (7) (8)

(1) (2) (3) (4)

Fig.13 Transfer characteristics of the luminance notch filter in 3.58 MHz mode (Y-comb filter disabled) at

LUBW = 1.

(1) LCBW[2:0] = 000 (2) LCBW[2:0] = 010 (3) LCBW[2:0] = 100 (4) LCBW[2:0] = 110

(5) LCBW[2:0] = 001 (6) LCBW[2:0] = 011 (7) LCBW[2:0] = 101 (8) LCBW[2:0] = 111

2000 Mar 15 25

Philips Semiconductors Preliminary speciﬁcation

PAL/NTSC/SECAM video decoder with adaptive PAL/NTSC comb ﬁlter, VBI-data slicer and high performance scaler

SAA7114H

handbook, full pagewidth

MHB537

−60

−57

−54

−51

−48

−45

−42

−39

−36

−33

−30

−27

−24

−21

−18

−15

−12

−9

−6

−3

0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 4.0 4.2 4.4 4.6 4.8 5.0

(dB)

f (MHz)

−60

−57

−54

−51

−48

−45

−42

−39

−36

−33

−30

−27

−24

−21

−18

−15

−12

−9

−6

−3

0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 4.0 4.2 4.4 4.6 4.8 5.0

(dB)

f (MHz)

(5) (6) (7) (8)

(1) (2) (3) (4)

Fig.14 Transfer characteristics of the luminance notch filter in 4.43 MHz mode (Y-comb filter disabled) at

LUBW = 0.

(1) LCBW[2:0] = 000. (2) LCBW[2:0] = 010. (3) LCBW[2:0] = 100. (4) LCBW[2:0] = 110.

(5) LCBW[2:0] = 001. (6) LCBW[2:0] = 011. (7) LCBW[2:0] = 101. (8) LCBW[2:0] = 111.

2000 Mar 15 26

Philips Semiconductors Preliminary speciﬁcation

PAL/NTSC/SECAM video decoder with adaptive PAL/NTSC comb ﬁlter, VBI-data slicer and high performance scaler

SAA7114H

handbook, full pagewidth

MHB538

−60

−57

−54

−51

−48

−45

−42

−39

−36

−33

−30

−27

−24

−21

−18

−15

−12

−9

−6

−3

0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 4.0 4.2 4.4 4.6 4.8 5.0

(dB)

f (MHz)

−60

−57

−54

−51

−48

−45

−42

−39

−36

−33

−30

−27

−24

−21

−18

−15

−12

−9

−6

−3

0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 4.0 4.2 4.4 4.6 4.8 5.0

(dB)

f (MHz)

(5) (6) (7) (8)

(1) (2) (3) (4)

Fig.15 Transfer characteristics of the luminance notch filter in 4.43 MHz mode (Y-comb filter disabled) at

LUBW = 1.

(1) LCBW[2:0] = 000. (2) LCBW[2:0] = 010. (3) LCBW[2:0] = 100. (4) LCBW[2:0] = 110.

(5) LCBW[2:0] = 001. (6) LCBW[2:0] = 011. (7) LCBW[2:0] = 101. (8) LCBW[2:0] = 111.

2000 Mar 15 27

Philips Semiconductors Preliminary speciﬁcation

PAL/NTSC/SECAM video decoder with adaptive PAL/NTSC comb ﬁlter, VBI-data slicer and high performance scaler

SAA7114H

handbook, full pagewidth

MHB539

−1

(dB)

f (MHz)

0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0

f (MHz)

0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0

(8)

(7)

(6)

(5)

(4)

(3)

(2)

(1)

(9) (10) (11) (12) (13) (14) (15) (16)

−39

−36

−33

−30

−27

−24

−21

−18

−15

−12

−9

−6

−3

Fig.16 Transfer characteristics of the luminance peaking/low-pass filter (sharpness).

(1) LUFI[3:0] = 0001. (2) LUFI[3:0] = 0010. (3) LUFI[3:0] = 0011. (4) LUFI[3:0] = 0100. (5) LUFI[3:0] = 0101. (6) LUFI[3:0] = 0110. (7) LUFI[3:0] = 0111. (8) LUFI[3:0] = 0000.

(9) LUFI[3:0] = 1000. (10) LUFI[3:0] = 1001. (11) LUFI[3:0] = 1010. (12) LUFI[3:0] = 1011. (13) LUFI[3:0] = 1100. (14) LUFI[3:0] = 1101. (15) LUFI[3:0] = 1110. (16) LUFI[3:0] = 1111.

2000 Mar 15 28

Philips Semiconductors Preliminary speciﬁcation

PAL/NTSC/SECAM video decoder with adaptive PAL/NTSC comb ﬁlter, VBI-data slicer and high performance scaler

SAA7114H

8.1.3.3 Brightness Contrast Saturation (BCS) control and decoder output levels

The resulting Y (CVBS) and UV-signals are fed to the BCS block, which contains the following functions:

• Chrominance saturation control by DSAT7 to DSAT0

• Luminance contrast and brightness control by DCON7 to DCON0 and DBRI7 to DBRI0

• Raw data (CVBS) gain and offset adjustment by RAWG7 to RAWG0 and RAWO7 to RAWO0

• Limiting YUV or CVBS to the values 1 (minimum) and 254 (maximum) to fulfil

“ITU Recommendation 601/656”

Fig.17 YUV range for scaler input and X-port output.

“ITU Recommendation 601/656”

digital levels with default BCS (decoder) settings DCON[7:0] = 44H, DBRI[7:0] = 80H and DSAT[7:0] = 40H.

Equations for modification to the YUV levels via BCS control I2C-bus bytes DBRI, DCON and DSAT. Luminance:

Chrominance: It should be noted that the resulting levels are limited to 1 to 254 in accordance with

“ITU Recommendation 601/656”

OUT

Int

DCON

-----------------

Y 128–()× DBRI+=

OUT

Int

DSAT

--------------- -

CRCB, 128–()× 128+=

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LUMINANCE 100%

+255 +235

+128

+16

white

black

U-COMPONENT

+255 +240

+212 +212

+128

+16

+44

blue 100% blue 75%

yellow 75% yellow 100%

colourless

V-COMPONENT

+255 +240

+128

+16

+44

red 100% red 75%

cyan 75%

cyan 100%

colourless

MGC634

a. Y output range. b. U output range (CB). c. V output range (CR).

2000 Mar 15 29

Philips Semiconductors Preliminary speciﬁcation

PAL/NTSC/SECAM video decoder with adaptive PAL/NTSC comb ﬁlter, VBI-data slicer and high performance scaler

SAA7114H

Fig.18 CVBS (raw data) range for scaler input, data slicer and X-port output.

CVBS levels with default settings RAWG[7:0] = 64 and RAWO[7:0] = 128. Equation for modification of the raw data levels via bytes RAWG and RAWO:

It should be noted that the resulting levels are limited to 1 to 254 in accordance with “

ITU Recommendation 601/656”

CVBS

OUT

Int

RAWG

------------------

CVBS

nom

128–()× RAWO+=

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LUMINANCE

+255 +209

+71

+60

white

sync bottom

black shoulder

black

SYNC

LUMINANCE

+255

+199

+60

white

sync bottom

black shoulder = black

SYNC

MGD700

a. Sources containing 7.5 IRE black level offset (e.g. NTSC M).

b. Sources not containing black level offset.

2000 Mar 15 30

Philips Semiconductors Preliminary speciﬁcation

PAL/NTSC/SECAM video decoder with adaptive PAL/NTSC comb ﬁlter, VBI-data slicer and high performance scaler

SAA7114H

8.1.4 SYNCHRONIZATION The prefiltered luminance signal is fed to the

synchronization stage. Its bandwidth is further reduced to 1 MHz in a low-pass filter. The sync pulses are sliced and fed to the phase detectors where they are compared with the sub-divided clock frequency. The resulting output signal is applied to the loop filter to accumulate all phase deviations. Internal signals (e.g. HCL and HSY) are generated in accordance with analog front-end requirements. The loop filter signal drives an oscillator to generate the line frequency control signal LFCO, see Fig.19.

The detection of ‘pseudo syncs’ as part of the macrovision copy protection standard is also done within the synchronization circuit.

The result is reported as flag COPRO within the decoder status byte at subaddress 1FH.

8.1.5 CLOCK GENERATION CIRCUIT The internal CGC generates all clock signals required for

the video input processor.

The internal signal LFCO is a digital-to-analog converted signal provided by the horizontal PLL. It is the multiple of the line frequency:

6.75 MHz = 429 × fH (50 Hz), or

6.75 MHz = 432 × fH (60 Hz).

Internally the LFCO signal is multiplied by a factor of 2 and 4 in the PLL circuit (including phase detector, loop filtering, VCO and frequency divider) to obtain the output clock signals. The rectangular output clocks have a 50% duty factor.

Table 2 Decoder clock frequencies

CLOCK FREQUENCY (MHz)

XTALO 24.576 or 32.110 LLC 27 LLC2 13.5 LLC4 (internal) 6.75 LLC8 (virtual) 3.375

Fig.19 Block diagram of the clock generation circuit.

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BAND PASS

FC = LLC/4

ZERO

CROSS

DETECTION

PHASE

DETECTION

LOOP

FILTER

DIVIDER

1/2

DIVIDER

1/2

OSCILLATOR

MHB330

LLC2

LLC

LFCO

8.1.6 POWER-ON RESET AND CHIP ENABLE (CE) INPUT A missing clock, insufficient digital or analog V

DDA0

supply voltages (below 2.7 V) will start the reset sequence; all outputs are forced to 3-state (see Fig.20). The indicator output RES is LOW for about 128 LLC after the internal resetandcan be applied to reset other circuits of the digital TV system.

It is possible to force a reset by pulling the Chip Enable (CE) to ground. After the rising edge of CE and sufficient power supply voltage, the outputs LLC, LLC2 and SDA return from 3-state to active, while the other signals have to be activated via programming.

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