Philips SAA7111AHZ-01, SAA7111AHZ-02, SAA7111AHZ-03, SAA7111AH-01, SAA7111AH-03 Datasheet

DATA SH EET

Product speciﬁcation Supersedes data of 1997 May 26 File under Integrated Circuits, IC22

1998 May 15

INTEGRATED CIRCUITS

SAA7111A

Enhanced Video Input Processor (EVIP)

1998 May 15 2

Philips Semiconductors Product speciﬁcation

Enhanced Video Input Processor (EVIP) SAA7111A

CONTENTS

1 FEATURES 2 APPLICATIONS 3 GENERAL DESCRIPTION 4 QUICK REFERENCE DATA 5 ORDERING INFORMATION 6 BLOCK DIAGRAM 7 PINNING 8 FUNCTIONAL DESCRIPTION

8.1 Analog input processing

8.2 Analog control circuits

8.2.1 Clamping

8.2.2 Gain control

8.3 Chrominance processing

8.4 Luminance processing

8.5 RGB matrix

8.6 VBI-data bypass

8.7 VPO-bus (digital outputs)

8.8 Reference signals HREF, VREF and CREF

8.9 Synchronization

8.10 Clock generation circuit

8.11 Power-on reset and CE input

8.12 RTCO output

8.13 The Line-21 text slicer

8.13.1 Suggestions for I2C-bus interface of the display software reading line-21 data

9 BOUNDARY-SCAN TEST

9.1 Initialization of boundary-scan circuit

9.2 Device identification codes

10 GAIN CHARTS 11 LIMITING VALUES 12 CHARACTERISTICS 13 TIMING DIAGRAMS 14 CLOCK SYSTEM

14.1 Clock generation circuit

14.2 Power-on control

15 OUTPUT FORMATS 16 APPLICATION INFORMATION

16.1 Layout hints

17 I2C-BUS DESCRIPTION

17.1 I2C-bus format

17.2 I2C-bus detail

17.2.1 Subaddress 00

17.2.2 Subaddress 02

17.2.3 Subaddress 03

17.2.4 Subaddress 04

17.2.5 Subaddress 05

17.2.6 Subaddress 06

17.2.7 Subaddress 07

17.2.8 Subaddress 08

17.2.9 Subaddress 09

17.2.10 Subaddress 0A

17.2.11 Subaddress 0B

17.2.12 Subaddress 0C

17.2.13 Subaddress 0D

17.2.14 Subaddress 0E

17.2.15 Subaddress 10

17.2.16 Subaddress 11

17.2.17 Subaddress 12

17.2.18 Subaddress 13

17.2.19 Subaddress 15

17.2.20 Subaddress 16

17.2.21 Subaddress 17

17.2.22 Subaddress 1A (read-only register)

17.2.23 Subaddress 1B (read-only register)

17.2.24 Subaddress 1C (read-only register)

17.2.25 Subaddress 1F (read-only register) 18 FILTER CURVES

18.1 Anti-alias filter curve

18.2 TUF-block filter curve

18.3 Luminance filter curves

18.4 Chrominance filter curves 19 I2C-BUS START SET-UP 20 PACKAGE OUTLINES 21 SOLDERING

21.1 Introduction

21.2 Reflow soldering

21.3 Wave soldering

21.4 Repairing soldered joints 22 DEFINITIONS 23 LIFE SUPPORT APPLICATIONS 24 PURCHASE OF PHILIPS I2C COMPONENTS

1998 May 15 3

Philips Semiconductors Product speciﬁcation

Enhanced Video Input Processor (EVIP) SAA7111A

1 FEATURES

• Four analog inputs, internal analog source selectors,

e.g. 4 × CVBS or 2 × Y/C or (1 × Y/C and 2 × CVBS)

• Two analog preprocessing channels

• Fully programmable static gain for the main channels or

automatic gain control for the selected CVBS or Y/C channel

• Switchable white peak control

• Two built-in analog anti-aliasing filters

• Two 8-bit video CMOS analog-to-digital converters

• On-chip clock generator

• Line-locked system clock frequencies

• Digital PLL for horizontal-sync processing and clock

generation

• Requires only one crystal (24.576 MHz) for all standards

• Horizontal and vertical sync detection

• Automatic detection of 50 and 60 Hz field frequency,

and automatic switching between PAL and NTSC standards

• Luminance and chrominance signal processing for

PAL BGHI, PAL N, PAL M, NTSC M, NTSC N, NTSC 4.43, NTSC-Japan and SECAM

• User programmable luminance peaking or aperture

correction

• Cross-colour reduction for NTSC by chrominance comb

filtering

• PAL delay line for correcting PAL phase errors

• Real time status information output (RTCO)

• Brightness Contrast Saturation (BCS) control on-chip

• The YUV (CCIR-601) bus supports a data rate of:

– 864 × f

= 13.5 MHz for 625 line sources

– 858 × fH= 13.5 MHz for 525 line sources.

• Data output streams for 16, 12 or 8-bit width with the

following formats: – YUV4:1:1 (12-bit) – YUV4:2:2 (16-bit) – YUV4:2:2 (CCIR-656) (8-bit) – RGB (5, 6, and 5) (16-bit) with dither – RGB (8, 8, and 8) (24-bit) with special application.

• Odd/even field identification by a non interlace CVBS input signal

• Fix level for RGB output format during horizontal blanking

• 720 active samples per line on the YUV bus

• One user programmable general purpose switch on an

output pin

• Built-in line-21 text slicer

• A 27 MHz Vertical Blanking Interval (VBI) data bypass

programmable by I

C-bus for INTERCAST applications

• Power-on control

• Two via I2C-bus switchable outputs for the digitized

CVBS or Y/C input signals AD1 (7 to 0) and AD2 (7 to 0)

• Chip enable function (reset for the clock generator and power save mode up from chip version 3)

• Compatible with memory-based features (line-locked clock)

• Boundary scan test circuit complies with the

‘IEEE Std. 1149.1−1990’

(ID-Code = 0 F111 02 B)

• I2C-bus controlled (full read-back ability by an external controller)

• Low power (<0.5 W), low voltage (3.3 V), small package (LQFP64)

• 5 V tolerant digital I/O ports.

2 APPLICATIONS

• Desktop/Notebook (PCMCIA) video

• Multimedia

• Digital television

• Image processing

• Video phone

• Intercast.

1998 May 15 4

Philips Semiconductors Product speciﬁcation

Enhanced Video Input Processor (EVIP) SAA7111A

3 GENERAL DESCRIPTION

The Enhanced Video Input Processor (EVIP) is a combination of a two-channel analog preprocessing circuit including source selection, anti-aliasing filter and ADC, an automatic clamp and gain control, a Clock Generation Circuit (CGC), a digital multi-standard decoder (PAL BGHI, PAL M, PAL N, NTSC M, NTSC-Japan NTSC N and SECAM), a brightness/contrast/saturation control circuit, a colour space matrix (see Fig.1) and a 27 MHz VBI-data bypass.

The pure 3.3 V CMOS circuit SAA7111A, analog front-end and digital video decoder, is a highly integrated circuit for desktop video applications. The decoder is based on the principle of line-locked clock decoding and is able to decode the colour of PAL, SECAM and NTSC signals into CCIR-601 compatible colour component values. The SAA7111A accepts as analog inputs CVBS or S-video (Y/C) from TV or VTR sources. The circuit is I

C-bus controlled. The SAA7111A then supports several

text features as Line 21 data slicing and a high-speed VBI data bypass for Intercast.

4 QUICK REFERENCE DATA

5 ORDERING INFORMATION

SYMBOL PARAMETER MIN. TYP. MAX. UNIT

DDD

digital supply voltage 3.0 3.3 3.6 V

DDA

analog supply voltage 3.1 3.3 3.5 V

amb

operating ambient temperature 0 25 70 °C

A+D

analog and digital power − 0.5 − W

TYPE

NUMBER

PACKAGE

NAME DESCRIPTION VERSION

SAA7111AHZ LQFP64 plastic low proﬁle quad ﬂat package; 64 leads; body 10 × 10 × 1.4 mm SOT314-2 SAA7111AH QFP64 plastic quad ﬂat package; 64 leads (lead length 1.6 mm);

body 14 × 14 × 2.7 mm

SOT393-1

1998 May 15 5

Philips Semiconductors Product speciﬁcation

Enhanced Video Input Processor (EVIP) SAA7111A

6 BLOCK DIAGRAM

Fig.1 Block diagram.

handbook, full pagewidth

SDA

XTAL XTALI

RES

IICSA

TRST

TDI

HSVS

CLOCK

GENERATION

CIRCUIT

POWER-ON

CONTROL

INTERFACE

C-BUS

SYNCHRONIZATION

CIRCUIT

LUMINANCE

CIRCUIT

SAA7111A

CHROMINANCE

CIRCUIT

AND

BRIGHTNESS

CONTRAST

SATURATION

CONTROL

VBI DATA BYPASS

UPSAMPLING FILTER

C-BUS

CONTROL

CLOCKS

ANALOG

PROCESSING

AND

ANALOG-TO-

DIGITAL

CONVERSION

AI11 AI12

AI21 AI22

12 10

8 6

AD2 AD1

ANALOG

CONTROL

CON

BYPASS

30 27 17 29 28 60 15 16 24

RTS0

21 22 20

LLC2 CREF

34 to 39 42 to 51

FEI HREF

VPO (0 : 15)

GPSW

SSS

n.c.

AOUT

RTCO

MGG061

RTS1

LLC

SSA0

DDA0

SSD1-5

DDD1-5

57,41,33,25,18

56,40,32,26,19

SSA1-2

DDA1-2

9,5 11,7

Y/CVBS

C/CVBS

TCK

59 4 58

TMS

TDO

VREF

YUV-to-RGB

CONVERSION

AND

OUTPUT

FORMATTER

PROCESSING

LFCO

TEST

CONTROL

BLOCK

FOR BOUNDARY SCAN TEST

AND SCAN TEST

SCL

1998 May 15 6

Philips Semiconductors Product speciﬁcation

Enhanced Video Input Processor (EVIP) SAA7111A

7 PINNING

SYMBOL

I/O/P DESCRIPTION

(L)QFP64

n.c. 1 − Do not connect. TDO 2 O Test data output for boundary scan test; note 1. TDI 3 I Test data input for boundary scan test; note 1. TMS 4 I Test mode select input for boundary scan test or scan test; note 1. V

SSA2

5 P Ground for analog supply voltage channel 2. AI22 6 I Analog input 22. V

DDA2

7 P Positive supply voltage for analog channel 2 (+3.3 V). AI21 8 I Analog input 21. V

SSA1

9 P Ground for analog supply voltage channel 1. AI12 10 I Analog input 12. V

DDA1

11 P Positive supply voltage for analog channel 1 (+3.3 V). AI11 12 I Analog input 11. V

SSS

13 P Substrate ground connection. AOUT 14 O Analog test output; for testing the analog input channels. V

DDA0

15 P Positive supply voltage for internal Clock Generator Circuit (CGC) (+3.3 V). V

SSA0

16 P Ground for internal CGC. VREF 17 O Vertical reference output signal (I

C-bit COMPO = 0) or inverse composite blanking

signal (I2C-bit COMPO = 1) (enabled via I2C-bus bit OEHV).

DDD5

18 P Digital supply voltage 5 (+3.3 V). V

SSD5

19 P Ground for digital supply voltage 5. LLC 20 O Line-locked system clock output (27 MHz). LLC2 21 O Line-locked clock

⁄2output (13.5 MHz).

CREF 22 O Clock reference output: this is a clock qualiﬁer signal distributed by the internal CGC

for a data rate of LLC2. Using CREF all interfaces on the VPO bus are able to generate a bus timing with identical phase. If CCIR 656 format is selected (OFTS0 = 1 and OFTS1 = 1) an inverse composite blanking signal (pixel qualiﬁer) is provided on this pin.

RES 23 O Reset output (active LOW); sets the device into a deﬁned state. All data outputs are

in high impedance state. The I2C-bus is reset (waiting for start condition).

CE 24 I Chip enable; connection to ground forces a reset, up from version 3 power save

function additionally available.

DDD4

25 P Digital supply voltage input 4 (+3.3 V). V

SSD4

26 P Ground for digital supply voltage input 4. HS 27 O Horizontal sync output signal (programmable); the positions of the positive and

negative slopes are programmable in 8 LLC increments over a complete line (equals 64 µs) via I

C-bus bytes HSB and HSS. Fine position adjustment in 2 LLC

increments can be performed via I2C-bus bits HDEL1 and HDEL0.

RTS1 28 O Two functions output; controlled by I

C-bus bit RTSE1. RTSE1 = 0: PAL line identiﬁer (LOW = PAL line); indicates the inverted and non-inverted R − Y component for PAL signals. RTSE1 = 1: H-PLL locked indicator; a high state indicates that the internal horizontal PLL has locked.

1998 May 15 7

Philips Semiconductors Product speciﬁcation

Enhanced Video Input Processor (EVIP) SAA7111A

RTS0 29 O Two functions output; controlled by I2C-bus bit RTSE0.

RTSE0 = 0: odd/even ﬁeld identiﬁcation (HIGH = odd ﬁeld). RTSE0 = 1: vertical locked indicator; a HIGH state indicates that the internal Vertical Noise Limiter (VNL) has locked.

VS 30 O Vertical sync signal (enabled via I

C-bus bit OEHV); this signal indicates the vertical sync with respect to the YUV output. The HIGH period of this signal is approximately six lines if the VNL function is active. The positive slope contains the phase information for a deﬂection controller.

HREF 31 O Horizontal reference output signal (enabled via I

C-bus bit OEHV); this signal is used to indicate data on the digital YUV bus. The positive slope marks the beginning of a new active line. The HIGH period of HREF is 720 Y samples long. HREF can be used to synchronize data multiplexer/demultiplexer. HREF is also present during the vertical blanking interval.

SSD3

32 P Ground for digital supply voltage input 3.

DDD3

33 P Digital supply voltage 3 (+3.3 V).

VPO (15 to 10)

34 to 39 O Digital VPO-bus (Video Port Out) signal; higher bits of the 16-bit VPO-bus or the

16-bit RGB-bus output signal. The output data rate, the format and multiplexing scheme of the VPO-bus are controlled via I

C-bus bits OFTS0 and OFTS1. If I2C-bus bit VIPB = 1 the six MSBs of the digitized input signal are connected to these outputs, conﬁgured by the I2C-bus ‘MODE’ bits (see Figs 33 to 40): LUMA → VPO15 to VPO8, CHROMA → VPO7 to VPO0.

SSD2

40 P Ground for digital supply voltage input 2.

DDD2

41 P Digital supply voltage 2 (+3.3 V).

VPO (9 to 0)

42 to 51 O Digital VPO-bus output signal; lower bits of the 16-bit YUV-bus or the 16-bit RGB-bus

output signal. The output data rate, the format and multiplexing schema of the VPO-bus are controlled via I

C-bus bits OFTS0 and OFTS1. If I2C-bus bit VIPB = 1 the digitized input signal are connected to these outputs, conﬁgured by the I2C-bus ‘MODE’ bits (see Figs 33 to 40): LUMA → VPO15 to VPO8, CHROMA → VPO7 to VPO0.

FEI 52 I Fast enable input signal (active LOW); this signal is used to control fast switching on

the digital YUV-bus. A HIGH at this input forces the IC to set its Y and UV outputs to the high impedance state.

GPSW 53 O General purpose switch output; the state of this signal is set via I

C-bus control and

the levels are TTL compatible.

XTAL 54 O Second terminal of crystal oscillator; not connected if external clock signal is used. XTALI 55 I Input terminal for 24.576 MHz crystal oscillator or connection of external oscillator

with CMOS compatible square wave clock signal.

SSD1

56 P Ground for digital supply voltage input 1.

DDD1

57 P Digital supply voltage input 1 (+3.3 V). TRST 58 I Test reset input not (active LOW), for boundary scan test; notes 1, 2 and 3. TCK 59 I Test clock for boundary scan test; note 1. RTCO 60 O Real time control output: contains information about actual system clock frequency,

subcarrier frequency and phase and PAL sequence.

SYMBOL

I/O/P DESCRIPTION

(L)QFP64

1998 May 15 8

Philips Semiconductors Product speciﬁcation

Enhanced Video Input Processor (EVIP) SAA7111A

Notes

1. In accordance with the ‘

IEEE1149.1

’ standard the pads TCK, TDI, TMS and TRST are input pads with an internal

pull-up transistor and TDO a 3-state output pad.

2. This pin provides easy initialization of BST circuit. TRST can be used to force the TAP (Test Access Port) controller to the Test-Logic-Reset state (normal operation) at once.

3. For board design without boundary scan implementation (pin compatibility with the SAA7110) connect the TRST pin to ground.

IICSA 61 I I

C-bus slave address select; 0 = 48H for write, 49H for read 1 = 4AH for write, 4BH for read.

SDA 62 I/O Serial data input/output (I

C-bus).

SCL 63 I/O Serial clock input/output (I

C-bus).

n.c. 64 − Not connect.

SYMBOL

I/O/P DESCRIPTION

(L)QFP64

1998 May 15 9

Philips Semiconductors Product speciﬁcation

Enhanced Video Input Processor (EVIP) SAA7111A

Fig.2 Pin configuration (LQFP64/QFP64).

handbook, full pagewidth

SAA7111A

MGG060

1 2 3 4 5 6 7 8

9 10 11 12 13 14 15 16

48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33

TCK

IICSA

SDA

RTCO

n.c.

TDO

TDI

TMS

SSA2

n.c.

AI22

DDA2

VPO15

VPO14

VPO13

VPO12

VPO11

VPO10

VPO9

VPO8

VPO7

VPO6

VPO5

VPO4

VPO3

VPO2

VPO1

VPO0

FEI

GPSW

XTAL

XTALI

SSD1

DDD1

DDD3

DDD2

SSD2

AI21

AI11

AOUT

SSA1

SSA0

SSD5

LLC

LLC2

CREF

RTS1

RTS0

HREF

SSD3

SSD4

DDD4

VREF

SSS

DDA1

DDA0

DDD5

AI12

SCL

TRST

RES

1998 May 15 10

Philips Semiconductors Product speciﬁcation

Enhanced Video Input Processor (EVIP) SAA7111A

8 FUNCTIONAL DESCRIPTION

8.1 Analog input processing

The SAA7111A offers four analog signal inputs, two analog main channels with source switch, clamp circuit, analog amplifier, anti-alias filter and video CMOS ADC (see Fig.5).

8.2 Analog control circuits

The anti-alias filters are adapted to the line-locked clock frequency via a filter control circuit. During the vertical blanking time, gain and clamping control are frozen.

8.2.1 C

LAMPING

The clamp control circuit controls the correct clamping of the analog input signals. The coupling capacitor is also used to store and filter the clamping voltage. An internal digital clamp comparator generates the information with respect to clamp-up or clamp-down. The clamping levels for the two ADC channels are fixed for luminance (60) and chrominance (128). Clamping time in normal use is set with the HCL pulse at the back porch of the video signal.

8.2.2 G

AIN CONTROL

Signal (white) peak control limits the gain at signal overshoots. The flow charts (see Figs 13 and 14) show more details of the AGC. The influence of supply voltage variation within the specified range is automatically eliminated by clamp and automatic gain control.

The gain control circuit receives (via the I2C-bus) the static gain levels for the two analog amplifiers or controls one of these amplifiers automatically via a built-in automatic gain control (AGC) as part of the Analog Input Control (AICO).

Fig.3 Analog line with clamp (HCL) and gain

range (HSY).

handbook, halfpage

HCL

MGL065

HSY

analog line blanking

TV line

255

GAIN CLAMP

The AGC (automatic gain control for luminance) is used to amplify a CVBS or Y signal to the required signal amplitude, matched to the ADCs input voltage range. The AGC active time is the sync bottom of the video signal.

8.3 Chrominance processing

The 8-bit chrominance signal is fed to the multiplication inputs of a quadrature demodulator, where two subcarrier signals from the local oscillator DTO1 are applied (0 and 90° phase relationship to the demodulator axis). The frequency is dependent on the present colour standard. The output signals of the multipliers are low-pass filtered (four programmable characteristics) to achieve the desired bandwidth for the colour difference signals (PAL and NTSC) or the 0 and 90° FM-signals (SECAM).

The colour difference signals are fed to the Brightness/Contrast/Saturation block (BCS), which includes the following five functions:

• AGC (Automatic Gain Control for chrominance PAL and NTSC)

• Chrominance amplitude matching (different gain factors for R − Y and B − Y to achieve CCIR-601 levels Cr and Cb for all standards)

• Chrominance saturation control

• Luminance contrast and brightness

• Limiting YUV to the values 1 (min.) and 254 (max.) to

fulfil CCIR-601 requirements.

Fig.4 Automatic gain range.

handbook, halfpage

analog input level

controlled

ADC input level

maximum

minimum

range tbf0 dB

0 dB

MGG063

+4.5 dB

−7.5 dB

(1 V(p-p) 27/47 Ω)

1998 May 15 11

Philips Semiconductors Product speciﬁcation

Enhanced Video Input Processor (EVIP) SAA7111A

The SECAM-processing contains the following blocks:

• Baseband ‘bell’ filters to reconstruct the amplitude and phase equalized 0 and 90° FM-signals

• Phase demodulator and differentiator (FM-demodulation)

• De-emphasis filter to compensate the pre-emphasised input signal, including frequency offset compensation (DB or DR white carrier values are subtracted from the signal, controlled by the SECAM-switch signal).

The burst processing block provides the feedback loop of the chroma PLL and contains;

• Burst gate accumulator

• Colour identification and killer

• Comparison nominal/actual burst amplitude (PAL/NTSC

standards only)

• Loop filter chrominance gain control (PAL/NTSC standards only)

• Loop filter chrominance PLL (only active for PAL/NTSC standards)

• PAL/SECAM sequence detection, H/2-switch generation

• Increment generation for DTO1 with divider to generate stable subcarrier for non-standard signals.

The chrominance comb filter block eliminates crosstalk between the chrominance channels in accordance with the PAL standard requirements. For NTSC colour standards the chrominance comb filter can be used to eliminate crosstalk from luminance to chrominance (cross-colour) for vertical structures. The comb filter can be switched off if desired. The embedded line delay is also used for SECAM recombination (cross-over switches).

The resulting signals are fed to the variable Y-delay compensation, RGB matrix, dithering circuit and output interface, which contains the VPO output formatter and the output control logic (see Fig.6).

8.4 Luminance processing

The 8-bit luminance signal, a digital CVBS format or a luminance format (S-VHS, HI8), is fed through a switchable prefilter. High frequency components are emphasized to compensate for loss. The following chrominance trap filter (f

= 4.43 or 3.58 MHz centre frequency selectable) eliminates most of the colour carrier signal, therefore, it must be bypassed for S-video (S-VHS and HI8) signals.

The high frequency components of the luminance signal can be peaked (control for sharpness improvement via I

C-bus) in two band-pass filters with selectable transfer characteristic. This signal is then added to the original (unpeaked) signal. A switchable amplifier achieves common DC amplification, because the DC gains are different in both chrominance trap modes. The improved luminance signal is fed to the BCS control located in the chrominance processing block (see Fig.7).

8.5 RGB matrix

Y, Cr and Cb data are converted after interpolation into RGB data in accordance with CCIR-601 recommendations. The realized matrix equations consider the digital quantization:

R = Y + 1.371 Cr G=Y−0.336 Cb − 0.698 Cr B = Y + 1.732 Cb.

After dithering (noise shaping) the RGB data is fed to the output interface within the VPO-bus output formatter.

8.6 VBI-data bypass

For a 27 MHz VBI-data bypass the offset binary CVBS signal is upsampled behind the ADCs. Upsampling of the CVBS signal from 13.5 to 27 MHz is possible, because the ADCs deliver high performance at 13.5 MHz sample clock. Suppressing of the back folded CVBS frequency components after upsampling is achieved by an interpolation filter (see Fig.42).

The TUF block on the digital top level performs the upsampling and interpolation for the bypassed CVBS signal (see Fig.6).

For bypass details see Figs 8 to 10.

8.7 VPO-bus (digital outputs)

The 16-bit VPO-bus transfers digital data from the output interfaces to a feature box or a field memory, a digital colour space converter (SAA7192 DCSC), a video enhancement and digital-to-analog processor (SAA7165 VEDA2) or a colour graphics board (Targa-format) as a graphical user interface.

1998 May 15 12

Philips Semiconductors Product speciﬁcation

Enhanced Video Input Processor (EVIP) SAA7111A

The output data formats are controlled via the I2C-bus bits OFTS0, OFTS1 and RGB888. Timing for the data stream formats, YUV (4 : 1 : 1) (12-bit), YUV (4 : 2 : 2) (16-bit), RGB (5, 6 and 5) (16-bit) and RGB (8, 8 and 8) (24-bit) with an LLC2 data rate, is achieved by marking each second positive rising edge of the clock LLC in conjunction with CREF (clock reference) (except RGB (8, 8 and 8), see special application in Fig.32). The higher output signals VPO15 to VPO8 in the YUV format perform the digital luminance signal. The lower output signals VPO7 to VPO0 in the YUV format are the bits of the multiplexed colour difference signals (B − Y) and (R − Y). The arrangement of the RGB (5, 6 and 5) and RGB (8, 8 and 8) data stream bits on the VPO-bus is given in Table 6.

The data stream format YUV 4:2:2 (the 8 higher output signals VPO15 to VPO8) in LLC data rate fulfils the CCIR-656 standard with its own timing reference code at the start and end of each video data block.

A pixel in the format tables is the time required to transfer a full set of samples. If 16-bit 4 : 2 : 2 format is selected two luminance samples are transmitted in comparison to one (B − Y) and one (R − Y) sample within a pixel. The time frames are controlled by the HREF signal.

Fast enable is achieved by setting input FEI to LOW. The signal is used to control fast switching on the digital VPO-bus. HIGH on this pin forces the VPO outputs to a high-impedance state (see Figs 18 and 19). The I2C-bus bit OEYC has to be set HIGH to use this function.

The digitized PAL, SECAM or NTSC signals AD1 (7 to 0) and AD2 (7 to 0) are connected directly to the VPO-bus via I2C-bus bit VIPB = 1 and MODE = 4, 5, 6 or 7.

AD1 (7 to 0) → VPO (15 to 8) and AD2 (7 to 0) → VPO (7 to 0).

The selection of the analog input channels is controlled via I2C-bus subaddress 02 MODE select.

The upsampled 8-bit offset binary CVBS signal (VBI-data bypass) is multiplexed under control of the I2C-bus to the digital VPO-bus (see Fig.8).

8.8 Reference signals HREF, VREF and CREF

• HREF: The positive slope of the HREF output signal indicates the beginning of a new active video line. The high period is 720 luminance samples long and is also present during the vertical blanking. The description of timing and position from HREF is illustrated in Figs 15, 16, 21 and 23.

• VREF: The VREF output delivers a vertical reference signal or an inverse composite blank signal controlled via the I2C-bus [subaddress 11, inverse composite blank (COMPO)]. Furthermore four different modes of vertical reference signals are selectable via the I2C-bus [subaddress 13, vertical reference output control (VCTR1 and VCTR0)]. The description of VREF timing and position is illustrated in Figs 15, 16, 24 and 25.

• CREF: The CREF output delivers a clock/pixel qualifier signal for external interfaces to synchronize to the VPO-bus data stream.

Four different modes for the clock qualifier signal are selectable via the I2C-bus [subaddress 13, clock reference output control (CCTR1 and CCTR0)]. The description of CREF timing and position is illustrated in Figs 16, 18, 20 and 21.

8.9 Synchronization

The prefiltered luminance signal is fed to the synchronization stage. Its bandwidth is reduced to 1 MHz in a low-pass filter. The sync pulses are sliced and fed to the phase detectors where they are compared with the sub-divided clock frequency. The resulting output signal is applied to the loop filter to accumulate all phase deviations. Internal signals (e. g. HCL and HSY) are generated in accordance with analog front-end requirements. The output signals HS, VS, and PLIN are locked to the timing reference, guaranteed between the input signal and the HREF signal, as further improvements to the circuit may change the total processing delay. It is therefore not recommended to use them for applications which require absolute timing accuracy on the input signals. The loop filter signal drives an oscillator to generate the line frequency control signal LFCO (see Fig.7).

8.10 Clock generation circuit

The internal CGC generates all clock signals required for the video input processor. The internal signal LFCO is a digital-to-analog converted signal provided by the horizontal PLL. It is the multiple of the line frequency

Internally the LFCO signal is multiplied by a factor of 2 or 4 in the PLL circuit (including phase detector, loop filtering, VCO and frequency divider) to obtain the LLC and LLC2 output clock signals. The rectangular output clocks have a 50% duty factor (see Fig.26).

6.75MHz

429 432

--------- -

×=

1998 May 15 13

Philips Semiconductors Product speciﬁcation

Enhanced Video Input Processor (EVIP) SAA7111A

8.11 Power-on reset and CE input

A missing clock, insufficient digital or analog V

DDA0

supply voltages (below 2.7 V) will initiate the reset sequence; all outputs are forced to 3-state. The indicator output RES is LOW for approximately 128LLC after the internal reset and can be applied to reset other circuits of the digital TV system.

It is possible to force a reset by pulling the chip enable (CE) to ground. After the rising edge of CE and sufficient power supply voltage, the outputs LLC, LLC2, CREF, RTCO, RTS0, RTS1, GPSW and SDA return from 3-state to active, while HREF, VREF, HS and VS remain in 3-state and have to be activated via I

C-bus programming

(see Table 5).

8.12 RTCO output

The real time control and status output signal contains serial information about the actual system clock (increment of the HPLL), subcarrier frequency [increment and phase (via reset) of the FSC-PLL] and PAL sequence bit. The signal can be used for various applications in external circuits, e.g. in a digital encoder to achieve clean encoding (see Fig.20).

8.13 The Line-21 text slicer

The text slicer block detects and acquires Line-21 Closed Captioning data from a 525-line CVBS signal. Extended data services on Line-21 Field 2 are also supported. If valid data is detected the two data bytes are stored in two I2C-bus registers. A parity check is also performed and the result is stored in the MSB of the corresponding byte. A third I2C-bus register is provided for data valid and data ready flags. The two bits F1VAL and F2VAL indicate that the input signal carries valid Closed Captioning data in the corresponding fields. The data ready bits F1RDY and F2RDY have to be evaluated if asynchronous I2C-bus reading is used.

8.13.1 S

UGGESTIONS FOR I

C-BUS INTERFACE OF THE

DISPLAY SOFTWARE READING LINE

-21 DATA

There are two methods by which the software can acquire the data:

1. Synchronous reading once per frame (or once per field); It can use either the rising edge (Line-21 Field 1) or both edges (Line-21 Field 1 or 2) of the ODD signal (pin RTSO) to initiate an I2C-bus read transfer of the three registers 1A, 1B and 1C.

2. Asynchronous reading; It can poll either the F1RDY bit (Line-21 Field 1) or both F1RDY/F2RDY bits (Line-21 Field 1 or 2). After valid data has been read the corresponding F*RDY bit is set to LOW until new data has arrived. The polling frequency has to be slightly higher than the frame or field frequency, respectively.

1998 May 15 14

Philips Semiconductors Product speciﬁcation

Enhanced Video Input Processor (EVIP) SAA7111A

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AI22 AI21

FUSE (1 : 0)

AI12 AI11

FUSE (1 : 0)

AOSL (1 : 0)

HOLDG

ANALOG CONTROL

GAI10-GAI18

SSS

n.c.

VBSL 8 8

MGC655

CHRLUM

VERTICAL

BLANKING

CONTROL

SOURCE

SWITCH

CLAMP

CIRCUIT

ANALOG

AMPLIFIER

ANTI-ALIAS

FILTER

BYPASS SWITCH

SOURCE

SWITCH

CLAMP

CIRCUIT

ANALOG

AMPLIFIER

ANTI-ALIAS

FILTER

BYPASS SWITCH

ADC2

ADC1

TEST

AND

SELECTOR

CLAMP

CONTROL

GAIN

CONTROL

CROSS MULTIPLEXER

ANTI-ALIAS

CONTROL

DDA1

SSA2

AOUT

MODE

CONTROL

MODE 0 MODE 1 MODE 2

GAI20-GAI28

GUDL0-GUDL2

GAFIX WPOFF

HSY

VBLNK SVREF

HCL

AD1BYPAD2BYP

BUFFER

DAC9

HLNRS UPTCV

DDA2

9 5

6 8

11 7

10 12

SSA1

GLIMB GLIMT WIPA SLTCA

Fig.5 Analog input processing.

1998 May 15 15

Philips Semiconductors Product speciﬁcation

Enhanced Video Input Processor (EVIP) SAA7111A

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Fig.6 Chrominance circuit.

ewidth

CHRLUM

CODE

AD1BYPAD2BYP

BRIG

CONT

SATN

HUEC

DCCF

fH/2 switch signal

MGG062

DDD1-5

SSD1-5

57,41,33, 25,18

56,40,32,26,19

34 to 39

42 to 51

QUADRATURE

DEMODULATOR

COMB

FILTERS

SECAM

RECOMBINATION

FORMATTER

OUTPUT

AND

INTERFACE

ACCUMULATOR

BURST GATE

LOW-PASS

LOOP FILTER

SUBCARRIER

INCREMENT

GENERATION

AND

DIVIDER

SUBCARRIER GENERATION

FCTCCSTD 1

RGB MATRIX

interpolation

dithering

SECAM

PROCESSING

DIT CBR

CHBW0 CHBW1

CSTD 0

INCS

RES

TCK

TDI

59 3

POWER-ON

CONTROL

TEST

CONTROL

BLOCK

TDO

TRST

TMS

LUM

RTCO

n.c.

CLOCKS

sequential UV signals

RGB

FEI

HREF

VPO (9 : 0)

VPO (15 : 10)

VBI DATA BYPASS

TUF

PHASE

DEMODULATOR

AMPLITUDE

DETECTOR

OFTS0 OFTS1 RGB888 OEYC OEHV FECO VRLN VSTA (8 : 0) VSTO (8 : 0)

GPSW RTSE1 RTSE0 VIPB VLOF COLO COMPO

LEVEL

ADJUSTMENT,

BRIGHTNESS,

CONTRAST,

AND

SATURATION

CONTROL

GAIN

CONTROL

AND Y-DELAY

COMPENSATION

1998 May 15 16

Philips Semiconductors Product speciﬁcation

Enhanced Video Input Processor (EVIP) SAA7111A

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CREF LLC

XTALI XTAL

VREF

RTS0

SDASCLIICSA

GPSW

I C BUS CONTROL

CLOCKS

SYNCHRONIZATION CIRCUIT

PREF

BYPS

APER0 APER1 VBLB

AUFD

HSB HSS

FSEL

VTRC

STTC

FIDT

VNOI0 VNOI1 VTRC

VTRC

RTS1

MGC654

LLC2

HLCK

DDA0

SSA0

61 63 62 30 29 17 27 28

16 24

22 20 21

DAC6

AND

WEIGHTING

ADDING

BAND-PASS

VARIABLE

FILTER

CHROMINANCE

TRAP

PREFILTER

AMPLIFIER

MATCHING

CLOCK

LINE-LOCKED GENERATOR

LOOP FILTER

DETECTOR

PHASE

COARSE

DETECTOR

PHASE

FINE

SYNC SLICER

SYNC

PREFILTER

LINE 21

TEXT

SLICER

CLOCK

CRYSTAL

GENERATOR

TIME

DISCRETE

OSCILLATOR 2

INTERFACE

I C-BUS

PROCESSOR

VERTICAL

COUNTER

GENERATION

CLOCK

CIRCUIT

LUMINANCE CIRCUIT

BPSS0 BPSS1 PREF

LUM

VBLB

CLOCK CIRCUIT

INCS

STAGE

HPLL VTRC

EXFIL

BYTE1 BYTE2

STATUS

Fig.7 Luminance and sync processing.

1998 May 15 17

Philips Semiconductors Product speciﬁcation

Enhanced Video Input Processor (EVIP) SAA7111A

Fig.8 Multiplexing of the CVBS signal to the VPO-bus.

HREFINT = internal horizontal reference. TBP = upsampled CVBS input data (27 MHz). AD1BYP/AD2BYP = digitized CVBS input data and Y/C input data (13.5 MHz). VBP0 = programmable vertical reference signal. VBP4 = delayed programmable vertical reference signal (4LLC clocks delay).

handbook, full pagewidth

MGG064

CLOCK 0

HREFINT

V_GATE

(programmable)

4 × REG

CLOCK 0

REG

BCHI1 BCHI0 SWHI

0 0 1 1

0 1 0 1

0 VBP0 VBP4

VBP0

AD1BYP

VBP4

MUX

CVBS

MUX

BYP

BCLO1 BCLO0 SWLO

0 0 1 1

0 1 0 1

BCLO1 to 0

C-bus

BCHI1 to 0

C-bus

VIPB I

C-bus

TBP7 to 0

(CVBS)

UV or YUV

Y or YUV

0 VBP0 VBP4

VBP0

VBP4

VBP0

AD2BYP

VBP4

MUX

CVBS

VPO7 to 0

SWHI

SWLO

VPO15 to 8

MUX

BYP

(LUMA see Fig. 37)

(CHROMA see Fig. 37)

1998 May 15 18

Philips Semiconductors Product speciﬁcation

Enhanced Video Input Processor (EVIP) SAA7111A

Fig.9 VREF output signal generation.

VREF_CCIR 656 = vertical reference signal referring to the field interval definitions of CCIR656. HREFINT = internal horizontal reference signal. VREFINT = internal vertical reference signal. VBP0 = programmable vertical reference signal. VBP4 = delayed programmable vertical reference signal (4LLC clocks delay).

handbook, full pagewidth

MGG065

V C T R 1

0 0 1 1

0 1 0 1

V C T R 0

VREFINT

VREF

CLOCK 0

COMPO

VCTR1 to 0

VREFOUT

VREF CCIR 656 VBP0 VBP4

VBP0 VBP4

VREFINT

HREFINT

VREF CCIR 656

REG

HREF

CLK0

REG

CLOCK 0

REG

MUX

CLOCK 0

REG

Fig.10 CREF output signal generation.

CREFINT = internal clock qualifier signal.

handbook, full pagewidth

MGG066

C C T R 1

0 0 1 1

0 1 0 1

C C T R 0

CREFINT

selected

VREF

CCTR1 to 0

CREF

CLOCK 0

CREFOUT

0 if VREF = 0 1 if VREF = 0 1 (always HIGH)

REG

1998 May 15 19

Philips Semiconductors Product speciﬁcation

Enhanced Video Input Processor (EVIP) SAA7111A

9 BOUNDARY-SCAN TEST

The SAA7111A has built in logic and 5 dedicated pins to support boundary-scan testing which allows board testing without special hardware (nails). The SAA7111A follows the

‘IEEE Std. 1149.1 - Standard Test Access Port and

Boundary-Scan Architecture

’ set by the Joint Test Action

Group (JTAG) chaired by Philips. The 5 special pins are Test Mode Select (TMS), Test

Clock (TCK), Test Reset (TRST), Test Data Input (TDI) and Test Data Output (TDO).

The BST functions BYPASS, EXTEST, INTEST, SAMPLE, CLAMP and IDCODE are all supported (see Table 1). Details about the JTAG BST-TEST can be found in the specification “

EEE Std. 1149.1”

. A file containing the detailed Boundary-Scan Description Language (BSDL) description of the SAA7111A is available on request.

9.1 Initialization of boundary-scan circuit

The Test Access Port (TAP) controller of an IC should be in the reset state (TEST_LOGIC_RESET) when the IC is in functional mode. This reset state also forces the instruction register into a functional instruction such as IDCODE or BYPASS.

To solve the power-up reset, the standard specifies that the TAP controller will be forced asynchronously to the TEST_LOGIC_RESET state by setting the TRST pin LOW.

9.2 Device identiﬁcation codes

A Device Identification Register (DIR) is specified in

‘IEEE Std. 1149.1-1990 - IEEE Standard Test Access Port and Boundary-Scan Architecture

’ (IEEE Std. 1149.1b-1994). It is a 32-bit register which contains fields for the specification of the IC manufacturer, the IC part number and the IC version number. Its biggest advantage is the possibility to check for the correct ICs mounted after production and determination of the version number of ICs during field service.

When the IDCODE instruction is loaded into the BST instruction register, the identification register will be connected between TDI and TDO of the IC. The identification register will load a component specific code during the CAPTURE_DATA_REGISTER state of the TAP controller and this code can subsequently be shifted out. At board level this code can be used to verify component manufacturer, type and version number. The device identification register contains 32-bits, numbered 31 to 0, where bit 31 is the Most Significant Bit (MSB) (nearest to TDI) and bit 0 is the Least Significant Bit (LSB) (nearest to TDO); see Fig.11.

Table 1 BST instructions supported by the SAA7111A

INSTRUCTION DESCRIPTION

BYPASS This mandatory instruction provides a minimum length serial path (1 bit) between TDI and TDO

when no test operation of the component is required.

EXTEST This mandatory instruction allows testing of off-chip circuitry and board level interconnections.

SAMPLE This mandatory instruction can be used to take a sample of the inputs during normal operation of

the component. It can also be used to preload data values into the latched outputs of the boundary-scan register.

CLAMP This optional instruction is useful for testing when not all ICs have BST. This instruction addresses

the bypass register while the boundary-scan register is in external test mode.

IDCODE This optional instruction will provide information on the components manufacturer, part number and

version number.

INTEST This optional instruction allows testing of the internal logic (no support for customers available).

USER1 This private instruction allows testing by the manufacturer (no support for customers available).

1998 May 15 20

Philips Semiconductors Product speciﬁcation

Enhanced Video Input Processor (EVIP) SAA7111A

Fig.11 32 bits of identification code.

handbook, full pagewidth

MGL111

0000001010111110001000100010010

4-bit

version

code

16-bit part number 11-bit manufacturer

indentification

TDI TDO

MSB LSB

28 27 12 11 1 0

1998 May 15 21

Philips Semiconductors Product speciﬁcation

Enhanced Video Input Processor (EVIP) SAA7111A

10 GAIN CHARTS

Fig.12 Amplifier curve.

handbook, halfpage

7.5

5.5

3.5

1.5

−0.5

−4.5

−2.5

256 512

gain value (i)

MGC648

bit [8] = 1

factor

= 20 x log10 gain =

(

512

768 − i

i > 256

bit [8] = 0

factor

= 20 x log10 gain =

(

512

257 + i

(

i < 256

(

Fig.13 Clamp and gain flow.

WIPE = white peak level (254); SBOT = sync bottom level (1); CLL = clamp level [60 Y (128 C)]; HSY = horizontal sync pulse; HCL = horizontal clamp pulse.

handbook, full pagewidth

+ CLAMP − CLAMP

NO CLAMP

10 10

01 10

MGC647

fast − GAIN

slow + GAIN

+ GAIN − GAIN

HCL HSY

ADC

SBOT

WIPE

CLL

ANALOG INPUT

GAIN -><- CLAMP

VBLK

NO BLANKING ACTIVE

1998 May 15 22

Philips Semiconductors Product speciﬁcation

Enhanced Video Input Processor (EVIP) SAA7111A

Fig.14 Gain flow chart.

X = system variable; Y = IAGV − FGVI > GUDL; VBLK = vertical blanking pulse; HSY = horizontal sync pulse; AGV = actual gain value; FGV = frozen gain value.

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ANALOG INPUT

AMPLIFIER

ANTI-ALIAS FILTER

ADC

LUMA/CHROMA DECODER

HSY

>254

>248

X = 0

X = 1

−

1/LLC2

+1/LLC2 −1/LLC2

+/− 0

+1/F

+1/L

GAIN ACCUMULATOR (18 BITS)

ACTUAL GAIN VALUE 9-BIT (AGV) [−6/+6 dB]

STOP

HSY

UPDATE

FGV

MGC652

AGV

GAIN VALUE 9-BIT

VBLK

NO ACTION

DAC

gain

HOLDG

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