Philips SAA7111AHZ, SAA7111AH Datasheet

INTEGRATED CIRCUITS

DATA SH EET

SAA7111A

Enhanced Video Input Processor (EVIP)

Preliminary speciﬁcation Supersedes data of 1996 Nov 07 File under Integrated Circuits, IC22

1997 May 26

Philips Semiconductors Preliminary speciﬁcation

Enhanced Video Input Processor (EVIP) SAA7111A

CONTENTS

1 FEATURES 2 APPLICATIONS 3 GENERAL DESCRIPTION 4 QUICK REFERENCE DATA 5 ORDERING INFORMATION 6 BLOCK DIAGRAM 7 PINNING 8 FUNCTIONAL DESCRIPTION

8.1 Analog input processing

8.2 Analog control circuits

8.2.1 Clamping

8.2.2 Gain control

8.3 Chrominance processing

8.4 Luminance processing

8.5 RGB matrix

8.6 VBI-data bypass

8.7 VPO-bus (digital outputs)

8.8 Reference signals HREF, VREF and CREF

8.9 Synchronization

8.10 Clock generation circuit

8.11 Power-on reset and CE input

8.12 RTCO output

8.13 The Line-21 text slicer

8.13.1 Suggestions for I2C-bus interface of the display software reading line-21 data

9 BOUNDARY-SCAN TEST

9.1 Initialization of boundary-scan circuit

9.2 Device identification codes

10 GAIN CHARTS 11 LIMITING VALUES 12 CHARACTERISTICS 13 TIMING DIAGRAMS 14 CLOCK SYSTEM

14.1 Clock generation circuit

14.2 Power-on control

15 OUTPUT FORMATS 16 APPLICATION INFORMATION 17 I2C-BUS DESCRIPTION

17.1 I2C-bus format

17.2 I2C-bus detail

17.2.1 Subaddress 00

17.2.2 Subaddress 02

17.2.3 Subaddress 03

17.2.4 Subaddress 04

17.2.5 Subaddress 05

17.2.6 Subaddress 06

17.2.7 Subaddress 07

17.2.8 Subaddress 08

17.2.9 Subaddress 09

17.2.10 Subaddress 0A

17.2.11 Subaddress 0B

17.2.12 Subaddress 0C

17.2.13 Subaddress 0D

17.2.14 Subaddress 0E

17.2.15 Subaddress 10

17.2.16 Subaddress 11

17.2.17 Subaddress 12

17.2.18 Subaddress 13

17.2.19 Subaddress 15

17.2.20 Subaddress 16

17.2.21 Subaddress 17

17.2.22 Subaddress 1A (read-only register)

17.2.23 Subaddress 1B (read-only register)

17.2.24 Subaddress 1C (read-only register)

17.2.25 Subaddress 1F (read-only register) 18 FILTER CURVES

18.1 Anti-alias filter curve

18.2 TUF-block filter curve

18.3 Luminance filter curves

18.4 Chrominance filter curves 19 I2C-BUS START SET-UP 20 PACKAGE OUTLINES 21 SOLDERING

21.1 Introduction

21.2 Reflow soldering

21.3 Wave soldering

21.3.1 PLCC

21.3.2 QFP

21.3.3 Method (PLCC and QFP)

21.4 Repairing soldered joints 22 DEFINITIONS 23 LIFE SUPPORT APPLICATIONS 24 PURCHASE OF PHILIPS I2C COMPONENTS

1997 May 26 2

Philips Semiconductors Preliminary speciﬁcation

Enhanced Video Input Processor (EVIP) SAA7111A

1 FEATURES

• Four analog inputs, internal analog source selectors,

e.g. 4 × CVBS or 2 × Y/C or (1 × Y/C and 2 × CVBS)

• Two analog preprocessing channels

• Fully programmable static gain for the main channels or

automatic gain control for the selected CVBS or Y/C channel

• Switchable white peak control

• Two built-in analog anti-aliasing filters

• Two 8-bit video CMOS analog-to-digital converters

• On-chip clock generator

• Line-locked system clock frequencies

• Digital PLL for horizontal-sync processing and clock

generation

• Requires only one crystal (24.576 MHz) for all standards

• Horizontal and vertical sync detection

• Automatic detection of 50 and 60 Hz field frequency,

and automatic switching between PAL and NTSC standards

• Luminance and chrominance signal processing for

PAL BGHI, PAL N, PAL M, NTSC M, NTSC N, NTSC 4.43, NTSC-Japan and SECAM

• User programmable luminance peaking or aperture

correction

• Cross-colour reduction for NTSC by chrominance comb

filtering

• PAL delay line for correcting PAL phase errors

• Real time status information output (RTCO)

• Brightness Contrast Saturation (BCS) control on-chip

• The YUV (CCIR-601) bus supports a data rate of:

– 864 × f – 858 × fH= 13.5 MHz for 525 line sources

• Data output streams for 16, 12 or 8-bit width with the

following formats: – YUV4:1:1 (12-bit) – YUV4:2:2 (16-bit) – YUV4:2:2 (CCIR-656) (8-bit) – RGB (5, 6, 5) (16-bit) with dither – RGB (8, 8, 8) (24-bit) with special application

• Odd/even field identification by a non interlace CVBS

input signal

• Fix level for RGB output format during horizontal

blanking

= 13.5 MHz for 625 line sources

• 720 active samples per line on the YUV bus

• One user programmable general purpose switch on an

output pin

• Built-in line-21 text slicer

• A 27 MHz Vertical Blanking Interval (VBI) data bypass

programmable by I

• Power-on control

• Two via I2C-bus switchable outputs for the digitized

CVBS or Y/C input signals AD1 (7 to 0) and AD2 (7 to 0)

• Chip enable function (reset for the clock generator)

• Compatible with memory-based features (line-locked

clock)

• Boundary scan test circuit complies with the

IEEE Std. 1149.1−1990

• I2C-bus controlled (full read-back ability by an external controller)

• Low power (<0.5 W), low voltage (3.3 V), small package (LQFP64)

• 5 V tolerant digital I/O ports.

2 APPLICATIONS

• Desktop/Notebook (PCMCIA) video

• Multimedia

• Digital television

• Image processing

• Video phone

• Intercast.

C-bus for INTERCAST applications

(ID-Code = 0 F111 02 B)

1997 May 26 3

Philips Semiconductors Preliminary speciﬁcation

Enhanced Video Input Processor (EVIP) SAA7111A

3 GENERAL DESCRIPTION

The Enhanced Video Input Processor (EVIP) is a combination of a two-channel analog preprocessing circuit including source selection, anti-aliasing filter and ADC, an automatic clamp and gain control, a Clock Generation Circuit (CGC), a digital multi-standard decoder (PAL BGHI, PAL M, PAL N, NTSC M, NTSC-Japan NTSC N and SECAM), a brightness/contrast/saturation control circuit, a colour space matrix (see Fig.1) and a 27 MHz VBI-data bypass.

The pure 3.3 V CMOS circuit SAA7111A, analog front-end and digital video decoder, is a highly integrated circuit for desktop video applications. The decoder is based on the principle of line-locked clock decoding and is able to decode the colour of PAL, SECAM and NTSC signals into CCIR-601 compatible colour component values. The SAA7111A accepts as analog inputs CVBS or S-video (Y/C) from TV or VTR sources. The circuit is I

C-bus controlled. The SAA7111A then supports several text features as Line 21 data slicing and a high-speed VBI data bypass for Intercast.

4 QUICK REFERENCE DATA

SYMBOL PARAMETER MIN. TYP. MAX. UNIT

V V T P

DDD DDA amb A+D

digital supply voltage 3.0 3.3 3.6 V analog supply voltage 3.1 3.3 3.5 V operating ambient temperature 0 25 70 °C analog and digital power − 0.5 − W

5 ORDERING INFORMATION

TYPE

NUMBER

NAME DESCRIPTION VERSION

PACKAGE

SAA7111AHZ LQFP64 plastic low proﬁle quad ﬂat package; 64 leads; body 10 × 10 × 1.4 mm SOT314-2 SAA7111AH QFP64 plastic quad ﬂat package; 64 leads (lead length 1.6 mm); body

SOT393-1

14 × 14 × 2.7 mm

SAA7111AWP PLCC68 plastic leaded chip carrier; 68 leads; body 24 × 24 × 4.5 mm SOT188-2

1997 May 26 4

Philips Semiconductors Preliminary speciﬁcation

Enhanced Video Input Processor (EVIP) SAA7111A

6 BLOCK DIAGRAM

handbook, full pagewidth

VBI DATA BYPASS

UPSAMPLING FILTER

BYPASS

AI11 AI12

AI21 AI22

n.c.

SSS

n.c.

TDI

TCK

TMS

TDO

23 (14)

21 (12) 19 (10)

17 (8) 15 (6)

7,8,9 (64)

22 (13)

36, 37

1 (10)

18,14 (9,5) 20,16 (11,7)

12 (3) 2 (59) 13 (4) 1 (58)

11 (2)

ANALOG

PROCESSING

AND

ANALOG-TO-

DIGITAL

CONVERSION

AD2 AD1

ANALOG

PROCESSING

CONTROL

TEST

CONTROL

BLOCK

FOR BOUNDARY SCAN TEST

AND SCAN TEST

CON

CHROMINANCE

C/CVBS

Y/CVBS

BRIGHTNESS SATURATION

SYNCHRONIZATION

CIRCUIT

AND

CONTRAST

CONTROL

LUMINANCE

CIRCUIT

SAA7111A

LFCO

45 to 50

YUV-to-RGB

CONVERSION

AND

OUTPUT

FORMATTER

C-BUS

CONTROL

C-BUS

INTERFACE

CLOCKS

CLOCK

GENERATION

CIRCUIT

POWER-ON

CONTROL

53 to 62

(34 to 39) (42 to 51)

(52) 63 (31) 42

(53) 64

(61) 4 (62) 5 (63) 6

(54) 65 (55) 66

(21) 30 (22) 31 (20) 29

(23) 32

VPO (0 : 15)

FEI HREF

GPSW

IICSA SDA

SCL

XTAL XTALI

LLC2 CREF LLC RES

AOUT

SSA1-2

DDA1-2

TRST

(57,41,33,25,18) 68,52,44,34,27

DDD1-5

The pin numbers given in parenthesis refer to the 64-pin package.

(56,40,32,26,19) 67,51,43,35,28

SSD1-5

(30)41(27)38(17)26(29)40(28)39(60)

VREF

RTS0

HSVS

Fig.1 Block diagram.

1997 May 26 5

RTS1

RTCO

(15)24(16)25(24)

DDA0

SSA0

MGG061

Philips Semiconductors Preliminary speciﬁcation

Enhanced Video Input Processor (EVIP) SAA7111A

7 PINNING

SYMBOL

I/O/P DESCRIPTION

(L)QFP64 PLCC68

n.c. 1 10 − do not connect TDO 2 11 O test data output for boundary scan test; note 3 TDI 3 12 I test data input for boundary scan test; note 3 TMS 4 13 I test mode select input for boundary scan test or scan test; note 3

PINS

SSA2

5 14 P ground for analog supply voltage channel 2 AI22 6 15 I analog input 22 V

DDA2

7 16 P positive supply voltage for analog channel 2 (+3.3 V) AI21 8 17 I analog input 21 V

SSA1

9 18 P ground for analog supply voltage channel 1 AI12 10 19 I analog input 12 V

DDA1

11 20 P positive supply voltage for analog channel 1 (+3.3 V) AI11 12 21 I analog input 11 V

SSS

13 22 P substrate ground connection AOUT 14 23 O analog test output; for testing the analog input channels V

DDA0

15 24 P positive supply voltage for internal Clock Generator Circuit (CGC)

(+3.3 V)

SSA0

VREF 17 26 O vertical reference output signal (I

16 25 P ground for internal CGC

C-bit COMPO = 0) or inverse composite blanking signal (I2C-bit COMPO = 1) (enabled via I2C-bus bit OEHV)

V V

DDD5 SSD5

18 27 P digital supply voltage 5 (+3.3 V)

19 28 P ground for digital supply voltage 5 LLC 20 29 O line-locked system clock output (27 MHz) LLC2 21 30 O line-locked clock

⁄2output (13.5 MHz)

CREF 22 31 O clock reference output: this is a clock qualiﬁer signal distributed by the

internal CGC for a data rate of LLC2. Using CREF all interfaces on the VPO bus are able to generate a bus timing with identical phase. If CCIR 656 format is selected (OFTS0 = 1 and OFTS1 = 1) an inverse composite blanking signal (pixel qualiﬁer) is provided on this pin.

RES 23 32 O reset output (active LOW); sets the device into a deﬁned state. All data

outputs are in high impedance state. The I2C-bus is reset (waiting for

start condition). CE 24 33 I chip enable; connection to ground forces a reset V V

DDD4 SSD4

25 34 P digital supply voltage input 4 (+3.3 V) 26 35 P ground for digital supply voltage input 4

HS 27 38 O horizontal sync output signal (programmable); the positions of the

positive and negative slopes are programmable in 8 LLC increments over

a complete line (= 64 µs) via I

C-bus bytes HSB and HSS. Fine position adjustment in 2 LLC increments can be performed via I2C-bus bits HDEL1 and HDEL0.

1997 May 26 6

Philips Semiconductors Preliminary speciﬁcation

Enhanced Video Input Processor (EVIP) SAA7111A

SYMBOL

I/O/P DESCRIPTION

(L)QFP64 PLCC68

RTS1 28 39 O two functions output; controlled by I2C-bus bit RTSE1.

RTSE1 = 0: PAL line identiﬁer (LOW = PAL line); indicates the inverted and non-inverted R−Y component for PAL signals. RTSE1 = 1: H-PLL locked indicator; a high state indicates that the internal horizontal PLL has locked.

PINS

RTS0 29 40 O two functions output; controlled by I

C-bus bit RTSE0. RTSE0 = 0: odd/even ﬁeld identiﬁcation (HIGH = odd ﬁeld). RTSE0 = 1: vertical locked indicator; a HIGH state indicates that the internal Vertical Noise Limiter (VNL) has locked.

VS 30 41 O vertical sync signal (enabled via I

C-bus bit OEHV); this signal indicates the vertical sync with respect to the YUV output. The HIGH period of this signal is approximately six lines if the VNL function is active. The positive slope contains the phase information for a deﬂection controller.

HREF 31 42 O horizontal reference output signal (enabled via I

C-bus bit OEHV); this signal is used to indicate data on the digital YUV bus. The positive slope marks the beginning of a new active line. The HIGH period of HREF is 720 Y samples long. HREF can be used to synchronize data multiplexer/demultiplexer. HREF is also present during the vertical blanking interval.

SSD3

DDD3

VPO (15 to 10)

32 43 P ground for digital supply voltage input 3 33 44 P digital supply voltage 3 (+3.3 V)

34 to 39 45 to 50 O digital VPO-bus (Video Port Out) signal; higher bits of the 16-bit VPO-bus

or the 16-bit RGB-bus output signal. The output data rate, the format and multiplexing scheme of the VPO-bus are controlled via I

C-bus bits OFTS0 and OFTS1. If I2C-bus bit VIPB = 1 the six MSBs of the digitized input signal are connected to these outputs, conﬁgured by the I2C-bus ‘MODE’ bits (see Figs 34 to 41): LUMA -> VPO15 to VPO8, CHROMA -> VPO7 to VPO0.

SSD2

DDD2

VPO (9 to 0)

40 51 P ground for digital supply voltage input 2 41 52 P digital supply voltage 2 (+3.3 V)

42 to 51 53 to 62 O digital VPO-bus output signal; lower bits of the 16-bit YUV-bus or the

16-bit RGB-bus output signal. The output data rate, the format and multiplexing schema of the VPO-bus are controlled via I

C-bus bits OFTS0 and OFTS1. If I2C-bus bit VIPB = 1 the digitized input signal are connected to these outputs, conﬁgured by the I2C-bus ‘MODE’ bits (see Figs 34 to 41): LUMA -> VPO15 to VPO8, CHROMA -> VPO7 to VPO0.

FEI 52 63 I fast enable input signal (active LOW); this signal is used to control fast

switching on the digital YUV-bus. A HIGH at this input forces the IC to set its Y and UV outputs to the high impedance state.

GPSW 53 64 O general purpose switch output; the state of this signal is set via I

C-bus

control and the levels are TTL compatible

XT AL 54 65 O second terminal of crystal oscillator; not connected if external clock signal

is used

XTALI 55 66 I input terminal for 24.576MHz crystal oscillator or connection of external

oscillator with CMOS compatible square wave clock signal

SSD1

56 67 P ground for digital supply voltage input 1

1997 May 26 7

Philips Semiconductors Preliminary speciﬁcation

Enhanced Video Input Processor (EVIP) SAA7111A

SYMBOL

I/O/P DESCRIPTION

(L)QFP64 PLCC68

PINS

DDD1

57 68 P digital supply voltage input 1 (+3.3 V) TRST 58 1 I test reset input not (active LOW), for boundary scan test; notes 1, 2 and 3 TCK 59 2 I test clock for boundary scan test; note 3 RTCO 60 3 O real time control output: contains information about actual system clock

frequency, subcarrier frequency and phase and PAL sequence

IICSA 61 4 I I

C-bus slave address select; 0 = 48H for write, 49H for read 1 = 4AH for write, 4BH for read

SDA 62 5 I/O serial data input/output (I SCL 63 6 I/O serial clock input/output (I n.c. 64 7, 8, 9,

− do not connect

C-bus)

36 and 37

Notes

1. For board design without boundary scan implementation (pin compatibility with the SAA7110) connect theTRST pin to ground.

2. This pin provides easy initialization of BST circuit. TRST can be used to force the TAP (Test Access Port) controller to the Test-Logic-Reset state (normal operation) at once.

3. In accordance with the

IEEE1149.1

standard the pads TCK, TDI, TMS and TRST are input pads with an internal

pull-up transistor and TDO a 3-state output pad.

1997 May 26 8

Philips Semiconductors Preliminary speciﬁcation

Enhanced Video Input Processor (EVIP) SAA7111A

handbook, full pagewidth

DDD1VSSD1

TDO

TMS

SSA2

DDA2

SSA1

DDA1

AOUT

DDA0

SSA0 VREF

n.c.

TDI

AI22

AI21

AI12

AI11

SSS

n.c. 9

10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26

SCL

n.c.

SDA 5

IICSA 4

SAA7111A

TRST

TCK

RTCO

66 XTALI

XTAL 65

GPSW 64

FEI 63

VPO0 62

VPO1 61

60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44

VPO3 VPO3 VPO4 VPO5 VPO6 VPO7 VPO8 VPO9

DDD2

SSD2

VPO10 VPO11 VPO12 VPO13 VPO14 VPO15

DDD3

29LLC

DDD5

SSD5

LLC2

CREF

RES

DDD4

Fig.2 Pin configuration (PLCC68).

1997 May 26 9

SSD4

36 n.c.

37 n.c.

38 HS

RTS1

RTS0

41 VS

HREF

SSD3

MGG059

Philips Semiconductors Preliminary speciﬁcation

Enhanced Video Input Processor (EVIP) SAA7111A

handbook, full pagewidth

SSD1

DDD1

TRST

SAA7111A

24 CE

RES

DDD4

XTALI 55

SSD4

XTAL 54

27 HS

GPSW 53

RTS1

FEI 52

RTS0

VPO0 51

30 VS

VPO1

HREF

VPO2 49

SSD3

48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33

VPO3 VPO4 VPO5

VPO6 VPO7 VPO8 VPO9 V

DDD2

SSD2

VPO10 VPO11 VPO12 VPO13 VPO14 VPO15

DDD3

MGG060

SSA2

DDA2

SSA1

DDA1

AOUT

DDA0

SSA0

n.c.

TDO

TDI

TMS

AI22

AI21

AI12

AI11

SSS

RTCO 60

LLC2

TCK 59

CREF

IICSA

SDA

SCL

n.c.

61 1 2 3 4 5 6 7 8 9

10 11 12 13 14 15 16

LLC

DDD5

SSD5

VREF

Fig.3 Pin configuration (LQFP64/QFP64).

1997 May 26 10

Philips Semiconductors Preliminary speciﬁcation

Enhanced Video Input Processor (EVIP) SAA7111A

8 FUNCTIONAL DESCRIPTION

8.1 Analog input processing

The SAA7111A offers four analog signal inputs, two analog main channels with source switch, clamp circuit, analog amplifier, anti-alias filter and video CMOS ADC (see Fig.6).

8.2 Analog control circuits

The anti-alias filters are adapted to the line-locked clock frequency via a filter control circuit. During the vertical blanking time, gain and clamping control are frozen.

8.2.1 C

LAMPING

The clamp control circuit controls the correct clamping of the analog input signals. The coupling capacitor is also used to store and filter the clamping voltage. An internal digital clamp comparator generates the information with respect to clamp-up or clamp-down. The clamping levels for the two ADC channels are fixed for luminance (60) and chrominance (128). Clamping time in normal use is set with the HCL pulse at the back porch of the video signal.

HSY

TV line

HCL

MGL065

handbook, halfpage

255

analog line blanking

GAIN CLAMP

Fig.4 Analog line with clamp (HCL) and gain

range (HSY).

8.2.2 G

AIN CONTROL

Signal (white) peak control limits the gain at signal overshoots. The flow charts (see Figs 14 and 15) show more details of the AGC. The influence of supply voltage variation within the specified range is automatically eliminated by clamp and automatic gain control.

The AGC (automatic gain control for luminance) is used to amplify a CVBS or Y signal to the required signal amplitude, matched to the ADCs input voltage range. The AGC active time is the sync bottom of the video signal.

handbook, halfpage

(1 V(p-p) 27/47 Ω)

analog input level

+4.5 dB

−7.5 dB

maximum

minimum

range tbf0 dB

controlled

ADC input level

0 dB

MGG063

Fig.5 Automatic gain range.

8.3 Chrominance processing

The 8-bit chrominance signal is fed to the multiplication inputs of a quadrature demodulator, where two subcarrier signals from the local oscillator DTO1 are applied (0 and 90° phase relationship to the demodulator axis). The frequency is dependent on the present colour standard. The output signals of the multipliers are low-pass filtered (four programmable characteristics) to achieve the desired bandwidth for the colour difference signals (PAL, NTSC) or the 0 and 90° FM-signals (SECAM).

The colour difference signals are fed to the Brightness/Contrast/Saturation block (BCS), which includes the following five functions:

• AGC (Automatic Gain Control for chrominance PAL and NTSC)

• Chrominance amplitude matching (different gain factors for R−Y and B−Y to achieve CCIR-601 levels Cr and Cb for all standards)

• Chrominance saturation control

• Luminance contrast and brightness.

• Limiting YUV to the values 1 (min.) and 254 (max.) to

fulfil CCIR-601 requirements.

The gain control circuit receives (via the I2C-bus) the static gain levels for the two analog amplifiers or controls one of these amplifiers automatically via a built-in automatic gain control (AGC) as part of the Analog Input Control (AICO).

1997 May 26 11

Philips Semiconductors Preliminary speciﬁcation

Enhanced Video Input Processor (EVIP) SAA7111A

The SECAM-processing contains the following blocks:

• Baseband ‘bell’ filters to reconstruct the amplitude and phase equalized 0 and 90° FM-signals

• Phase demodulator and differentiator (FM-demodulation)

• De-emphasis filter to compensate the pre-emphasised input signal, including frequency offset compensation (DB or DR white carrier values are subtracted from the signal, controlled by the SECAM-switch signal).

The burst processing block provides the feedback loop of the chroma PLL and contains;

• Burst gate accumulator

• Colour identification and killer

• Comparison nominal/actual burst amplitude (PAL/NTSC

standards only)

• Loop filter chrominance gain control (PAL/NTSC standards only)

• Loop filter chrominance PLL (only active for PAL/NTSC standards)

• PAL/SECAM sequence detection, H/2-switch generation

• Increment generation for DTO1 with divider to generate stable subcarrier for non-standard signals.

The chrominance comb filter block eliminates crosstalk between the chrominance channels in accordance with the PAL standard requirements. For NTSC colour standards the chrominance comb filter can be used to eliminate crosstalk from luminance to chrominance (cross-colour) for vertical structures. The comb filter can be switched off if desired. The embedded line delay is also used for SECAM recombination (cross-over switches).

The high frequency components of the luminance signal can be peaked (control for sharpness improvement via

C-bus) in two band-pass filters with selectable transfer

I characteristic. This signal is then added to the original (unpeaked) signal. A switchable amplifier achieves common DC amplification, because the DC gains are different in both chrominance trap modes. The improved luminance signal is fed to the BCS control located in the chrominance processing block (see Fig.8).

8.5 RGB matrix

Y, Cr and Cb data are converted after interpolation into RGB data in accordance with CCIR-601 recommendations. The realized matrix equations consider the digital quantization:

R = Y + 1.371 Cr G=Y−0.336 Cb − 0.698 Cr B = Y + 1.732 Cb

After dithering (noise shaping) the RGB data is fed to the output interface within the VPO-bus output formatter.

8.6 VBI-data bypass

For a 27 MHz VBI-data bypass the offset binary CVBS signal is upsampled behind the ADCs. Upsampling of the CVBS signal from 13.5 to 27 MHz is possible, because the ADCs deliver high performance at 13.5 MHz sample clock. Suppressing of the back folded CVBS frequency components after upsampling is achieved by an interpolation filter (see Fig.43).

The TUF block on the digital top level performs the upsampling and interpolation for the bypassed CVBS signal (see Fig.7).

The resulting signals are fed to the variable Y-delay compensation, RGB matrix, dithering circuit and output interface, which contains the VPO output formatter and the output control logic (see Fig.7).

8.4 Luminance processing

The 8-bit luminance signal, a digital CVBS format or a luminance format (S-VHS, HI8), is fed through a switchable prefilter. High frequency components are emphasized to compensate for loss. The following chrominance trap filter (f frequency selectable) eliminates most of the colour carrier signal, therefore, it must be bypassed for S-video (S-VHS, HI8) signals.

1997 May 26 12

= 4.43 or 3.58 MHz centre

For bypass details see Figs 9 to 11.

8.7 VPO-bus (digital outputs)

The 16-bit VPO-bus transfers digital data from the output interfaces to a feature box or a field memory, a digital colour space converter (SAA7192 DCSC), a video enhancement and digital-to-analog processor (SAA7165 VEDA2) or a colour graphics board (Targa-format) as a graphical user interface.

Philips Semiconductors Preliminary speciﬁcation

Enhanced Video Input Processor (EVIP) SAA7111A

The output data formats are controlled via the I2C-bus bits OFTS0, OFTS1 and RGB888. Timing for the data stream formats, YUV (4,: 1 : 1) (12-bit), YUV (4,: 2 : 2) (16-bit), RGB (5, 6, 5) (16-bit) and RGB (8, 8, 8) (24-bit) with an LLC2 data rate, is achieved by marking each second positive rising edge of the clock LLC in conjunction with CREF (clock reference) (except RGB (8, 8, 8), see special application in Fig.33). The higher output signals VPO15 to VPO8 in the YUV format perform the digital luminance signal. The lower output signals VPO7 to VPO0 in the YUV format are the bits of the multiplexed colour difference signals (B−Y) and (R−Y). The arrangement of the RGB (5, 6, 5) and RGB (8, 8, 8) data stream bits on the VPO-bus is given in Table 6.

The data stream format YUV 4:2:2 (the 8 higher output signals VPO15 to VPO8) in LLC data rate fulfils the CCIR-656 standard with its own timing reference code at the start and end of each video data block.

A pixel in the format tables is the time required to transfer a full set of samples. If 16-bit 4 : 2 : 2 format is selected two luminance samples are transmitted in comparison to one (B−Y) and one (R−Y) sample within a pixel.The time frames are controlled by the HREF signal.

Fast enable is achieved by setting input FEI to LOW. The signal is used to control fast switching on the digital VPO-bus. HIGH on this pin forces the VPO outputs to a high-impedance state (see Figs 19 and 20). The I2C-bus bit OEYC has to be set HIGH to use this function.

The digitized PAL, SECAM or NTSC signals AD1 (7 to 0) and AD2 (7 to 0) are connected directly to the VPO-bus via I2C-bus bit VIPB = 1 and MODE = 4, 5, 6 or 7.

AD1 (7 to 0) -> VPO (15 to 8) and AD2 (7 to 0) -> VPO (7 to 0)

• VREF: The VREF output delivers a vertical reference signal or an inverse composite blank signal controlled via the I2C-bus [subaddress 11, inverse composite blank (COMPO)]. Furthermore four different modes of vertical reference signals are selectable via the I2C-bus [subaddress 13, vertical reference output control (VCTR1 and VCTR0)]. The description of VREF timing and position is illustrated in Figs 16, 17, 25 and 26.

• CREF: The CREF output delivers a clock/pixel qualifier signal for external interfaces to synchronize to the VPO-bus data stream.

Four different modes for the clock qualifier signal are selectable via the I2C-bus [subaddress 13, clock reference output control (CCTR1 and CCTR0]. The description of CREF timing and position is illustrated in Figs 17, 19, 21 and 22.

8.9 Synchronization

The prefiltered luminance signal is fed to the synchronization stage. Its bandwidth is reduced to 1 MHz in a low-pass filter. The sync pulses are sliced and fed to the phase detectors where they are compared with the sub-divided clock frequency. The resulting output signal is applied to the loop filter to accumulate all phase deviations. Internal signals (e. g. HCL and HSY) are generated in accordance with analog front-end requirements. The output signals HS, VS, and PLIN are locked to the timing reference, guaranteed between the input signal and the HREF signal, as further improvements to the circuit may change the total processing delay. It is therefore not recommended to use them for applications which require absolute timing accuracy on the input signals. The loop filter signal drives an oscillator to generate the line frequency control signal LFCO (see Fig.8).

The selection of the analog input channels is controlled via I2C-bus subaddress 02 MODE select.

The upsampled 8-bit offset binary CVBS signal (VBI-data bypass) is multiplexed under control of the I2C-bus to the digital VPO-bus (see Fig.9).

8.8 Reference signals HREF, VREF and CREF

• HREF: The positive slope of the HREF output signal indicates the beginning of a new active video line. The high period is 720 luminance samples long and is also present during the vertical blanking. The description of timing and position from HREF is illustrated in Figs 16, 17, 22 and 24.

1997 May 26 13

8.10 Clock generation circuit

The internal CGC generates all clock signals required for the video input processor. The internal signal LFCO is a digital-to-analog converted signal provided by the horizontal PLL. It is the multiple of the line frequency (6.75 MHz = 429/432 × f multiplied by a factor of 2 or 4 in the PLL circuit (including phase detector, loop filtering, VCO and frequency divider) to obtain the LLC and LLC2 output clock signals. The rectangular output clocks have a 50% duty factor (see Fig.27).

). Internally the LFCO signal is

Philips Semiconductors Preliminary speciﬁcation

Enhanced Video Input Processor (EVIP) SAA7111A

8.11 Power-on reset and CE input

A missing clock, insufficient digital or analog V

DDA0

supply voltages (below 2.7 V) will initiate the reset sequence; all outputs are forced to 3-state. The indicator output RES is LOW for approximately 128LLC after the internal reset and can be applied to reset other circuits of the digital TV system.

It is possible to force a reset by pulling the chip enable (CE) to ground. After the rising edge of CE and sufficient power supply voltage, the outputs LLC, LLC2, CREF, RTCO, RTS0, RTS1, GPSW and SDA return from 3-state to active, while HREF, VREF, HS and VS remain in 3-state

and have to be activated via I

C-bus programming (see

Table 5).

8.12 RTCO output

The real time control and status output signal contains serial information about the actual system clock (increment of the HPLL), subcarrier frequency [increment and phase (via reset) of the FSC-PLL] and PAL sequence bit. The signal can be used for various applications in external circuits, e.g. in a digital encoder to achieve clean encoding (see Fig.21).

8.13.1 S

UGGESTIONS FOR I

DISPLAY SOFTWARE READING LINE

C-BUS INTERFACE OF THE

-21 DATA

There are two methods by which the software can acquire the data:

1. Synchronous reading once per frame (or once per field); It can use either the rising edge (Line-21 Field 1) or both edges (Line-21 Field 1 or 2) of the ODD signal (pin RTSO) to initiate an I2C-bus read transfer of the three registers 1A, 1B and 1C.

2. Asynchronous reading; It can poll either the F1RDY bit (Line-21 Field 1) or both F1RDY/F2RDY bits (Line-21 Field 1 or 2). After valid data has been read the corresponding F*RDY bit is set to LOW until new data has arrived. The polling frequency has to be slightly higher than the frame or field frequency, respectively.

8.13 The Line-21 text slicer

The text slicer block detects and acquires Line-21 Closed Captioning data from a 525-line CVBS signal. Extended data services on Line-21 Field 2 are also supported. If valid data is detected the two data bytes are stored in two I2C-bus registers. A parity check is also performed and the result is stored in the MSB of the corresponding byte. A third I2C-bus register is provided for data valid and data ready flags. The two bits F1VAL and F2VAL indicate that the input signal carries valid Closed Captioning data in the corresponding fields. The data ready bits F1RDY and F2RDY have to be evaluated if asynchronous I2C-bus reading is used.

1997 May 26 14

Philips Semiconductors Preliminary speciﬁcation

Enhanced Video Input Processor (EVIP) SAA7111A

AOUT

(14) 23

AND

TEST

SELECTOR

BUFFER

ADC2

AOSL (1 : 0)

SWITCH

BYPASS

FILTER

ANTI-ALIAS

DAC9

ANALOG

AMPLIFIER

FUSE (1 : 0)

ANALOG

ADC1

SWITCH

BYPASS

FILTER

ANTI-ALIAS

DAC9

AMPLIFIER

VERTICAL

FUSE (1 : 0)

CONTROL

BLANKING

CONTROL

ANTI-ALIAS

GAIN

CONTROL

VBLNK

SVREF

VBSL 8 8

HOLDG

GAFIX

HSY

GLIMB

GLIMT

WPOFF

GAI20-GAI28

GAI10-GAI18

GUDL0-GUDL2

HLNRS

WIPA

SLTCA

AD1BYPAD2BYP

handbook, full pagewidth

CROSS MULTIPLEXER

UPTCV

Fig.6 Analog input processing.

987 (64)

n.c.

18 (9)

SSA1

14 (5)

SSA2

CLAMP

CIRCUIT

SWITCH

SOURCE

15 (6)

17 (8)

AI22

AI21

20 (11)

DDA1

16 (7)

DDA2

CLAMP

CIRCUIT

SWITCH

SOURCE

19 (10)

21 (12)

AI12

AI11

1997 May 26 15

CLAMP

CONTROL

MODE

CONTROL

HCL

MODE 0

MODE 1

MODE 2

ANALOG

CONTROL

22 (13)

SSS

CHRLUM

MGC655

The pin numbers given in parenthesis refer to the 64-pin package.

Philips Semiconductors Preliminary speciﬁcation

Enhanced Video Input Processor (EVIP) SAA7111A

k, full pagewidth

AD1BYPAD2BYP

sequential

SECAM

PROCESSING

UV signals

LEVEL

LOW-PASS

FEI

(52) 63

53 to 62

(42 to 51),

OUTPUT

RGB

RGB MATRIX

AND

CONTRAST,

BRIGHTNESS,

ADJUSTMENT,

VPO

(9 : 0)

VPO

45 to 50

(34 to 39),

AND

INTERFACE

FORMATTER

dithering

interpolation

CONTROL

SATURATION

PHASE

DETECTOR

AMPLITUDE

DEMODULATOR

HREF

(15 : 10)

(31) 42

COMB

FILTERS

DIT CBR

GAIN

CONTROL

AND Y-DELAY

COMPENSATION

BURST GATE

LOOP FILTER

ACCUMULATOR

GPSW

RTSE1

OFTS0

OFTS1

SECAM

DCCF

RECOMBINATION

BRIG

CONT

CODE

FCTCCSTD 1

RTSE0

VIPB

VLOF

RGB888

OEYC

OEHV

/2 switch signal

SATN

COLO

COMPO

FECO

VRLN

RTCO

(60) 3

VSTA (8 : 0)

VSTO (8 : 0)

MGG062

Fig.7 Chrominance circuit.

CHBW0

CHRLUM

10 (1)

n.c.

CHBW1

QUADRATURE

DEMODULATOR

TEST

CONTROL

2 (59)

1 (58)

13 (4)

12 (3)

TDI

TCK

TRST

BLOCK

11 (2)

TDO

TMS

SUBCARRIER

AND

INCREMENT

SUBCARRIER

GENERATION

HUEC

GENERATION

POWER-ON

(57,41,33,

25,18)

68,52,44,

34,27

DDD1-5

1997 May 26 16

DIVIDER

CONTROL

32 (23)

RES

INCS

CSTD 0

CLOCKS CE

(56,40,32,26,19)

TUF

VBI DATA BYPASS

67,51,43,35,28

SSD1-5

LUM

The pin numbers given in parenthesis refer to the 64-pin package.

Philips Semiconductors Preliminary speciﬁcation

Enhanced Video Input Processor (EVIP) SAA7111A

DDA0VSSA0

CREF

LLC

LLC2

XTALI

XTAL

(22) 31

CLOCKS

(21)30

(20) 29

CLOCK

GENERATOR

LINE-LOCKED

(24)33

(16) 25

(15) 24

CLOCK

CIRCUIT

GENERATION

(54) 65

(55) 66

CLOCK

CRYSTAL

GENERATOR

MGC654

CLOCK CIRCUIT

DAC6

INCS

APER0

APER1

AND

ADDING

STAGE

WEIGHTING

VBLB

AMPLIFIER

MATCHING

VBLB

PHASE

FINE

PHASE

DETECTOR

COARSE

DETECTOR

AUFD

HSB

HPLL

HSS

VTRC

EXFIL

STTC

HLCK

FSEL

VTRC

TIME

DISCRETE

OSCILLATOR 2

LOOP FILTER

(28)

(27)

COUNTER

RTS1

handbook, full pagewidth

BPSS0

BPSS1

FILTER

VARIABLE

BAND-PASS

PREF

SYNC SLICER

LUMINANCE CIRCUIT

TRAP

CHROMINANCE

LUM

PREFILTER

BYPS

VBLB

PREF

SYNC

PREFILTER

TEXT

LINE 21

1997 May 26 17

FIDT

VNOI0

VNOI1

VTRC

SYNCHRONIZATION CIRCUIT

BYTE1

SLICER

BYTE2

STATUS

I C BUS CONTROL

VERTICAL

PROCESSOR

I C-BUS

INTERFACE

64 (53)

GPSW

(17) (29)

(30)

(62)

(63)

(61)

VREF

RTS0

SDASCLIICSA

Fig.8 Luminance and sync processing.

The pin numbers given in parenthesis refer to the 68-pin package.

Philips Semiconductors Preliminary speciﬁcation

Enhanced Video Input Processor (EVIP) SAA7111A

handbook, full pagewidth

TBP7 to 0

(CVBS)

Y or YUV

BCHI1 to 0

C-bus

VBP0

VBP4

MUX

CVBS

(LUMA see Fig. 37)

SWHI

BCHI1 BCHI0 SWHI

0 0 1 1

AD1BYP

0 1 0 1

0 VBP0 VBP4

MUX BYP

VPO15 to 8

VPIB

C-bus

UV or YUV

BCLO1 to 0

C-bus

V_GATE

(programmable)

HREFINT

VBP0

VBP4

MUX

CVBS

(CHROMA see Fig. 37)

SWLO

BCLO1 BCLO0 SWLO

0 0 1 1

AD2BYP

0 1 0 1

REG

CLOCK 0

0 VBP0 VBP4

MUX BYP

4 × REG

CLOCK 0

VPO7 to 0

VBP4

VBP0

MGG064

HREFINT = internal horizontal reference. TBP = upsampled CVBS input data (27 MHz). AD1BYP/AD2BYP = digitized CVBS input data and Y/C input data (13.5 MHz). VBP0 = programmable vertical reference signal. VBP4 = delayed programmable vertical reference signal (4LLC clocks delay).

Fig.9 Multiplexing of the CVBS signal to the VPO-bus.

1997 May 26 18

Philips Semiconductors Preliminary speciﬁcation

Enhanced Video Input Processor (EVIP) SAA7111A

handbook, full pagewidth

VREF CCIR 656

HREFINT

VBP0 VBP4

VREFINT

HREFINT

VREF_CCIR 656 = vertical reference signal referring to the field interval definitions of CCIR656. HREFINT = internal horizontal reference signal. VREFINT = internal vertical reference signal. VBP0 = programmable vertical reference signal. VBP4 = delayed programmable vertical reference signal (4LLC clocks delay).

REG

CLOCK 0

VREFINT

VREF CCIR 656

VBP0

VBP4

VCTR1 to 0

VREFOUT

Fig.10 VREF output signal generation.

MUX

COMPO

REG

VREF

CLOCK 0

MGG065

handbook, full pagewidth

CREFINT

selected

VREF

CCTR1 to 0

CREFINT = internal clock qualifier signal.

CREFOUT

CREFINT 0 if VREF = 0 1 if VREF = 0 1 (always HIGH)

Fig.11 CREF output signal generation.

1997 May 26 19

REG

CREF

CLOCK 0

MGG066

Philips Semiconductors Preliminary speciﬁcation

Enhanced Video Input Processor (EVIP) SAA7111A

9 BOUNDARY-SCAN TEST

The SAA7111A has built in logic and 5 dedicated pins to support boundary-scan testing which allows board testing without special hardware (nails). The SAA7146 follows the

“IEEE Std. 1149.1 - Standard Test Access Port and Boundary-Scan Architecture

Group (JTAG) chaired by Philips. The 5 special pins are Test Mode Select (TMS), Test

Clock (TCK), Test Reset (TRST), Test Data Input (TDI) and Test Data Output (TDO).

The BST functions BYPASS, EXTEST, INTEST, SAMPLE, CLAMP and IDCODE are all supported (see Table 1). Details about the JTAG BST-TEST can be found in the specification “ containing the detailed Boundary-Scan Description Language (BSDL) description of the SAA7111A is available on request.

9.1 Initialization of boundary-scan circuit

The TAP controller of an IC should be in the reset state (TEST_LOGIC_RESET) when the IC is in functional mode. This reset state also forces the instruction register into a functional instruction such as IDCODE or BTPASS.

” set by the Joint Test Action

EEE Std. 1149.1”

. A file

9.2 Device identiﬁcation codes

A Device Identification Register (DIR) is specified in

“IEEE Std. 1149.1-1990 - IEEE Standard Test Access Port and Boundary-Scan Architecture

is a 32-bit register which contains fields for the specification of the IC manufacturer, the IC part number and the IC version number. Its biggest advantage is the possibility to check for the correct ICs mounted after production and determination of the version number of ICs during field service.

When the IDCODE instruction is loaded into the BST instruction register, the identification register will be connected between TDI and TDO of the IC. The identification register will load a component specific code during the CAPTURE_DATA_REGISTER state of the TAP controller and this code can subsequently be shifted out. At board level this code can be used to verify component manufacturer, type and version number. The device identification register contains 32-bits, numbered 31 to 0, where bit 31 is the Most Significant Bit (MSB) (nearest to TDI) and bit 0 is the Least Significant Bit (LSB) (nearest to TDO); see Fig.12.

” (IEEE Std. 1149.1b-1994). It

To solve the power-up reset, the standard specifies that the TAP controller will be forced asynchronously to the TEST_LOGIC_RESET state by setting the TRST pin LOW.

Table 1 BST instructions supported by the SAA7111A

INSTRUCTION DESCRIPTION

BYPASS this mandatory instruction provides a minimum length serial path (1 bit) between TDI and TDO

when no test operation of the component is required

EXTEST this mandatory instruction allows testing of off-chip circuitry and board level interconnections

SAMPLE This mandatory instruction can be used to take a sample of the inputs during normal operation of

the component. It can also be used to preload data values into the latched outputs of the boundary-scan register.

CLAMP This optional instruction is useful for testing when not all ICs have BST. This instruction addresses

the bypass register while the boundary-scan register is in external test mode.

IDCODE this optional instruction will provide information on the components manufacturer, part number and

version number

INTEST this optional instruction allows testing of the internal logic (no support for customers available)

USER1 this private instruction allows testing by the manufacturer (no support for customers available)

1997 May 26 20

Philips Semiconductors Preliminary speciﬁcation

Enhanced Video Input Processor (EVIP) SAA7111A

handbook, full pagewidth

MSB LSB 31

28 27 12 11 1 0

TDI TDO

4-bit

version

code

16-bit part number 11-bit manufacturer

0000001010111110001000100010010

indentification

MGL111

Fig.12 32 bits of identification code.

1997 May 26 21

Philips Semiconductors Preliminary speciﬁcation

Enhanced Video Input Processor (EVIP) SAA7111A

10 GAIN CHARTS

handbook, full pagewidth

handbook, halfpage

7.5

factor

5.5

3.5

bit [8] = 1

1.5

−0.5

−2.5

−4.5

= 20 x log10 gain =

i > 256

= 20 x log10 gain =

factor

(

bit [8] = 0

256 512

gain value (i)

Fig.13 Amplifier curve.

ANALOG INPUT

512

768 − i

(

i < 256

(

MGC648

257 + i

512

(

ADC

NO BLANKING ACTIVE

10 10

CLL

+ CLAMP − CLAMP

WIPE = white peak level (254); SBOT = sync bottom level (1); CLL = clamp level [60 Y (128 C)]; HSY = horizontal sync pulse; HCL = horizontal clamp pulse.

VBLK

GAIN -><- CLAMP

HCL HSY

01 10

SBOT

NO CLAMP

+ GAIN − GAIN

Fig.14 Clamp and gain flow.

fast − GAIN

WIPE

slow + GAIN

MGC647

1997 May 26 22

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