Philips SAA7111 Datasheet

INTEGRATED CIRCUITS

DATA SH EET

SAA7111

Video Input Processor (VIP)

Preliminary specification
Supersedes data of 1996 May 15
File under Integrated Circuits, IC22

1996 Oct 30

Philips Semiconductors Preliminary specification

Video Input Processor (VIP) SAA7111

CONTENTS

1 FEATURES
2 APPLICATIONS
3 GENERAL DESCRIPTION
4 QUICK REFERENCE DATA
5 ORDERING INFORMATION
6 BLOCK DIAGRAM
7 PINNING
8 FUNCTIONAL DESCRIPTION

8.1 Analog input processing

8.2 Analog control circuits

8.2.1 Clamping

8.2.2 Gain control

8.3 Chrominance processing

8.4 Luminance processing

8.5 RGB matrix

8.6 VPO-bus (digital outputs)

8.7 Synchronization

8.8 Clock generation circuit

8.9 Power-on reset and CE input

8.10 RTCO output

8.11 The Line-21 text slicer

8.11.1 Suggestions for I2C-bus interface of the display
software reading line-21 data

9 GAIN CHARTS
10 LIMITING VALUES
11 CHARACTERISTICS
12 TIMING DIAGRAMS
13 CLOCK SYSTEM

13.1 Clock generation circuit

13.2 Power-on control

14 OUTPUT FORMATS
15 APPLICATION EXAMPLES
16 I2C-BUS DESCRIPTION

16.1 I2C-bus format

16.2 I2C-bus detail

16.2.1 Subaddress 00

16.2.2 Subaddress 02

16.2.3 Subaddress 03

16.2.4 Subaddress 04

16.2.5 Subaddress 05

16.2.6 Subaddress 06

16.2.7 Subaddress 07

16.2.8 Subaddress 08

16.2.9 Subaddress 09

16.2.10 Subaddress 0A

16.2.11 Subaddress 0B

16.2.12 Subaddress 0C

16.2.13 Subaddress 0D

16.2.14 Subaddress 0E

16.2.15 Subaddress 10

16.2.16 Subaddress 11

16.2.17 Subaddress 12

16.2.18 Subaddress 1A (read-only register)

16.2.19 Subaddress 1B (read-only register)

16.2.20 Subaddress 1C (read-only register)

16.2.21 Subaddress 1F (read-only register)
17 FILTER CURVES

17.1 Anti-alias filter curve

17.2 Luminance filter curves

17.3 Chrominance filter curves
18 I2C START SET-UP
19 PACKAGE OUTLINE
20 SOLDERING

20.1 Introduction

20.2 Reflow soldering

20.3 Wave soldering

20.3.1 PLCC

20.3.2 QFP

20.3.3 Method (PLCC and QFP)

20.4 Repairing soldered joints
21 DEFINITIONS
22 LIFE SUPPORT APPLICATIONS
23 PURCHASE OF PHILIPS I2C COMPONENTS

1996 Oct 30 2

Philips Semiconductors Preliminary specification

Video Input Processor (VIP) SAA7111

1 FEATURES

• Four analog inputs, internal analog source selectors,

e.g. 4 × CVBS or 2 × Y/C or (1 × Y/C and 2 × CVBS)

• Two analog preprocessing channels

• Fully programmable static gain for the main channels or

automatic gain control for the selected CVBS or Y/C
channel

• Switchable white peak control

• Two built-in analog anti-aliasing filters

• Two 8-bit video CMOS analog-to-digital converters

(ADCs)

• On-chip clock generator

• Line-locked system clock frequencies

• Digital PLL for H-sync processing and clock generation

• Requires only one crystal (24.576 MHz) for all standards

• Horizontal and vertical sync detection

• Automatic detection of 50/60 Hz field frequency, and

automatic switching between standards PAL and NTSC

• Luminance and chrominance signal processing for

PAL BGHI, PAL N, PAL M, NTSC M, NTSC N and
NTSC 4.43

• User programmable luminance peaking or aperture

correction

• Cross-colour reduction for NTSC by chrominance comb

filtering

• PAL delay line for correcting PAL phase errors

• Real time status information output (RTCO)

• Brightness Contrast Saturation (BCS) control on-chip

• The YUV (CCIR-601) bus supports a data rate of:

– 864 × f

= 13.5 MHz for 625 line sources

H

– 858 × fH= 13.5 MHz for 525 line sources

• Data output streams for 16, 12 or 8-bit width with the

following formats:
– 411 YUV (12-bit)
– 422 YUV (16-bit)
– 422 YUV [CCIR-656] (8-bit)
– 565 RGB (16-bit) with dither
– 888 RGB (24-bit) with special application

• 720 active samples per line on the YUV bus

• One user programmable general purpose switch on an

output pin

• Built in line-21 text slicer

• Power-on control

• Two switchable outputs for the digitized CVBS or Y/C

input signals AD1 (7 to 0) and AD2 (7 to 0) via the

2

I

C-bus

• Chip enable function (reset for the clock generator)

• Compatible with memory-based features (line-locked

clock)

• Boundary scan test circuit complies with the

“IEEE Std. 1149.1−1990”

(ID-Code = 0 7111 02 B)

• I2C-bus controlled (full read-back ability by an external
controller).

2 APPLICATIONS

• Desktop video

• Multimedia

• Digital television

• Image processing

• Video phone.

3 GENERAL DESCRIPTION

The Video Input Processor (VIP) is a combination of a
two-channel analog preprocessing circuit including source
selection, anti-aliasing filter and ADC, an automatic clamp
and gain control, a Clock Generation Circuit (CGC), a
digital multi-standard decoder (PAL BGHI, PAL M, PAL N,
NTSC M and NTSC N), a brightness/contrast/saturation
control circuit and a colour space matrix (see Fig.1).

The CMOS circuit SAA7111, analog front-end and digital
video decoder, is a highly integrated circuit for desktop
video applications. The decoder is based on the principle
of line-locked clock decoding and is able to decode the
colour of PAL and NTSC signals into CCIR-601
compatible colour component values. The SAA7111
accepts as analog inputs CVBS or S-video (Y/C) from

2

TV or VTR sources. The circuit is I

C-bus controlled.

1996 Oct 30 3

Philips Semiconductors Preliminary specification

Video Input Processor (VIP) SAA7111

4 QUICK REFERENCE DATA

SYMBOL PARAMETER MIN. TYP. MAX. UNIT

V

DDD

V

DDA

T

amb

P

A+D

5 ORDERING INFORMATION

digital supply voltage 4.5 5.0 5.5 V
analog supply voltage 4.75 5.0 5.25 V
operating ambient temperature 0 25 70 °C
analog and digital power 0.77 1.0 1.26 W

TYPE NUMBER

PACKAGE

NAME DESCRIPTION VERSION

SAA7111 PLCC68 plastic leaded chip carrier; 68 leads SOT188-2
SAA7111 QFP64 plastic quad flat package; 64 leads (lead length 1.6 mm);

SOT393-1

body 14 × 14 × 2.7 mm

1996 Oct 30 4

Philips Semiconductors Preliminary specification

Video Input Processor (VIP) SAA7111

6 BLOCK DIAGRAM

handbook, full pagewidth

BYPASS

AI11
AI12

AI21
AI22

n.c.

V

SS

n.c.

TDI

TCK

TMS

TDO

23 (14)

21 (12)
19 (10)

17 (8)
15 (6)

7,8,9 (64)
22 (13)

10,36,
37

18,14 (9,5)
20,16 (11,7)

12 (3)
2 (59)
13 (4)
1 (58)

11 (2)

ANALOG

PROCESSING

AND

ANALOG-TO-

DIGITAL

CONVERSION



AD2 AD1

ANALOG

PROCESSING

CONTROL

TEST

CONTROL

BLOCK

FOR
BOUNDARY
SCAN TEST

AND
SCAN TEST

CON

C/CVBS

Y/CVBS

Y

SYNCHRONIZATION

CHROMINANCE

CIRCUIT

AND

BRIGHTNESS

CONTRAST

SATURATION

CONTROL

LUMINANCE

CIRCUIT

SAA7111

CIRCUIT

Y

UV

LFCO

45 to 50

YUV-to-RGB

CONVERSION

AND

OUTPUT

FORMATTER

Y

2

I C-BUS

CONTROL

2

I C-BUS

INTERFACE

CLOCKS

CLOCK

GENERATION

CIRCUIT

POWER-ON

CONTROL

53 to 62

(34 to 39)
(42 to 51)

(52) 63
(31) 42

(53) 64

(61) 4
(62) 5
(63) 6

(54) 65
(55) 66

(21) 30
(22) 31
(20) 29

(23) 32

VPO
(0 : 15)

FEI
HREF

GPSW

IICSA
SDA
SCL

XTAL
XTALI

LLC2
CREF
LLC
RES

AOUT

V

SSA1-2

V

DDA1-2

TRST

(57,41,33,25,18)
68,52,44,34,27

V

DD1-5

The pin numbers given in parenthesis refer to the 64-pin package.

(56,40,32,26,19)
67,51,43,35,28

V

SS1-5

(30)41(27)38(17)26(29)40(28)39(60)

HSVS

VREF

Fig.1 Block diagram.

1996 Oct 30 5

RTS0

RTS1

RTCO

3

(15)24(16)25(24)

DDA0

V

SSA0

V

33

MGC653

CE

Philips Semiconductors Preliminary specification

Video Input Processor (VIP) SAA7111

7 PINNING

SYMBOL

I/O DESCRIPTION

PLCC68 QFP64

TRST 1 58 I Test reset input not (active LOW), for boundary scan test;

notes 1, 2, 3 and 4.
TCK 2 59 I Test clock input for boundary scan test; note 3>
RTCO 3 60 O Real time control output: contains information about actual system

clock frequency, subcarrier frequency and phase and PAL sequence>

PINS

2

IICSA 4 61 I I

C-bus slave address select input; 0 = > 48h for write, 49h for read,

1 = > 4Ah for write, 4Bh for read.

2

SDA 5 62 I/O I
SCL 6 63 I/O I

C-bus serial data input/output.

2

C-bus serial clock input/output.
n.c. 7 64 − Not connected.
n.c. 8 −−Not connected.
n.c. 9 −−Not connected.
n.c. 10 1 − Not connected.
TDO 11 2 O Test data output for boundary scan test; note 3.
TDI 12 3 I Test data input for boundary scan test; note 3.
TMS 13 4 I Test mode select input for boundary scan test or scan test; note 3.
V

SSA2

14 5 GND Ground for analog supply voltage channel 2.
AI22 15 6 I Analog input 22.
V

DDA2

16 7 P Positive supply voltage (+5 V) for analog channel 2.
AI21 17 8 I Analog input 21.
V

SSA1

18 9 GND Ground for analog supply voltage channel 1.
AI12 19 10 I Analog input 12.
V

DDA1

20 11 P Positive supply voltage (+5 V) for analog channel 1.
AI11 21 12 I Analog input 11.
V

SSS

22 13 GND Substrate (connected to analog ground).
AOUT 23 14 O Analog test output; for testing the analog input channels.
V

DDA0

V

SSA0

VREF 26 17 O Vertical reference output signal (I

24 15 P Positive supply voltage (+5 V) for internal CGC.

25 16 GND Ground for internal CGC.

2

C-bit COMPO = 0) or inverse
composite blank signal (I2C-bit COMPO = 1) (enabled via I2C-bit
OEHV).

V
V

DD5
SS5

27 18 P Positive digital supply voltage 5 (+5 V).
28 19 GND Digital ground for positive supply voltage 5.

LLC 29 20 O Line-locked system clock output (27 MHz).

1

LLC2 30 21 O Line-locked clock

⁄2output (13.5 MHz).

CREF 31 22 O Clock reference output: this is a clock qualifier signal distributed by

the CGC for a data rate of LLC2. Using CREF all interfaces on the
VPO-bus are able to generate a bus timing with identical phase. If
CCIR-656 format is selected (OFTS0 = 1 and OFTS1 = 1) an inverse
composite blank signal (pixel qualifier) is provided on this pin.

1996 Oct 30 6

Philips Semiconductors Preliminary specification

Video Input Processor (VIP) SAA7111

SYMBOL

I/O DESCRIPTION

PLCC68 QFP64

RES 32 23 O Reset output (active LOW); sets the device into a defined state. All

data outputs are in high impedance state. The I2C-bus is reset
(waiting for start condition) note 4.

CE 33 24 I Chip enable; connection to ground forces a reset.

PINS

V
V

DD4
SS4

34 25 P Positive digital supply voltage 4 (+5 V).

35 26 GND Digital ground for positive supply voltage 4.
n.c. 36 −−Not connected.
n.c. 37 −−Not connected.
HS 38 27 O Horizontal sync output signal (programmable); the positions of the

positive and negative slopes are programmable in 8 LLC increments

2

over a complete line (= 64 µs) via I

C-bus bytes HSB and HSS. Fine
position adjustment in 2 LLC increments can be performed via
I2C-bits HDEL1 and HDEL0.

2

RTS1 39 28 O Two functions output; controlled by I

C-bit RTSE1.
RTSE1 = 0: PAL line identifier (LOW = PAL line); indicates the
inverted and non-inverted R − Y component for PAL signals.
RTSE1 = 1: H-PLL locked indicator; a high state indicates that the
internal horizontal PLL has locked.

2

RTS0 40 29 O Two functions output; controlled by I

C-bit RTSE0.
RTSE0 = 0: odd/even field identification (HIGH = odd field).
RTSE0 = 1: vertical locked indicator; a HIGH state indicates that the
internal VNL has locked.

2

VS 41 30 O Vertical sync output signal (enabled via I

C-bit OEHV); this signal
indicates the vertical sync with respect to the YUV output. The HIGH
period of this signal is approximately six lines if the vertical noise
limiter (VNL) function is active. The positive slope contains the phase
information for a deflection controller.

2

HREF 42 31 O Horizontal reference output signal (enabled via I

C-bit OEHV); this
signal is used to indicate data on the digital YUV bus. The positive
slope marks the beginning of a new active line. The HIGH period of
HREF is 720 Y samples long. HREF can be used to synchronize data
multiplexer/demultiplexers. HREF is also present during the vertical
blanking interval.

V
V

SS3
DD3

43 32 GND Digital ground for positive supply voltage 3.
44 33 P Positive digital supply voltage 3 (+5 V).

VPO (15 to 10) 45 to 50 34 to 39 O Digital VPO-bus (Video Port Out) output signal; higher bits of the

16-bit YUV-bus or the 16-bit RGB-bus output signal. The output data
rate, the format and multiplexing scheme of the VPO-bus are

2

controlled via I

C-bits OFTS0 and OFTS1. With I2C-bit VIPB = 1 the
six MSBs of the digitized input signal (AD1 [7 to 2]) are connected to
these outputs.

V
V

SS2
DD2

51 40 GND Digital ground for positive supply voltage 2.
52 41 P Positive digital supply voltage 2 (+5 V).

1996 Oct 30 7

Philips Semiconductors Preliminary specification

Video Input Processor (VIP) SAA7111

SYMBOL

I/O DESCRIPTION

PLCC68 QFP64

VPO (9 to 0) 53 to 62 42 to 51 O Digital VPO-bus output signal; lower bits of the 16-bit YUV-bus or the

16-bit RGB-bus output signal. The output data rate, the format and
multiplexing schema of the VPO-bus are controlled via I2C-bits
OFTS0 and OFTS1. With I2C-bit VIPB = 1 the digitized input signals
(AD1 [1 and 0] and AD2 [7 to 0]) are connected to these outputs.

FEI 63 52 I Fast enable input signal (active LOW); this signal is used to control

fast switching on the digital YUV-bus. A HIGH at this input forces the
IC to set its Y and UV outputs to the high impedance state; note 4.

GPSW 64 53 O General purpose switch output; the state of this signal is set via

PINS

2

C-bus control and the levels are TTL compatible.

I

XTAL 65 54 O Second output terminal of crystal oscillator; not connected if external

clock signal is used.

XTALI 66 55 I Input terminal for 24.576 MHz crystal oscillator or connection of

external oscillator with CMOS compatible square wave clock signal.

V
V

SS1
DD1

67 56 GND Digital ground for positive supply voltage 1.
68 57 P Positive digital supply voltage 1 (+5 V).

Notes

1. For board design without boundary scan implementation (pin compatibility with the SAA7110) connect theTRST pin
to ground.

2. This pin provides easy initialization of BST circuit. TRST can be used to force the TAP (Test Access Port) controller
to the Test-Logic-Reset state (normal operation) at once.

3. In accordance with the

“IEEE1149.1”

standard the pads TCK, TDI, TMS and TRST are input pads with an internal

pull-up transistor and TDO a 3-state output pad.

4. All pin names that carry an ‘overscore’ have been renamed due to Philips pin name conventions. In previous data
sheet versions these pins were marked by the suffix ‘N’, e.g. TRST = TRSTN.

1996 Oct 30 8

Philips Semiconductors Preliminary specification

Video Input Processor (VIP) SAA7111

DD1VSS1

handbook, full pagewidth

n.c.
9

n.c.

8

n.c.
7

SCL
6

SDA
5

IICSA
4

RTCO
3

TCK
2

TRST
1

V



68

67

66 XTALI

XTAL
65

GPSW
64

FEI
63

VPO0
62

VPO1

61

V

SSA2

V

DDA2

V

SSA1

V

DDA1

AOUT

V

DDA0

V

SSA0

VREF

n.c.

TDO

TDI

TMS

AI22

AI21

AI12

AI11

V

SS

10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26

SAA7111

60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44

VPO3
VPO3
VPO4
VPO5
VPO6
VPO7
VPO8
VPO9

V

DD2

V

SS2

VPO10
VPO11
VPO12
VPO13
VPO14
VPO15

V

DD3

27

28

29LLC

30

31

32

33

34

V

DD5

V

SS5

LLC2

CREF

RES

CE

V

DD4

Fig.2 Pin configuration (PLCC68).

1996 Oct 30 9

35

V

SS4

36
n.c.

37

n.c.

38
HS

39

RTS1

40

RTS0

41
VS

42

HREF

43

V

MGC636

SS3

Philips Semiconductors Preliminary specification

Video Input Processor (VIP) SAA7111

handbook, full pagewidth

SS1

DD1

TRST

V

58

57

SAA7111

23

24
CE

RES

V

56

25

DD4

V

XTALI
55

26

SS4

V

XTAL
54

27
HS

GPSW
53

28

RTS1

FEI

52

29

RTS0

VPO0

51

30
VS

VPO1
50

31

HREF

VPO2
49

32

MBH226

SS3

V

48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33

VPO3
VPO4
VPO5

VPO6
VPO7
VPO8
VPO9
V

DD2

V

SS2

VPO10
VPO11
VPO12
VPO13
VPO14
VPO15

V

DD3

V

SSA2

V

DDA2

V

SSA1

V

DDA1

AOUT

V

DDA0

V

SSA0

n.c.

TDO

TDI

TMS

AI22

AI21

AI12

AI11

V

SS

RTCO
60

21

LLC2

TCK
59

22

CREF

IICSA

SDA

SCL

n.c.
64

63

62

61
1
2
3
4
5
6
7
8
9

10
11
12
13
14
15
16

17

18

19

20

LLC

SS5

DD5

V

V

VREF

Fig.3 Pin configuration (QFP64).

1996 Oct 30 10

Philips Semiconductors Preliminary specification

Video Input Processor (VIP) SAA7111

8 FUNCTIONAL DESCRIPTION

8.1 Analog input processing

The SAA7111 offers four analog signal inputs, two analog
main channels with clamp circuit, analog amplifier,
anti-alias filter and video CMOS ADC (see Fig.6).

8.2 Analog control circuits

The anti-alias filters are adapted to the line-locked clock
frequency with help from a filter control. During the vertical
blanking, time gain and clamping control are frozen.

8.2.1 C

LAMPING

The clamp control circuit controls the correct clamping of
the analog input signals. The coupling capacitor is also
used to store and filter the clamping voltage. An internal
digital clamp comparator generates the information with
respect to clamp-up or clamp-down. The clamping levels
for the two ADC channels are fixed for luminance (60) and
chrominance (128). Clamping time in normal use is set
with the HCL pulse at the back porch of the video signal.

control (AGC) as part of the Analog Input Control (AICO).
The AGC (automatic gain control for luminance) is used to
amplify a CVBS or Y signal to the required signal
amplitude, matched to the ADCs input voltage range.
The AGC active time is the sync bottom of the video signal.

handbook, halfpage

(1 V(p-p) 75 Ω)

analog input level

maximum

+4 dB

−6 dB

minimum

range 10 dB0 dB

controlled

ADC input level

0 dB

MGC660

Fig.5 Automatic gain range.

HSY

TV line

HCL

MGC661

handbook, halfpage

225

60

1

analog line blanking

GAIN CLAMP

Fig.4 Analog line with clamp (HCL) and gain

range (HSY).

8.2.2 G

AIN CONTROL

Signal (white) peak control limits the gain at signal
overshoots. The flow charts (see Figs 10 and 11) show
more details of the AGC. The influence of supply voltage
variation within the specified range is automatically
eliminated by clamp and automatic gain control.

The gain control circuit receives (via the I2C-bus) the static
gain levels for the two analog amplifiers or controls one of
these amplifiers automatically via a built-in automatic gain

8.3 Chrominance processing

The 8-bit chrominance signal is fed to the multiplication
inputs of a quadrature demodulator, where two subcarrier
signals from the local oscillator DTO1 are applied
(0 and 90° phase relationship to the demodulator axis).
The frequency is dependent on the present colour
standard. The output signals of the multipliers are
low-pass filtered (four programmable characteristics) to
achieve the desired bandwidth for the colour difference
signals.

The colour difference signals are fed to the
Brightness/Contrast/Saturation block (BCS), which
includes the following five functions;

1. AGC (automatic gain control for chrominance).

2. Chroma amplitude matching [different gain factors for
(R−Y) and (B−Y) to achieve CCIR-601 levels Cr
and Cb].

3. Chroma saturation control.

4. Luminance contrast and brightness.

5. Limiting YUV to the values 1 (min.) and 254 (max.) to
fulfil CCIR-601 requirements.

1996 Oct 30 11

Philips Semiconductors Preliminary specification

Video Input Processor (VIP) SAA7111

The burst processing block provides the feedback loop of
the chroma PLL and contains;

Burst gate accumulator
Colour identification and killer
Comparison nominal/actual burst amplitude
Loop filter chroma gain control
Loop filter chroma PLL
PAL sequence generation
Increment generation for DTO1 with divider to generate

stable subcarrier for non-standard signals.

The chroma comb filter block eliminates crosstalk between
the chrominance channels in accordance with the PAL
standard requirements. For NTSC colour standards the
chroma comb filter can be used to eliminate crosstalk from
luminance to chrominance (cross-colour) for vertical
structures. The comb filter can be switched off if desired.

The resulting signals are fed to the variable Y-delay
compensation, RGB matrix, dithering circuit and output
interface, which contains the VPO output formatter and the
output control logic (see Fig.7).

8.4 Luminance processing

The 8-bit luminance signal, a digital CVBS format or a
luminance format (S-VHS, HI8), is fed through a
switchable prefilter. High frequency components are
emphasized to compensate for loss. The following
chrominance trap filter (f
frequency selectable) eliminates most of the colour carrier
signal, therefore, it must be bypassed for S-video
(S-VHS, HI8) signals.

The high frequency components of the luminance signal
can be peaked (control for sharpness improvement via
I2C-bus) in two band-pass filters with selectable transfer
characteristic. This signal is then added to the original
(unpeaked) signal. A switchable amplifier achieves
common DC amplification, because the DC gains are
different in both chrominance trap modes. The improved
luminance signal is fed to the BCS control located in the
chrominance processing block (see Fig.8).

= 4.43 or 3.58 MHz centre

0

8.5 RGB matrix

Y data and Cr, Cb data are converted after interpolation
into RGB data in accordance with CCIR-601
recommendation. The realized matrix equations consider
the digital quantization:

R = Y + 1.371 Cr
G=Y−0.336 Cb − 0.698 Cr
B = Y + 1.732 Cb

After dithering (noise shaping) the RGB data is fed to the
output interface within the VPO-bus output formatter.

8.6 VPO-bus (digital outputs)

The 16-bit VPO-bus transfers digital data from the output
interfaces to a feature box or a field memory, a digital
colour space converter (SAA7192 DCSC), a video
enhancement and digital-to-analog processor
(SAA7165 VEDA2) or a colour graphics board
(Targa-format) as a graphical user interface.

The output data formats are controlled via the I
OFTS0, OFTS1 and RGB888. Timing for the data stream
formats, 411 YUV (12-bit), 422 YUV (16-bit),
565 RGB (16-bit) and 888 RGB (24-bit) with an LLC2 data
rate, is achieved by marking each second positive rising
edge of the clock LLC in conjunction with CREF (clock
reference) (except RGB 888, see special application in
Fig.27). The higher output signals VPO15 to VPO8 in the
YUV format perform the digital luminance signal. The
lower output signals VPO7 to VPO0 in the YUV format are
the bits of the multiplexed colour difference signals (B−Y)
and (R−Y). The arrangement of the RGB 565 and
RGB 888 data stream bits on the VPO-bus is given in
Table 5.

The data stream format 422 YUV (the 8 higher output
signals VPO15 to VPO8) in LLC data rate fulfils the
CCIR-656 standard with its own timing reference code at
the start and end of each video data block.

A pixel in the format tables is the time required to transfer
a full set of samples. In the event of a 4 :2:2format two
luminance samples are transmitted in comparison to one
(B−Y) and one (R−Y) sample within a pixel. The time
frames are controlled by the HREF signal.

2

C-bus bits

1996 Oct 30 12

Philips Semiconductors Preliminary specification

Video Input Processor (VIP) SAA7111

Fast enable is achieved by setting input FEI to LOW.
The signal is used to control fast switching on the digital
VPO-bus. HIGH on this pin forces the YUV outputs to a
high-impedance state (see Figs 15 and 17).

The digitized analog PAL or NTSC signals AD1 (7 to 0)
and AD2 (7 to 0) are connected directly to the VPO-bus
via I2C-bit VIPB = 1.

AD1 (7 to 0) -> VPO (15 to 8) and
AD2 (7 to 0) ->VPO (7 to 0)

The selection of the analog input channels are controlled
via I2C-bus subaddress 02 MODE select.

8.7 Synchronization

The prefiltered luminance signal is fed to the
synchronization stage. Its bandwidth is reduced to 1 MHz
in a low-pass filter. The sync pulses are sliced and fed to
the phase detectors where they are compared with the
sub-divided clock frequency. The resulting output signal is
applied to the loop filter to accumulate all phase
deviations. Internal signals (e. g. HCL and HSY) are
generated in accordance with analog front-end
requirements. The output signals HS, VS, and PLIN are
locked to the timing reference, guaranteed between the
input signal and the HREF signal, as further improvements
to the circuit may change the total processing delay. It is
therefore not recommended to use them for applications
which require absolute timing accuracy on the input
signals. The loop filter signal drives an oscillator to
generate the line frequency control signal LFCO
(see Fig.8).

8.8 Clock generation circuit

The internal CGC generates all clock signals required for
the video input processor. The internal signal LFCO is a
digital-to-analog converted signal provided by the
horizontal PLL. It is the multiple of the line frequency
(6.75 MHz = 432 × f

). Internally the LFCO signal is

h

multiplied by a factor of 2 or 4 in the PLL circuit (including
phase detector, loop filtering, VCO and frequency divider)
to obtain the LLC and LLC2 output clock signals.
The rectangular output clocks have a 50% duty factor
(see Fig.22).

8.9 Power-on reset and CE input

A missing clock, insufficient digital or analog V

DDA0

supply
voltages (below 3.5 V) will initiate the reset sequence; all
outputs are forced to 3-state. The indicator output RES is
LOW for approximately 128 LLC after the internal reset
and can be applied to reset other circuits of the digital TV
system.

It is possible to force a reset by pulling the CE
(chip enable) to ground. After the rising edge of CE and
sufficient power supply voltage, the outputs LLC, LLC2,
CREF, RTCO, RTS0, RTS1, GPSW and SDA return from
3-state to active, while HREF, VREF, HS and VS remain in

2

3-state and have to be activated via I

C-bus programming

(see Table 4).

8.10 RTCO output

The real time control and status output signal contains
serial information about the actual system clock
(increment of the HPLL), subcarrier frequency [increment
and phase (via reset) of the FSC-PLL] and PAL sequence
bit. The signal can be used for various applications in
external circuits, e.g. in a digital encoder to achieve clean
encoding (see Fig.16).

8.11 The Line-21 text slicer

The text slicer block detects and acquires Line-21 Closed
Captioning data from a 525-line CVBS signal. Extended
data services on Line-21 Field 2 are also supported.
If valid data is detected the two data bytes are stored in two

2

C-bus registers. A parity check is also performed and the

I
result is stored in the MSB of the corresponding byte. A
third I2C-bus register is provided for data valid and data
ready flags. The two bits F1VAL and F2VAL indicate that
the input signal carries valid Closed Captioning data on the
corresponding fields. The data ready bits F1RDY and
F2RDY have to be evaluated if asynchronous I2C-bus
reading is used.

8.11.1 S

UGGESTIONS FOR I

DISPLAY SOFTWARE READING LINE

2

C-BUS INTERFACE OF THE

-21 DATA

There are two methods by which the software can acquire
the data;

1. Synchronous reading once per frame (or once per
field): It can use either the rising edge (Line-21 Field 1)
or both edges (Line-21 Field 1 or 2) of the ODD signal
(pin RTSO) to initiate an I2C-bus read transfer of the
three registers 1A, 1B and 1C.

2. Asynchronous reading: It can poll either the F1RDY bit
(Line-21 Field 1) or both F1RDY/F2RDY bits (Line-21
Field 1 or 2). After valid data has been read the
corresponding F*RDY bit is set to LOW until new data
has arrived. The polling frequency has to be slightly
higher than the frame or field frequency, respectively.

1996 Oct 30 13

Philips Semiconductors Preliminary specification

Video Input Processor (VIP) SAA7111

AOUT

(14) 23

AND

TEST

BUFFER

SELECTOR

ADC2

AOSL (1 : 0)

SWITCH

BYPASS

FILTER

ANTI-ALIAS

ANALOG

AMPLIFIER

DAC9

FUSE (1 : 0)

ANALOG

ADC1

SWITCH

BYPASS

FILTER

ANTI-ALIAS

DAC9

AMPLIFIER

VERTICAL

FUSE (1 : 0)

CONTROL

BLANKING

CONTROL

ANTI-ALIAS

GAIN

CONTROL

VBLNK

SVREF

VBSL 8 8

HOLDG

GAFIX

HSY

GLIMB

GLIMT

WPOFF

GAI20-GAI28

GAI10-GAI18

GUDL0-GUDL2

HLNRS

WIPA

SLTCA

AD1BYPAD2BYP

handbook, full pagewidth

CROSS MULTIPLEXER

UPTCV

Fig.6 Analog input processing.

987 (64)

n.c.

n.c.

n.c.

18 (9)

SSA1

V

14 (5)

SSA2

V

CLAMP

CIRCUIT

SWITCH

SOURCE

15 (6)

17 (8)

AI22

AI21

20 (11)

DDA1

V

16 (7)

DDA2

V

CLAMP

SOURCE

19 (10)

21 (12)

AI12

CIRCUIT

SWITCH

AI11

1996 Oct 30 14

CLAMP

CONTROL

MODE

CONTROL

HCL

MODE 0

MODE 1

MODE 2

ANALOG

CONTROL

22 (13)

SSS

V

CHRLUM

MGC655

The pin numbers given in parenthesis refer to the 64-pin package.

Philips Semiconductors Preliminary specification

Video Input Processor (VIP) SAA7111

AD1BYPAD2BYP

FEI

(52) 63

(42 to 51),

AND

CONTRAST,

BRIGHTNESS,

LOW-PASS

VPO

(9 : 0)VPO

45 to 50

53 to 62

(34 to 39),

AND 

OUTPUT

INTERFACE

FORMATTER

RGB

dithering

interpolation

RGB MATRIX

Y





CONTROL

SATURATION

PHASE

DEMOD.

AMPLITUDE

(15 : 10)



(31) 42

COMB

DIT CBR

UV

GAIN

CONTROL



AND Y-DELAY

DETECTOR

BURST GATE

ACCUMULATOR

HREF

GPSW

RTSE1

OFTS0

OFTS1

FILTERS

DCCF

COMPENSATION

BRIG

CODE

LOOP FILTER

FCTCCSTD 1

CONT

RTSE0

VIPB

RGB888

OEYC

SATN

VLOF

COLO

OEHV

FECO

RTCO

(60) 3

COMPO

VRLN



MGC645

Y

handbook, full pagewidth

CHBW0

CHBW1

INCREMENT

SUBCARRIER

CHRLUM

QUADRATURE

10 (1)

n.c.

DEMODULATOR

TEST

CONTROL

1 (58)

2 (59)

12 (3)

TDI

TCK

TRST

BLOCK

13 (4)

TMS

SUBCARRIER

11 (2)

TDO

GENERATION

(57,41,33,

25,18)

V

1996 Oct 30 15

AND

DIVIDER

GENERATION

HUEC

CONTROL

POWER-ON

32 (23)

68,52,44,

34,27



RES

DD1-5

INCS

CSTD 0

CLOCKS
CE

(56,40,32,26,19)

67,51,43,35,28



SS1-5

V

Fig.7 Chrominance circuit.

LUM

The pin numbers given in parenthesis refer to the 64-pin package.

Philips Semiconductors Preliminary specification

Video Input Processor (VIP) SAA7111

DDA0VSSA0

CREF

LLC

LLC2

CE

V

XTALI

XTAL

(22) 31

CLOCKS

(21)30

(20) 29

CLOCK

GENERATOR

LINE-LOCKED

(24)33

(16) 25

(15) 24

CLOCK

CIRCUIT

GENERATION

(54) 65

(55) 66

CLOCK

CRYSTAL

GENERATOR

MGC654

CLOCK CIRCUIT

DAC6

INCS

APER0

APER1

Y

AND

ADDING

STAGE

WEIGHTING

VBLB

MATCHING

AMPLIFIER

VBLB

PHASE

FINE

PHASE

DETECTOR

COARSE

DETECTOR

AUFD

HSB

HPLL

HSS

VTRC

VTRC

EXFIL

STTC

HLCK

FSEL

VTRC

TIME

DISCRETE

OSCILLATOR 2

2

LOOP FILTER

(28)

(27)

COUNTER

39

RTS1

38

HS

handbook, full pagewidth

BPSS0

BPSS1

FILTER

VARIABLE

BAND-PASS

PREF

SYNC SLICER

LUMINANCE CIRCUIT

TRAP

CHROMINANCE

LUM

PREFILTER

BYPS

VBLB

PREF

SYNC

PREFILTER

TEXT

LINE 21

1996 Oct 30 16

FIDT

VNOI0

VNOI1

VTRC

SYNCHRONIZATION CIRCUIT

BYTE1

SLICER

BYTE2

STATUS

2

I C BUS CONTROL

VERTICAL

PROCESSOR

2

I C-BUS

INTERFACE

64 (53)

GPSW

(17)
(29)

(30)

(62)

(63)

(61)

26

VREF

40

RTS0

41

VS

5

SDASCLIICSA

6

4

Fig.8 Luminance and sync processing.

The pin numbers given in parenthesis refer to the 64-pin package.

Philips Semiconductors Preliminary specification

Video Input Processor (VIP) SAA7111

9 GAIN CHARTS

handbook, full pagewidth

handbook, halfpage

7.5

factor

dB

5.5

3.5

bit [8] = 1

1.5

−0.5

−2.5

−4.5

0

= 20 x log10 gain =

dB

i > 256

bit [8] = 0

= 20 x log10 gain =

factor

dB

256 512

gain value (i)

Fig.9 Amplifier curve.

ANALOG INPUT

(

512

768 − i

(

i < 256

(

MGC648

257 + i

512

(

ADC

NO BLANKING ACTIVE

10 10

10

CLL

+ CLAMP − CLAMP

WIPE = white peak level (254); SBOT = sync bottom level (1); CLL = clamp level [60 Y (128 C)];
HSY = horizontal sync pulse; HCL = horizontal clamp pulse.

10

VBLK

GAIN -><- CLAMP

HCL HSY

01 10

SBOT

NO CLAMP

+ GAIN − GAIN

Fig.10 Clamp and gain flow.

fast − GAIN

WIPE

slow + GAIN

MGC647

1996 Oct 30 17

Philips Semiconductors Preliminary specification

Video Input Processor (VIP) SAA7111

handbook, full pagewidth

NO ACTION

0

1

ANTI-ALIAS FILTER

0

1

<4

0

>248

ANALOG INPUT

AMPLIFIER

ADC

1

VBLK

1

HOLDG

1

>254

X = 0

gain

8

0

0

1

X

1

1

<1

0

DAC

LUMA/CHROMA DECODER

0

0

HSY

1

>254

X = 1

9

0

+1/F

STOP

X = system variable; Y = AGV − FGVI > GUDL; VBLK = vertical blanking pulse;
HSY = horizontal sync pulse; AGV = actual gain value; FGV = frozen gain value.

−

1/LLC2

+1/L

GAIN ACCUMULATOR (18 BITS)

ACTUAL GAIN VALUE 9-BIT (AGV) [−6/+6 dB]

1

AGV

Fig.11 Gain flow chart.

+1/LLC2 −1/LLC2

0

X

1

HSY

1

UPDATE

GAIN VALUE 9-BIT

+/− 0

0

0

Y

FGV

MGC652

1996 Oct 30 18

Philips Semiconductors Preliminary specification

Video Input Processor (VIP) SAA7111

10 LIMITING VALUES

In accordance with the Absolute Maximum Rating System (IEC 134).

SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT

V

DDD

V

DDA

V

diff

T

stg

T

amb

T

amb(bias)

V

esd

Note

1. Human body model: equivalent to discharging a 100 pF capacitor through a 1.5 kΩ resistor.

11 CHARACTERISTICS

= 4.5 to 5.5 V; V

V

DDD

digital supply voltage −0.5 +6.5 V
analog supply voltage −0.5 +6.5 V
voltage difference between V

SSAall

and V

SSall

− 100 mV
storage temperature −65 +150 °C
operating ambient temperature 0 +70 °C
operating ambient temperature under bias −10 +80 °C
electrostatic discharge all pins note 1 −2000 +2000 V

= 4.75 to 5.25 V; T

DDA

=25°C; unless otherwise specified.

amb

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

Supplies

V
I

DDD

P
V
I

DDA

P
P

DDD

D
DDA

A
A+D

digital supply voltage 4.5 5.0 5.5 V
digital supply current 100 130 160 mA
digital power 0.45 0.65 0.88 W
analog supply voltage 4.75 5.0 5.25 V
analog supply current 60 70 80 mA
analog power 0.32 0.35 0.38 W
analog and digital power 0.77 1.0 1.26 W

Analog part

I

clamp

V

i(p-p)

|Z

| input impedance clamping current off 200 −− kΩ

i

C

i

α

cs

clamping current VI= 1.25 V DC − 2 −µA
input voltage (peak-to-peak

value), AC coupling required

coupling
capacitor = 10 nF; note 1

0.55 1.0 1.5 V

input capacitance −− 10 pF
channel crosstalk fi= 5 MHz −−50 − dB

Analog-to-digital converters

B bandwidth at −3dB − 15 − MHz
φ

diff

differential phase (amplifier

− 2 − deg

plus anti-alias filter = bypass)

G

diff

differential gain (amplifier plus

− 2 − %

anti-alias filter = bypass)

f

ADC

ADC clock frequency 11 − 16 MHz

DLE DC differential linearity error − 0.5 − LSB
ILE DC integral linearity error − 1 − LSB

1996 Oct 30 19

Philips Semiconductors Preliminary specification

Video Input Processor (VIP) SAA7111

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

Digital inputs

V

IL

V

IH

V

IL(xtalI)

V

IH(xtalI)

V

ILn

V

IHn

I

LI

C

i(I/O)

C

i(n)

LOW level input voltage pins
SDA and SCL

HIGH level input voltage pins
SDA and SCL

LOW level CMOS input
voltage pin XTALI

HIGH level CMOS input
voltage pin XTALI

LOW level input voltage all
other inputs

HIGH level input voltage all
other inputs

input leakage current −− 1 µA
input capacitance inputs and outputs at

high-impedance

input capacitance all other
inputs

−0.5 − +1.5 V

0.7V

−− 0.3V

0.7V

− V

DDD

−− V

DDD

DDD

+ 0.5 V

DDD

V

−0.5 − +0.8 V

2.0 − V

DDD

+ 0.5 V

−− 8pF

−− 8pF

Digital outputs

V

OL

LOW level output voltage pins
SDA and SCL

V

OL

V

OH

V

OL(clk)

LOW level output voltage note 2 0 − 0.6 V
HIGH level output voltage note 2 2.4 − V
LOW level output voltage for

clocks

V

OH(clk)

HIGH level output voltage for
clocks

FEI input timing

t

SU;DAT

t

HD;DAT

input data set-up time 13 −− ns
input data hold time 3 −− ns

Data and control output timing

C

L

t

OHD;DAT

t

PD

t

PDZ

output load capacitance 15 − 50 pF
output hold time CL=15pF 5 −− ns
propagation delay CL=40pF −− 21 ns
propagation delay to 3-state −− 21 ns

SDA/SCL at 3 mA sink
current

−− 0.4 V

DDD

−0.5 − +0.6 V

2.6 − V

DDD

+ 0.5 V

V

1996 Oct 30 20