Philips SAA5355 Datasheet

INTEGRATED CIRCUITS

DATA SH EET

SAA5355

Single-chip colour CRT controller
(FTFROM)

Product specification
File under Integrated Circuits, IC02

March 1986

Philips Semiconductors Product specification

Single-chip colour CRT controller

SAA5355

(FTFROM)

GENERAL DESCRIPTION

The SAA5355 FTFROM (Five-Two-Five-ROM) is a single-chip VLSI NMOS crt controller capable of handling the display
functions required for a 525-line, level-3 videotex decoder. Only minimal hardware is required to produce a videotex
terminal using FTFROM  the simplest configuration needs just a microcontroller and 4 Kbytes of display memory.

Features

• Minimal additional hardware required

• Screen formats of 40/80 character by 1-to-25 row display

• 512 alphanumeric or graphical characters on-chip or extendable off-chip

• Serial attribute storage (STACK) and parallel attribute storage

• Dynamically redefinable character (DRCS) capability over full field

• Interfaces with 8/16-bit microprocessors with optional direct memory access

• On-chip scroll map minimizes data to be transferred when scrolling

• 32 on-screen colours redefinable from a palette of 4096

• Three on-chip digital-to-analogue converters which compensate for crt non-linearity

• Memory interface capable of supporting multi-page terminals. FTFROM can access up to 128 Kbytes of display

memory

• Programmable cursor

• Programmable local status row

• Three synchronization modes:

stand-alone built-in oscillator operating with an external 6,041957 MHz crystal
simple slave directly synchronized from the source of text composite sync
phase-locked slave indirect synchronization allows picture-in-text displays (e.g. VCR/VLP video with text overlay)

• On-chip timing with composite sync output

• Zoom feature which allows the height of any group of rows to be increased to enhance legibility

PACKAGE OUTLINE

40-lead DIL; plastic (SOT129); SOT 129-1; 1996 November 18.

March 1986 2

Philips Semiconductors Product specification

Single-chip colour CRT controller
(FTFROM)

SAA5355

March 1986 3

Fig.1 Block diagram.

Philips Semiconductors Product specification

Single-chip colour CRT controller

SAA5355

(FTFROM)

PINNING

1V
2
3

4 to 19 A16 to A1/

20 V
21 REF Analogue reference input.
22 B

24 R
25

26

27 CLKO 12 MHz clock output for hard-copy dot synchronization (referenced to output

28 SAND Sandcastle feedback output for SAA5230 teletext video processor or other circuit.

29 F1/F6 1,00699 MHz or 6,041957 MHz output.
30 F6 6,041957 MHz clock input (e.g. from SAA5230). Internal a.c. coupling is provided.
31 VCS/OSCO Video composite sync input (e.g. from SAA5230) for phase reference of vertical

32
33

34
35
36
37
38
39 R/
40 V

SS(1)

BUFEN Buffer enable input to the 8-bit link-through buffer.
RE Register enable input. This enables A1 to A6 and UDS as inputs,

D15 to D0

SS(2)

VDS Switching output for dot, screen (row), box and window video data; for use when

OD Output disable causing R, G, B and VDS outputs to go to high-impedance state.

TCS Text composite sync input/output depending on master/slave status.
FS/DDA Field sync pulse output or defined-display-area flag output (both referenced to

UDS Upper data strobe input/output.
LDS Lower data strobe output.
DTACK Data transfer acknowledge (open drain output).
BR Bus request to microprocessor (open drain output).
AS Address strobe output to external address latches.

W(S/R) Read/write input/output. Also serves as send/receive for the link-through buffer.

DD

Ground (0 V).

and D8 to D15 as input/outputs.
Multiplexed address and data bus input/outputs. These pins also function as the

8-bit link-through buffer.
Ground (0 V).

Analogue outputs (signals are gamma-corrected).23 G

video signal is present (e.g. from tv , VLP, alpha + photographic layer). This output
is LOW for tv display and HIGH for text and will interface directly with a number of
colour decoder ICs (e.g. TDA3563, TDA3562A).

Can be used at dot-rate.

dots).

Used when the display must be locked to the video source (e.g. VLP).
The phase-lock part of the sandcastle waveform can be disabled to allow
free-running of the SAA5230 phase-locked loop.

display timing when locking to a video source (e.g. VLP) or, in stand-alone sync
mode, output from internal oscillator circuit (fixed frequency).

output dots).

Positive supply voltage (+ 5 V).

March 1986 4

Philips Semiconductors Product specification

Single-chip colour CRT controller
(FTFROM)

SAA5355

Fig.2 Pinning diagram.

RATINGS

Limiting values in accordance with the Absolute Maximum System (IEC 134)

Supply voltage range (pin 40) V
Maximum input voltage (except F6,
Maximum input voltage (F6,

TCS) V

TCS, REF) V

Maximum input voltage (REF) V
Maximum output voltage V
Maximum output current I
Operating ambient temperature range T
Storage temperature range T

Outputs other than CLKO, OSCO, R, G, B, and

VDS are short-circuit protected.

March 1986 5

DD
Imax
lmax
REF
Omax

Omax

amb
stg

−0,3 to + 7,5 V

−0,3 to + 7,5 V

−0,3 to + 10,0 V

−0,3 to + 3,0 V

−0,3 to + 7,5 V

10 mA

−20 to + 70 °C

−55 to + 125 °C

Philips Semiconductors Product specification

Single-chip colour CRT controller

SAA5355

(FTFROM)

CHARACTERISTICS

= 5 V ± 5%; VSS = 0 V; T

V

DD

PARAMETER SYMBOL MIN. TYP. MAX. UNIT

SUPPLY

Supply voltage (pin 40) V
Supply current (pin 40) I

INPUTS
F6 (note 1)

Slave modes

(Fig.3)
Input voltage (peak-to-peak value) V
Input peaks relative to

50% duty factor ±V

Input leakage current at

V

= 0 to 10 V; T

I

= 25 °CI

amb

Input capacitance C

Stand-alone mode

(Fig.4)
Series capacitance of crystal C
Parallel capacitance of crystal C
Resonance resistance of crystal R
Gain of circuit G −−note 2 V/V

= −20 to + 70 °C; unless otherwise specified.

amb

DD

DD

I (p-p)

P

LI

I

1
0
r

4,75 5,0 5,25 V

−−350 mA

1,0 − 7,0 V

0,2 − 3,5 V

−−20 µA

−−12 pF

− 28 − fF

− 7,1 − pF

−−60 Ω

BUFEN, RE, OD

Input voltage LOW V
Input voltage HIGH V

IL
IH

0 − 0,8 V
2,0 − 6,5 V

Input current at

V

= 0 to VDD+ 0,3 V; T

I

Input capacitance C

= 25 °CI

amb

I

I

−10 −+10 µA

−−7pF

REF (Fig.5)
Input voltage V

REF

0 1 to 2 2,7 V

Resistance (pin 21 to pin 20) with

REF supply and R, G, B outputs OFF R

REF

− 125 −Ω

OUTPUTS
SAND

Output voltage high level at

= 0 to −10 µAV

I

O

OH

4,2 − V

Output voltage intermediate level at

I

= −10 to +10 µAV

O

OI

1,3 2,0 2,7 V

Output voltage low level at

IOH = 0,2 mA V

Load capacitance C

OL
L

0 − 0,2 V

−−130 pF

DD

V

March 1986 6

Philips Semiconductors Product specification

Single-chip colour CRT controller

SAA5355

(FTFROM)

PARAMETER SYMBOL MIN. TYP. MAX. UNIT

F1/F6, CLKO, DDA/FS

Output voltage HIGH at

IOH = −200 µAV

Output voltage LOW at I

= 3,2 mA V

OL

Load capacitance C

OH
OL
L

LDS, AS

Output voltage HIGH at

IOH= −200 µAV

Output voltage LOW at I

= 3,2 mA V

OL

Load capacitance C

OH
OL
L

DTACK, BR (open drain outputs)
Output voltage LOW at I

Load capacitance C
Capacitance (OFF state) C

= 3,2 mA V

OL

OL
L
OFF

R, G, B (note 3)
Output voltage HIGH (note 4) at

= −100 µA; V

I

OH

Output voltage LOW at I
Output resistance during line blanking R
Output capacitance (OFF state) C

= 2,7 V V

REF

= 2 mA V

OL

OH
OL
OBL
OFF

Output leakage current (OFF state)

at VI = 0 to VDD+ 0,3 V;
T

= 25 °CI

amb

OFF

VDS

Output voltage HIGH at I
Output voltage LOW at I
Output voltage LOW at I

= −250 µAV

OH

= 2 mA V

OL

= 1 mA V

OL

OH
OL
OL

Output leakage current (OFF state)

at V

= 0 to VDD+ 0,3 V;

I

= 25 °CI

T

amb

OFF

INPUT/OUTPUTS

2,4 − V

DD

0 − 0,4 V

−−50 pF

2,4 − V

DD

0 − 0,4 V

−−200 pF

0 − 0,4 V

−−150 pF

−−7pF

2,4 −−V

−−0,4 V

−−150 Ω

−−12 pF

−10 −+10 µA

2,4 − V

DD

0 − 0,4 V
0 − 0,2 V

−10 −+10 µA

V

V

V

VCS/OSCO

Input voltage HIGH V
Input voltage LOW V
Input current (output OFF) at

VI = 0 to VDD+ 0,3 V;

= 25 °CI

T

amb

Input capacitance C
Load capacitance C

March 1986 7

IH
IL

I

I
L

2,0 − 6,0 V
0 − 0,8 V

−10 −+10 µA

−−10 pF

−−50 pF

Philips Semiconductors Product specification

Single-chip colour CRT controller
(FTFROM)

PARAMETER SYMBOL MIN. TYP. MAX. UNIT

TCS

Input voltage HIGH V
Input voltage LOW V

IH
IL

Input current at

V

= 0 to VDD+ 0,3 V;

I

=25°CI

T

amb

Input capacitance C

I

I

Output voltage HIGH at

I

= −200 to 100 µAV

OH

Output voltage LOW at V

= 3,2 mA V

OL

Load capacitance C

A1/D0 to A16/D15,

UDS, R/W

Input voltage LOW V
Input voltage HIGH V

OH
OL
L

IL
IH

Input current at

V

= 0 to VDD+ 0,3 V;

I

T

=25°CI

amb

Input capacitance C
Output voltage HIGH at I
Output voltage LOW at I

= −200 µAV

OH

= 3,2 mA V

OL

Load capacitance C

I

I
OH
OL
L

TIMING (note 5)

3,5 − 10,0 V
0 − 1,5 V

−10 −+10 µA

−−10 pF

2,4 − 6,0 V
0 − 0,4 V

−−50 pF

0 − 0,8 V
2,0 − 6,0 V

−10 −+10 µA

−−10 pF

2,4 − V
0 − 0,4 V

−−200 pF

SAA5355

DD

V

F6 (Fig.3)
Rise and fall times t

Frequency f

March 1986 8

r
F6

, t

f

10 − 80 ns
5,9 − 6,1 MHz

Philips Semiconductors Product specification

Single-chip colour CRT controller
(FTFROM)

PARAMETER SYMBOL MIN. TYP. MAX. UNIT

CLKO, F1/F6, R, G, B, VDS
FS/DDA, OD (notes 6, 7 and Fig.6)

CLKO HIGH time t
CLKO LOW time t
CLKO rise and fall times t

CLKO HIGH to R, G, B,
R, G, B,

VDS valid to CLKO rise t
CLKO HIGH to R, G, B,
CLKO HIGH to R, G, B,

after

OD fall t
Skew between outputs R, G, B,
R, G, B,

VDS rise and fall times tVr, t

CLKO HIGH to R, G, B,

after

OD rise t

CLKO HIGH to

FS/DDA change t
FS/DDA valid to CLKO rise t
F1 HIGH time (note 8) t
F1 LOW time (note 8) t
F6 HIGH time t
F6 LOW time t
OD to CLKO rise set-up t
OD to CLKO HIGH hold t

MEMORY ACCESS TIMING

(notes 9, 10 and Fig.7)

VDS change t

VDS valid t
VDS floating

VDS t

VDS active

CLKH
CLKL
CLKr

t

CLKf
VCH
VOC
COV

FOD
VS

UOD
DCH
DOC
F1H
F1L
F6H
F6L
ODS
ODH

SAA5355

25 −−ns
15 −−ns

−−10 ns

10 −−ns
10 −−ns

−−60 ns

0 − 30 ns

−−20 ns

Vf

−−30 ns

0 − 60 ns
10 − 60 ns
5 −−ns

− 500 − ns

− 500 − ns

− 83 − ns

− 83 − ns

−−45 ns

−−0ns

UDS, LDS, AS

Cycle time t
UDS HIGH to bus-active for address output t
Address valid set-up to
Address valid hold from
Address float to

UDS fall t

AS fall t

AS LOW t

AS LOW to UDS fall delay t
UDS, LDS HIGH time t
UDS, LDS LOW time t
AS HIGH time t
AS LOW time t

March 1986 9

cyc
SAA
ASU
ASH
AFS
ATD
HDS
LDS
HAS
LAS

− 500 − ns
75 −−ns
20 −−ns
20 −−ns
0 −−ns
50 −−ns
220 −−ns
200 −−ns
125 −−ns
320 −−ns

Philips Semiconductors Product specification

Single-chip colour CRT controller
(FTFROM)

PARAMETER SYMBOL MIN. TYP. MAX. UNIT

AS LOW to UDS HIGH t
Data valid set-up to
Data valid hold from
UDS HIGH to AS rise delay t
AS LOW to data valid t

Link-through buffers

(notes 9, 10 and Fig.8)
BUFEN LOW to output valid t
Link-through delay time t
Input data float prior to direction change t
Output float after direction change t
Output float after

Microprocessor READ from FTFROM

(Fig.9)
R/

W HIGH set-up to UDS fall t
UDS LOW to returned-data access time t
RE LOW to returned data access time t
Data valid to
DTACK LOW to UDS rise t
UDS HIGH to DTACK rise t
UDS HIGH to address hold t
UDS HIGH to data hold t
UDS HIGH to RE rise t
UDS HIGH to R/W fall t
UDS LOW to DTACK LOW t
Address valid to

UDS rise t

UDS HIGH t

BUFEN HIGH t

DTACK LOW delay t

UDS fall t

AUH
DSU
DSH
UAS
AFA

BEA
LTD
IFR
OFR
BED

RUD
UDA
REA
DTL
DLU
DTR
DSA
DSH
SRE
UDR
DSD
AUL

SAA5355

305 −−ns
30 −−ns
0 −−ns
0 − 15 ns

−−275 ns

−−100 ns

−−85 ns
0 −−ns

−−60 ns

−−60 ns

0 −−ns

−−210 ns

−−210 ns

40 −−ns
0 −−ns
0 − 75 ns
10 −−ns
10 −−ns
10 −−ns
0 −−ns
250 − 350 ns
0 −−ns

March 1986 10