Philips SAA5288 Datasheet

INTEGRATED CIRCUITS

DATA SH EET

SAA5288

TV microcontroller with full screen On Screen Display (OSD)

Preliminary speciﬁcation File under Integrated Circuits, IC02

1997 Jun 24

Philips Semiconductors Preliminary speciﬁcation

TV microcontroller with full screen On Screen Display (OSD)

CONTENTS

1 FEATURES

1.1 General

1.2 Microcontroller

1.3 Display 2 GENERAL DESCRIPTION 3 QUICK REFERENCE DATA 4 ORDERING INFORMATION 5 BLOCK DIAGRAM 6 PINNING INFORMATION

6.1 Pinning

6.2 Pin description 7 FUNCTIONAL DESCRIPTION

7.1 Microcontroller

7.2 80C51 features not supported

7.2.1 Interrupt priority

7.2.2 Off-chip memory

7.2.3 Idle and Power-down modes

7.2.4 UART function

7.3 Additional features

7.3.1 Interrupts

7.3.2 Bit Level I2C-bus Interface

7.3.3 Byte Level I2C-bus Interface

7.3.4 LED support

7.3.5 6-bit PWM DACs

7.3.6 14-bit PWM DAC

7.3.7 Software ADC

7.4 Microcontroller Interfacing

7.4.1 Special Function Register map

7.4.2 Special Function Registers bit description

7.5 The display

7.5.1 Introduction

7.5.2 Character matrix

7.5.3 Page attributes

7.5.4 East/west selection

7.5.5 National option characters

7.6 The twist attribute

7.6.1 On screen display symbols

7.6.2 Language group identification

7.6.3 525-line operation

7.6.4 Control characters

7.6.5 Display modes

7.7 On Screen Display boxes

7.8 Screen colour

SAA5288

7.9 Cursor

7.10 Other display features

7.11 Display timing

7.12 Horizontal timing

7.13 Vertical timing

7.14 Display position

7.15 Clock generator 8 CHARACTER SETS

8.1 Pan-European

8.2 Russian

8.3 Greek/Turkish

8.4 Arabic/English/French

8.5 Thai

8.6 Arabic/Hebrew 9 LIMITING VALUES 10 CHARACTERISTICS 11 CHARACTERISTICS FOR THE I2C-BUS

INTERFACE 12 QUALITY SPECIFICATIONS 13 APPLICATION INFORMATION 14 EMC GUIDELINES 15 PACKAGE OUTLINE 16 SOLDERING

16.1 Introduction

16.2 Soldering by dipping or by wave

16.3 Repairing soldered joints 17 DEFINITIONS 18 LIFE SUPPORT APPLICATIONS 19 PURCHASE OF PHILIPS I2C COMPONENTS

1997 Jun 24 2

Philips Semiconductors Preliminary speciﬁcation

TV microcontroller with full screen On Screen Display (OSD)

1 FEATURES

1.1 General

• On-chip TV control tuning

• Hardware and software compatible with SAA5290,

SAA5291 and SAA5296

• Single +5 V power supply

• RGB interface to standard decoder ICs, push-pull output

drive

• SDIP52 package

• Single crystal oscillator for display and microcontroller.

1.2 Microcontroller

• 80C51 microcontroller core

• 16 kbyte mask programmed ROM

• 256 bytes of microcontroller RAM

• Eight 6-bit Pulse Width Modulator (PWM) outputs for

control of TV analog signals

• One 14-bit PWM for Voltage Synthesis tuner control

• Four 8-bit Analog-to-Digital Converters (ADCs)

• 2 high current open-drain outputs for directly driving

LED’s etc.

• Switchable bit or byte-oriented I

1.3 Display

• Single page (1024 × 8) on-board On Screen Display (OSD) memory

• Double size width and height capability for OSD

• Enhanced display features including meshing,

shadowing and additional display attributes

C-bus interface.

SAA5288

• 260 characters in mask programmed ROM

• Display clock derived internally to reduce peripheral

components to a minimum

• Automatic FRAME output control with manual override

• Standby mode for display hardware

• 525-line and 625-line display

• 12 × 10 character matrix

• Stable Display via slave synchronization to Horizontal

Sync and Vertical Sync.

2 GENERAL DESCRIPTION

The SAA5288 is a microcontroller for use in televisions with an OSD generator compatible with the Economy Teletext/TV microcontroller family (SAA5290, SAA5291, SAA5296 etc.). TV control facilities are provided by an on-chip industry standard 80C51 microcontroller and a 1 kbyte DRAM is included for OSD memory.

Hardware and software compatibility with the Economy Teletext/TV microcontroller family minimizes the changes required to develop a TV control function for areas where teletext is not broadcast.

The device cannot acquire Teletext but is based on a Teletext device. Therefore, throughout this document references are made to Teletext especially when describing the Display/OSD section. The Display/OSD section is fully compatible with a Teletext display and has all the features associated with Teletext (i.e. double height/width, flash, teletext boxes, graphics, etc.). The Display section is described with reference to Teletext to allow software compatibility with the Economy Teletext/TV microcontroller family.

3 QUICK REFERENCE DATA

SYMBOL PARAMETER MIN. TYP. MAX. UNIT

DDM

DDA

DDT

xtal

amb

supply voltage (all supplies) 4.5 5.0 5.5 V microcontroller supply current − 15 30 mA analogue supply current − 815mA display supply current − 15 30 mA crystal frequency − 12 − MHz operating ambient temperature −20 − +70

1997 Jun 24 3

Philips Semiconductors Preliminary speciﬁcation

TV microcontroller with full screen

SAA5288

On Screen Display (OSD)

4 ORDERING INFORMATION

TYPE NUMBER

NAME DESCRIPTION VERSION

SAA5288PS/nnn SDIP52 plastic shrink dual in-line package; 52 leads (600 mil) SOT247-1

5 BLOCK DIAGRAM

handbook, full pagewidth

DDA

DDD

DDMVSSD

XTALINV

XTALOUT OSCGND

OSCILLATOR

PACKAGE

PAGE

RAM

DISPLAY

TIMING

R, G, B, VDS,

COR

VSYNC HSYNC FRAME

RESET

8051 CPU

data

address

interrupt

PORT 1

I2C-BUS

TIMER/

COUNTER

16 KBYTE

ROM

256 BYTE

RAM

ADC

PORT 0

Fig.1 Block diagram.

TEXT

INTERFACE

PORT 3

P3.0 to P3.7P0.0 to P0.7P1.0 to P1.7

PWM

PORT 2

MGL121

P2.0 to P2.7

1997 Jun 24 4

Philips Semiconductors Preliminary speciﬁcation

TV microcontroller with full screen On Screen Display (OSD)

6 PINNING INFORMATION

6.1 Pinning

handbook, halfpage

P2.0/TPWM P2.1/PWM0 P2.2/PWM1 P2.3/PWM2 P2.4/PWM3 P2.5/PWM4 P2.6/PWM5 P2.7/PWM6

P3.0/ADC0 P3.1/ADC1 P3.2/ADC2 P3.3/ADC3

SSD P0.0

P0.1 P0.2 P0.3 P0.4 P0.5 P0.6 P0.7

SSD

IREF

i.c. i.c. i.c.

1 2 3 4 5 6 7 8

9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26

SAA5288

MGL114

P1.5

P1.4

P1.7/SDA

P1.6/SCL

P1.3/T1

P1.2/INT0

P1.1/T0

P1.0/INT

DDM

RESET

XTALOUT

XTALIN

OSCGND

DDD

DDA

VSYNC

HSYNC

VDS

RGBREF

P3.4/PWM7

COR

SSD

FRAME

SAA5288

Fig.2 Pin configuration.

1997 Jun 24 5

Philips Semiconductors Preliminary speciﬁcation

TV microcontroller with full screen On Screen Display (OSD)

6.2 Pin description Table 1 SDIP52 package

SYMBOL PIN DESCRIPTION

P2.0/TPWM 1 Port 2. 8-bit open-drain bidirectional port with alternative functions. P2.1/PWM0 2 P2.2/PWM1 3 P2.3/PWM2 4 P2.4/PWM3 5 P2.5/PWM4 6 P2.6/PWM5 7 P2.7/PWM6 8 P3.0/ADC0 9 Port 3. 8-bit open-drain bidirectional port with alternative functions. P3.1/ADC1 10 P3.2/ADC2 11 P3.3/ADC3 12 P3.4/PWM7 30 V

SSD

P0.0 14 Port 0. 8-bit open-drain bidirectional port. P0.1 15 P0.2 16 P0.3 17 P0.4 18 P0.5 19 P0.6 20 P0.7 21 V

SSD

i.c. 23 Internally connected; this pin should be connected to digital ground. i.c. 24 Internally connected; this pin should be connected to digital ground. i.c. 25 Internally connected; this pin should be connected to digital ground. IREF 26 Reference current input for analog current generator, connected to V

13 Digital ground

22 Digital ground.

P2.0/TPWM is the output for the 14-bit high precision PWM. P2.1/PWM0 to P2.7/PWM6 are the outputs for the 6-bit PWMs 0 to 6.

P3.0/ADC0 to P3.3/ADC3 are the inputs for the software ADC facility. P3.4/PWM7 is the output for the 6-bit PWM7.

P0.5 and P0.6 have 10 mA current sinking capability for direct drive of LEDs.

resistor.

SAA5288

via a 27 kΩ

SSA

1997 Jun 24 6

Philips Semiconductors Preliminary speciﬁcation

TV microcontroller with full screen

SAA5288

On Screen Display (OSD)

SYMBOL PIN DESCRIPTION

FRAME 27 De-interlace output synchronised with the VSYNC pulse to produce a non-interlaced

display by adjustment of the vertical deﬂection circuits.

SSD

COR 29 Open-drain, active LOW output which allows selective contrast reduction of the TV

RGBREF 31 DC input voltage to deﬁne the output HIGH level on the RGB pins. B 32 Pixel rate output of the BLUE colour information. G 33 Pixel rate output of the GREEN colour information. R 34 Pixel rate output of the RED colour information. VDS 35 Video/data switch push-pull output for dot rate fast blanking. HSYNC 36 Schmitt trigger input for a TTL level version of the horizontal sync pulse; the polarity

VSYNC 37 Schmitt trigger input for a TTL level version of the vertical sync pulse; the polarity of

DDA

DDD

OSCGND 40 Crystal oscillator ground. XTALIN 41 12 MHz crystal oscillator input. XTALOUT 42 12 MHz crystal oscillator output. RESET 43 If the reset input is HIGH for at least 3 machine cycles (36 oscillator periods) while

DDM

P1.0/INT1 45 Port 1. 8-bit open-drain bidirectional port with alternative functions. P1.1/T0 46 P1.2/INT0 47 P1.3/INT1 48 P1.6/SCL 49 P1.7/SDA 50 P1.4 51 P1.5 52

28 Internally connected; this pin should be connected to digital ground.

picture to enhance a mixed mode display.

of this pulse is programmable by register bit TXT1.H POLARITY.

this pulse is programmable by register bit TXT1.V POLARITY. 38 +5 V display power supply. 39 +5 V display power supply.

the oscillator is running, the device is reset; this pin should be connected to V

a 2.2 µF capacitor. 44 +5 V microcontroller power supply.

P1.0/INT1 is external interrupt 1, can be triggered on the rising/falling edge of pulse.

P1.1/T0 is the counter/timer 0.

P1.2/INT0 is the external interrupt 0.

P1.3/T1 is the counter/timer 1.

P1.7/SDA is the serial data port for the I

C-bus.

P1.6/SCL is the serial clock input for the I2C-bus.

DDM

via

1997 Jun 24 7

Philips Semiconductors Preliminary speciﬁcation

TV microcontroller with full screen On Screen Display (OSD)

7 FUNCTIONAL DESCRIPTION

7.1 Microcontroller

The functionality of the microcontroller used with this family is described with reference to the industry-standard 80C51 microcontroller. A full description of its functionality can be found in

Data Handbook IC20”

the changes made to this family fall into two categories:

• Features not supported by the SAA5288

• Features found on the SAA5288 but not supported by

the 80C51.

7.2 80C51 features not supported

7.2.1 INTERRUPT PRIORITY The IP SFR is not implemented and all interrupts are

treated with the same priority level. The normal priority of interrupts is maintained within the level.

Table 2 Interrupts and vector address

INTERRUPT SOURCE

Reset 000 External INT0 003 Timer 0 00B External INT1 013 Timer 1 01B

Byte I

C-bus 02B

Bit I

C-bus 053

7.2.2 O The SAA5288 does not support the use of off-chip

program memory or off-chip data memory.

“80C51-Based; 8-bit Microcontrollers,

. Using the 80C51 as a reference,

VECTOR ADDRESS

(HEX)

FF-CHIP MEMORY

SAA5288

7.3 Additional features

The following features are provided in addition to the standard 80C51 features.

7.3.1 I The external INT1 interrupt is modified to generate an

interrupt on both the rising and falling edges of the INT1 pin, when EX1 bit is set. This facility allows for software pulse-width measurement for handling of a remote control.

7.3.2 B For reasons of compatibility with the SAA5290, SAA5291,

SAA5291A and SAA5491 all contain a bit level serial I/O which supports the I2C-bus. P1.6/SCL and P1.7/SDA are the serial I/O pins. These two pins meet the I2C-bus specification concerning the input levels and output drive capability see

specifications)”

open-drain output configuration. All the four following modes of the I2C-bus are supported.

• Master transmitter

• Master receiver

• Slave transmitter

• Slave receiver.

Three SFRs support the function of the bit-level I2C-bus hardware: S1INT, S1BIT and S1SCS and are enabled by setting register bit TXT8.I2C SELECT to logic 0.

7.3.3 B The byte level serial I/O supports the I2C-bus protocol.

P1.6/SCL and P1.7/SDA are the serial I/O pins. These two pins meet the I2C-bus specification concerning the input levels and output drive capability. Consequently, these two pins have an open-drain output configuration.

NTERRUPTS

IT LEVEL I

C-BUS INTERFACE

“The I2C-bus and how to use it (including

. Consequently, these two pins have an

YTE LEVEL I

C-BUS INTERFACE

7.2.3 I

DLE AND POWER-DOWN MODES

Idle and Power-down modes are not supported. Consequently, the respective bits in PCON are not available.

7.2.4 UART

FUNCTION

The 80C51 UART is not available. As a consequence the SCON and SBUF SFRs are removed and the ES bit in the IE SFR is unavailable.

1997 Jun 24 8

The byte level I2C-bus serial port is identical to the I2C-bus serial port on the 8xC552. The operation of the subsystem is described in detail in the 8xC552 data sheet described in

“80C51-Based; 8-bit Microcontrollers Data Handbook

IC20”

Four SFRs support the byte level I2C-bus hardware: S1CON, S1STA, S1DAT and S1ADR. They are enabled by setting register bit TXT8. I2C SELECT to logic 1.

7.3.4 LED

SUPPORT

Port pins P0.5 and P0.6 have a 10 mA current sinking capability to enable LEDs to be driven directly.

Philips Semiconductors Preliminary speciﬁcation

TV microcontroller with full screen

SAA5288

On Screen Display (OSD)

7.3.5 6-BIT PWM DACS Eight 6-bit DACs are available to allow direct control of analogue sections of the television. Each low resolution 6-bit DAC is controlled by its associated Special Function Register (PWM0 to PWM7). The PWM

outputs are alternative functions of Port 2 and P3.4. The PWE bit in the SFR for the port corresponding to the PWM should be set to logic 1 for correct operation of the PWM, e.g. if PWM0 is to be used, P2.1 should be set to logic 1 setting the port pin to high-impedance.

7.3.5.1 Pulse Width Modulator Registers (PWM0 to PWM7)

Table 3 Pulse Width Modulator Registers (see Table 10 for addresses)

76543210

PWE − PV5 PV4 PV3 PV2 PV1 PV0

Table 4 Description of PWMn bits (n=0to7)

BIT SYMBOL DESCRIPTION

7 PWE If PWE is set to a logic 1, the corresponding PWM is active and controls its assigned

port pin. If PWE is set to la logic 0, the port pin is controlled by the corresponding bit in

the port SFR. 6 − not used 5 PV5 The output of the PWM is a pulse of period 21.33 µs with a pulse HIGH time determined

4 PV4 3 PV3 2 PV2 1 PV1 0 PV0

by the binary value of these 6-bits multiplied by 0.33 µs. PV5 is the most significant bit.

1997 Jun 24 9

Philips Semiconductors Preliminary speciﬁcation

TV microcontroller with full screen

SAA5288

On Screen Display (OSD)

7.3.6 14-BIT PWM DAC One 14-bit DAC is available to allow direct control of analogue sections of the television. The 14-bit PWM is controlled

using Special Function Registers TDACL and TDACH. The output of the TPWM is a pulse of period 42.66 µs. The 7 most significant bits, TDACH.TD13 (MSB) to TDACH.TD8

and TDACL.TD7, alter the pulse width between 0 and 42.33 µs, in much the same way as in the 6-bit PWMs. The 7 least significant bits, TDACL.TD6 to TDACL.TD0 (LSB), extend certain pulses by a further 0.33 µs, e.g. if the 7 least significant bits are given the value 01H, then 1 in 128 cycles is extended. If the 7 least significant bits are given the value 02H, then 2 in 128 cycles is extended, and so forth.

The TPWM will not start to output a new value until after writing a value to TDACH. Therefore, if the value is to be changed, TDACL should be written to before TDACH.

7.3.6.1 TPWM High Byte Register (TDACH)

Table 5 TPWM High Byte Register (SFR address D3H)

76543210

PWE − TD13 TD12 TD11 TD10 TD9 TD8

Table 6 Description of TDACH bits

BIT SYMBOL DESCRIPTION

7 PWE If PWE is set to a logic 1, the TPWM is active and controls port line P2.0. If PWE is set

to a logic 0, the port pin is controlled by the corresponding bit in the port SFR.

6 − not used 5 TD13 These 6-bits along with bit TD7 in the TDACL register control the pulse width period. 4 TD12 3 TD11 2 TD10 1 TD9 0 TD8

7.3.6.2 TPWM Low Byte Register (TDACL)

Table 7 TPWM Low Byte Register (SFR address D2H)

76543210

TD7 TD6 TD5 TD4 TD3 TD2 TD1 TD0

Table 8 Description of TDACL bits

BIT SYMBOL DESCRIPTION

7 TD7 This bit is used with bits TD13 to TD8 in the TDACH register to control the pulse width

6 to 0 TD6 to TD0 These 7-bits extend certain pulses by a further 0.33 µs.

TD13 is the most signiﬁcant bit.

period.

1997 Jun 24 10

Philips Semiconductors Preliminary speciﬁcation

TV microcontroller with full screen On Screen Display (OSD)

7.3.7 SOFTWARE ADC Up to 4 successive approximation ADCs can be

implemented in software by making use of the on-chip 8-bit DAC and multiplexed voltage comparator. The software ADC uses 4 analog inputs which are multiplexed with P3.0 to P3.3.

Table 9 ADC input channel selection

CH1 CH0 INPUT PIN

0 0 P3.3/ADC3 0 1 P3.0/ADC0 1 0 P3.1/ADC1 1 1 P3.2/ADC2

SAA5288

The control of the ADC is achieved using the Special Function Registers SAD and SADB.

SAD.CH1 and SAD.CH0 select one of the four inputs to pass to the comparator. The other comparator input comes from the DAC, whose value is set by SAD.SAD7 (MSB) to SAD.SAD4 and SADB.SAD3 to SADB.SAD0 (LSB). The setting of the value SAD.SAD7 to SAD.SAD4 must be performed at least 1 instruction cycle before the setting of SAD.ST to ensure comparison is made using the correct SAD.SAD7 to SAD.SAD4 value.

The output of the comparator is SAD.VHI, and is valid after 1 instruction cycle following the setting of SAD.ST to logic 1.

handbook, halfpage

P3.0 P3.1 P3.2 P3.3

MULTIPLEXER

8-BIT DAC

CH1, CH0

SAD7 to SAD0

Fig.3 SAD block diagram.

ST C1

REF+REF−

VH1

MGL115

1997 Jun 24 11

1997 Jun 24 12

7.4 Microcontroller Interfacing

The 80C51 communicates with the peripheral functions using Special Function Registers which are addressed as RAM locations. The registers in the teletext decoder appear as normal SFRs in the microcontroller memory map, but are written to using an internal serial bus. The SFR map is given in Section 7.4.1 and the SFR bit description is given in Section 7.4.2.

Philips Semiconductors Preliminary speciﬁcation

TV microcontroller with full screen

On Screen Display (OSD)

7.4.1 S

PECIAL FUNCTION REGISTER MAP

Table 10 Special Function Register map; note 1

BIT ADDRESS, SYMBOL OR ALTERNATIVE PORT FUNCTION RESET

VALUE

(HEX)

SYMBOL NAME

(2)

ACC

Accumulator E0 E7 E6 E5 E4 E3 E2 E1 E0 00

DIRECT

ADDRESS

(HEX)

76543210

−−−−−−−−

(2)

B register F0 F7 F6 F5 F4 F3 F2 F1 F0 00

−−−−−−−−

DPTR: Data Pointer

(2 bytes): DPH High byte 83 −−−−−−−−00 DPL Low byte 82 −−−−−−−−00

(2)(3)

(2)

Interrupt

Enable

A8 AF AE AD AC AB AA A9 A8 00

EA ES1 ES2 * ET1 EX1 ET0 EX0

Port 0 80 87 86 85 84 83 82 81 80 FF

−−−−−−−−

(2)

Port 1 90 97 96 95 94 93 92 91 90 FF

−−−−−−−−

(2)

Port 2 A0 A7 A6 A5 A4 A3 A2 A1 A0 FF

−−−−−−−−

(2)(3)

Port 3 B0 −−−−B3 B2 B1 B0 FF

−−−−−−−−

(3)

PCON PSW

Power Control 87 − * − * GF1 GF0 −−10

(2)

Program

Status Word

D0 D7 D6 D5 D4 D3 D2 D1 D0 00

CY AC F0 RS1 RS0 OV * P

SAA5288

1997 Jun 24 13

SYMBOL NAME

(3)

PWM0

(3)

PWM1

(3)

PWM2

(3)

PWM3

(3)

PWM4

(3)

PWM5

(3)

PWM6

(3)

PWM7

S1ADR

(3)

S1CON

(2)(3)(4)

S1SCS

(2)(3)(5)

S1DAT

(3)(4)

S1INT

(3)(5)

S1STA

(3)(4)

S1BIT

(3)(5)

Pulse Width

Modulator 0

Pulse Width

Modulator 1

Pulse Width

Modulator 2

Pulse Width

Modulator 3

Pulse Width

Modulator 4

Pulse Width

Modulator 5

Pulse Width

Modulator 6

Pulse Width

Modulator 7

Serial I2C-bus

address

Serial I2C-bus

control

Serial I2C-bus

control

Serial I2C-bus

data

Serial I2C-bus

Interrupt

Serial I2C-bus

status

Serial I2C-bus

data

DIRECT

BIT ADDRESS, SYMBOL OR ALTERNATIVE PORT FUNCTION RESET

ADDRESS

(HEX)

76543210

D5 PWE * PV5 PV4 PV3 PV2 PV1 PV0 40

D6 PWE * PV5 PV4 PV3 PV2 PV1 PV0 40

D7 PWE * PV5 PV4 PV3 PV2 PV1 PV0 40

DC PWE * PV5 PV4 PV3 PV2 PV1 PV0 40

DD PWE * PV5 PV4 PV3 PV2 PV1 PV0 40

DE PWE * PV5 PV4 PV3 PV2 PV1 PV0 40

DF PWE * PV5 PV4 PV3 PV2 PV1 PV0 40

D4 PWE * PV5 PV4 PV3 PV2 PV1 PV0 40

DB ADR6 ADR5 ADR4 ADR3 ADR2 ADR1 ADR0 GC 00

D8 DF DE DD DC DB DA D9 D8

CR2 ENSI STA STO SI AA CR1 CR0 00

D8 DF DE DD DC DB DA D9 D8

SDI SCI CLH BB RBF WBF STR ENS E0

DA DAT7 DAT6 DAT5 DAT4 DAT3 DAT2 DAT1 DAT0 00

DA SI −−−−−−−7F

D9 STAT4 STAT3 STAT2 STAT1 STAT0 0 0 0 F8

D9 SDO/SDI −−−−−−−7F

VALUE

(HEX)

Philips Semiconductors Preliminary speciﬁcation

TV microcontroller with full screen

On Screen Display (OSD)

SAA5288

1997 Jun 24 14

BIT ADDRESS, SYMBOL OR ALTERNATIVE PORT FUNCTION RESET

SYMBOL NAME

(2)(3)

SAD

Software ADC

(MSB) SADB

(2)(3)

Software ADC

(LSB)

DIRECT

ADDRESS

(HEX)

76543210

E8 EF EE ED EC EB EA E9 E8 00

VHI CH1 CH0 ST SAD7 SAD6 SAD5 SAD4

98 9F 9E 9D 9C 9B 9A 99 98 00

−−−−SAD3 SAD2 SAD1 SAD0

SP Stack Pointer 81 8F 8E 8D 8C 8B 8A 89 88 07

(2)

TCON

Timer/counter

88 TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0 00

control TDACH TPWM High

D3 PWE * TD13 TD12 TD11 TD10 TD9 TD8 40

byte TDACL TPWM Low

D2 TD7 TD6 TD5 TD4 TD3 TD2 TD1 TD0 00

byte TH0 Timer 0 High

8C TH07 TH06 TH05 TH04 TH03 TH02 TH01 TH00 00

byte TH1 Timer 1 High

8D TH17 TH16 TH15 TH14 TH13 TH12 TH11 TH10 00

byte TL0 Timer 0 Low

8A TL07 TL06 TL05 TL04 TL03 TL02 TL01 TL00 00

byte TL1 Timer 1 Low

8B TL17 TL16 TL15 TL14 TL13 TL12 TL11 TL10 00

byte TMOD Timer/counter

mode

(3)

TXT0

Teletext

89 GATE C/

TM1M0GATEC/TM1M000

Timer 1 Timer 0

C0 * * AUTO

FRAME

* DISPLAY

STATUS

DISABLE

FRAME

**00

ROW

ONLY

(3)

TXT1

TXT4

TXT5

(3)

Teletext

C1 * * * * * FIELD

POLARITYHPOLARITYVPOLARITY

C4 * * EAST/

WEST

C5 BKGND

OUT

BKGND IN COR

OUT

DISABLE

DBL HT

B MESH ENABLE

COR IN TEXT

OUT

C MESH ENABLE

TEXT IN PICTURE

TRANS

ENABLE

ON OUT

SHADOW

ENABLE

PICTURE

ON IN

VALUE

(HEX)

Philips Semiconductors Preliminary speciﬁcation

TV microcontroller with full screen

On Screen Display (OSD)

SAA5288

1997 Jun 24 15

SYMBOL NAME

(3)

TXT6

(3)

TXT7

(3)

TXT8

(3)

TXT9

(3)

TXT10

(3)

TXT11

(3)

TXT12

TXT13

(2)(3)

(3)

TXT16

(3)

TXT17

Teletext

T eletext

Teletext

DIRECT

BIT ADDRESS, SYMBOL OR ALTERNATIVE PORT FUNCTION RESET

ADDRESS

(HEX)

C6 BKGND

C7 STATUS

76543210

OUT

ROW

BKGND IN COR

OUT

CURSORONREVEAL

COR IN TEXT

OUT

TOP/

BOTTOM

DOUBLE

HEIGHT

TEXT IN PICTURE

ON OUT

BOX ON24BOX ON

1−23

PICTURE

ON IN

BOX ON

TOP

C8 I2C

** *****00

SELECT

C9 CURSOR

FREEZE

CLEAR

MEMORY

*R4R3R2R1R000

CA * * C5 C4 C3 C2 C1 C0 00

CB D7 D6 D5 D4 D3 D2 D1 D0 00

CC * ROM VERR4ROM

VER R3

ROM

VER R2

ROM

VER R1

ROM VERR0TXT ON * 0XXXX

B8 BF BE BD BC BB BA B9 B8 00

* PAGE

CLEARING

525

DISPLAY

* * * * OSD I/F

busy

CF * Y2 Y1 Y0 * * X1 X0 00

B9 * * * FORCE

625

FORCE

525

SCREEN

COL2

SCREEN

COL1

SCREEN

COL0

VALUE

(HEX)

X00B

Philips Semiconductors Preliminary speciﬁcation

TV microcontroller with full screen

On Screen Display (OSD)

Notes

1. The asterisk (*) indicates these bits are inactive and must be written to logic 0 for future compatibility.

2. SFRs are bit addressable.

3. SFRs are modified or added to the 80C51 SFRs.

4. This register is used for Byte Orientated I2C-bus, TXT8. I2C SELECT = 1.

5. This register is used for Bit Orientated I2C-bus, TXT8. I2C SELECT = 0.

SAA5288

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