DATA SH EET
Product specification
Supersedes data of March 1995
File under Integrated Circuits, IC02
1996 Jul 18
INTEGRATED CIRCUITS
SAA5252
Line twenty-one acquisition and
display (LITOD)
1996 Jul 18 2
Philips Semiconductors Product specification
Line twenty-one acquisition and display (LITOD) SAA5252
FEATURES
• Complete ‘stand-alone’ Line 21 decoder in one package
• On-chip display RAM allowing full page Text mode
• Enhanced character display modes
• Full colour captions
• RGB interface for standard colour decoder ICs
• Automatic handling of Field 2 data
• Automatic selection of (1H, 1V), (2H, 1V) or (2H, 2V)
scan modes
• Onboard OSD facility using Character generator
• RGB inputs to support existing OSD ICs
• I
2
C-bus or ‘stand-alone’ pin control
• Automatic data-ready signal generation on data
acquisition
• Can decode signals recorded on standard VHS and
S-VHS tape.
GENERAL DESCRIPTION
The SAA5252 (LITOD) is a single-chip CMOS device,
which will acquire, decode and display Line 21 Closed
Captioning data from a 525-line composite video signal.
Operation as an On-Screen Display (OSD) device is also
possible. Normal and line progressive scan modes are
supported.
QUICK REFERENCE DATA
ORDERING INFORMATION
SYMBOL PARAMETER MIN. TYP. MAX. UNIT
V
DD
supply voltage 4.5 5.0 5.5 V
I
DD
supply current − 30 − mA
V
syn
CVBS sync amplitude 0.1 0.3 0.6 V
V
vid
CVBS video amplitude 0.7 1.0 1.4 V
T
amb
operating ambient temperature −20 − +70 °C
T
stg
storage temperature −55 − +125 °C
TYPE
NUMBER
PACKAGE
NAME DESCRIPTION VERSION
SAA5252P DIP24 plastic dual in-line package; 24 leads (600 mil) SOT101-1
SAA5252T SO24 plastic small outline package; 24 leads; body width 7.5 mm SOT137-1
1996 Jul 18 3
Philips Semiconductors Product specification
Line twenty-one acquisition and display (LITOD) SAA5252
BLOCK DIAGRAM
MBB623 - 1
CHARACTER
GENERATOR
ADDRESSING
CONTROL
CODE
INTERPRETER
AND
ADDRESSING
CHARACTER
ROM
DISPLAY
TIMING
ROUNDING
ITALICS
AND
RGB
MULTIPLEXOR
PAGE
RAM
17
16
15
14
13
9
10
11
12
I C
INTERFACE
2
SERIAL/
PARALLEL
AND
PARITY
SYNC SEPARATOR
AND
ACQUISITION TIMING
ADC
DATA
DETECTOR
OSCILLATOR
5
3
4
7 86
2
1
23
24
20
22
21
19 18
V
SS DD
V
VH
i.c.
RGBREF
BLAN
R
G
B
BLANIN
RIN
GIN
BIN
DR
SDA
SCL
I C/DC
2
OSCIN
OSCGND
OSCOUT
BLACK
IREF
CVBS
SAA5252
Fig.1 Block diagram.
1996 Jul 18 4
Philips Semiconductors Product specification
Line twenty-one acquisition and display (LITOD) SAA5252
PINNING
SYMBOL PIN DESCRIPTION
CVBS 1 composite video input; signal should be connected via a
100 nF capacitor
I
2
C/DC 2 input selects I
2
C or Direct Control
SDA 3 serial data port for I
2
C-bus or mode select input for
direct control
SCL 4 serial clock input for I
2
C-bus or mode select input for
direct control
DR 5 data-ready signal to microcontroller (active-LOW) or
mode select input for direct control
i.c. 6 internally connected; connect to V
SS
for normal
operation
V 7 vertical reference input for display timing
H 8 horizontal reference input for display timing
BLANIN 9 video blanking input from external OSD device
RIN 10 RED video input from external OSD device
GIN 11 GREEN video input from external OSD device
BIN 12 BLUE video input from external OSD device
B 13 BLUE video output
G 14 GREEN video output
R 15 RED video output
BLAN 16 video blanking output
RGBREF 17 input voltage defining output HIGH level for RGB pins
for closed captioning output
V
DD
18 +5 V supply
V
SS
19 0 V ground
OSCOUT 20 oscillator output
OSCIN 21 oscillator input
OSCGND 22 oscillator ground
BLACK 23 video black level storage input; connected to V
SS
via
100 nF capacitor
IREF 24 reference current input; connected to V
SS
via 27 kΩ
resistor
Fig.2 Pin configuration.
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
SAA5252
CVBS
SDA
SCL
DR
i.c.
V
H
BLANIN
RIN
GIN
BIN
B
G
R
BLAN
RGBREF
V
DD
V
SS
OSCOUT
OSCIN
OSCGND
BLACK
IREF
I C/DC
2
MBB622 - 1
1996 Jul 18 5
Philips Semiconductors Product specification
Line twenty-one acquisition and display (LITOD) SAA5252
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 134).
Notes
1. This maximum value has an absolute maximum of 6.5 V independent of V
DD
.
2. The human body model ESD simulation is equivalent to discharging a 100 pF capacitor via a 1.5 kΩ resistor, which
produces a single discharge transient. Reference
“Philips Semiconductors Test Method UZW-BO/FQ-A302 (similar
to MIL-STD 883C method 3015.7)”
.
3. The machine model ESD simulation is equivalent to discharging a 200 pF capacitor via a resistor and series inductor
with effective dynamic values of 25 Ω and 2.5 µH, which produces a damped oscillating discharge. Reference
“Philips Semiconductors Test Method UZW-BO/FQ-B302 (similar to EIAJ IC-121 Test Method 20 condition C)”
.
Quality
This device will meet the requirements of the
“Philips Semiconductors General Quality Specification UZW-BO/FQ-0601”
in accordance with
“Quality Reference Handbook (order number 9397 750 00192)”
. This details the acceptance criteria
for all Q & R tests applied to the product.
SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT
V
DD
supply voltage (all supplies) −0.3 +6.5 V
V
Imax
maximum input voltage (any input) note 1 −0.3 V
DD
+ 0.5 V
V
Omax
maximum output voltage (any output) note 1 − V
DD
+ 0.5 V
V
dif
difference between V
SS
and OSCGND −±0.25 V
I
IOK
DC input or output diode current −±20 mA
I
Omax
maximum output current (each output) −±10 mA
T
amb
operating ambient temperature −20 +70 °C
T
stg
storage temperature −55 +125 °C
V
es
electrostatic handling
human body model note 2 −2000 +2000 V
machine model note 3 −200 +200 V
1996 Jul 18 6
Philips Semiconductors Product specification
Line twenty-one acquisition and display (LITOD) SAA5252
CHARACTERISTICS
V
DD
= 5 to 5.5 V; V
SS
=0V; T
amb
= −20 to +70 °C; unless otherwise specified.
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
Supplies
V
DD
supply voltage 4.5 5.0 5.5 V
I
DDtot
total supply current − 30 − mA
Inputs
CVBS (
PIN 1)
V
syn
sync voltage amplitude 0.1 0.3 0.6 V
V
vid(p-p)
video voltage amplitude
(peak-to-peak value)
0.7 1.0 1.4 V
V
dat
caption data voltage
amplitude
0.25 0.35 0.49 V
Z
source
source impedance −−250 Ω
V
I
input switching voltage level
of sync separator
1.7 2.0 2.3 V
Z
I
input impedance 2.5 5 − kΩ
C
I
input capacitance −−10 pF
IREF (PIN 24)
R
24
resistor to ground − 27 − kΩ
V
24
voltage on pin 24 −
1
⁄
2
V
DD
− V
H(PIN 8)
V
IL
LOW level input voltage −0.3 − +0.8 V
V
IH
HIGH level input voltage 2.0 − V
DD
+ 0.5 V
I
LI
input leakage current V
I
=0toV
DD
−10 − +10 µA
I
Imax
maximum input current −1 − +1 mA
C
I
input capacitance −−10 pF
t
r
pulse rise time −−5µs
t
f
pulse fall time −−5µs
t
W
pulse width
scan mode 1H 1 12 63 µs
scan mode 2H 1 6 31 µs
V(
PIN 7)
V
IL
LOW level input voltage −0.3 − +0.8 V
V
IH
HIGH level input voltage 2.0 − V
DD
+ 0.5 V
I
LI
input leakage current V
I
=0toV
DD
−10 − +10 µA
I
Imax
maximum input current −1 − +1 mA
C
I
input capacitance −−10 pF
t
r
pulse rise time −−5ns
t
f
pulse fall time −−5ns
t
W
pulse width 1 −−µs