Philips SAA4996H Datasheet

INTEGRATED CIRCUITS

SAA4996H

Motion Adaptive Colour Plus And Control IC (MACPACIC) for PALplus

Preliminary specification			1996 Oct 28
File under Integrated Circuits, IC02

Philips Semiconductors	Preliminary specification

Motion Adaptive Colour Plus And

SAA4996H

Control IC (MACPACIC) for PALplus

	CONTENTS		8	TEST
	1	FEATURES	8.1	Boundary scan test
			8.1.1	Identification codes
	2	GENERAL DESCRIPTION
			9	DC CHARACTERISTICS
	3	QUICK REFERENCE DATA
			10	AC CHARACTERISTICS
	4	ORDERING INFORMATION
			10.1	Clock buffers

5BLOCK DIAGRAMS

6PINNING

7FUNCTIONAL DESCRIPTION

7.1Introduction

7.1.1Data processing

7.1.2Control

7.2General requirements

7.3Hardware configurations and delays

7.3.1Full PALplus module (see Fig.5)

7.3.2Stand-alone MACPACIC (see Fig.6)

7.4Analog processing in front of the PALplus module

7.5Block diagram

7.6Luminance and helper processing

7.6.1Input range

7.7Luminance processing

7.7.1Luminance helper processing

7.8Output signals

7.9Measurements

7.9.1Line 22 offset reference measurement

7.9.2Line 23 and 623 amplitude reference measurement

7.9.3Noise measurement in line 23 and 623

7.10Automatic gain and offset control

7.10.1SNERT control bits influencing the AGC and AOC

7.10.2Gain control

7.10.3Offset control

7.10.4Helper amplitude and bandwidth control

7.11Output range

7.12Chrominance

7.12.1Input range

7.12.2Chrominance processing

7.12.3Output signals

7.12.4Output range

7.13Chrominance motion detection

7.14Intelligent residual cross-luminance reduction (IRXR)

7.15Control

7.15.1Input reference signals

7.15.2Functional description

7.15.3SNERT interface (see application note AN95XXX)

11LIST OF ABBREVIATIONS

12PACKAGE OUTLINE

13SOLDERING

13.1Introduction

13.2Reflow soldering

13.3Wave soldering

13.4Repairing soldered joints

14DEFINITIONS

15LIFE SUPPORT APPLICATIONS

1996 Oct 28

2

Philips Semiconductors	Preliminary specification

Motion Adaptive Colour Plus And Control

SAA4996H

IC (MACPACIC) for PALplus

1 FEATURES

∙Motion adaptive colour plus decoding

∙Helper AGC/AOC

∙Helper decompanding

∙Memory controlling

∙VERIC controlling.

2 GENERAL DESCRIPTION

The SAA4996H (MACPACIC) performs the Motion Adaptive Colour Plus (MACP) processing which is a dedicated field comb filter technique exploited for the PALplus system.

3 QUICK REFERENCE DATA

The integrated circuit is especially designed to be used in conjunction with the SAA4997H Vertical Reconstruction IC (VERIC) to decode the transmitted PALplus video signals in PALplus colour TV receivers.

In addition, a hardware configuration ‘stand-alone MACPACIC’ with only two field memories (FM1 and FM4) is also possible. In this condition no helper lines are processed and no vertical reconstruction is applied.

This configuration enables the Motion Adaptive Colour Plus processing to be performed in non PALplus receivers.

SYMBOL	PARAMETER	MIN.	MAX.	UNIT
VDD	digital supply voltage	4.75	5.25	V
Tamb	operating ambient temperature	0	+70	°C
Tdie	die temperature	−	+125	°C

4 ORDERING INFORMATION

TYPE		PACKAGE
NUMBER	NAME	DESCRIPTION	VERSION
SAA4996H	QFP100	plastic quad flat package; 100 leads (lead length 1.95 mm);	SOT317-1
		body 14 × 20 × 2.7 mm; high stand-off height

1996 Oct 28

3

Philips Semiconductors	Preliminary specification

Motion Adaptive Colour Plus And Control

SAA4996H

IC (MACPACIC) for PALplus

5 BLOCK DIAGRAMS

				SAA4996H
	17 to 24												60, 59,
Y_ADC		8								8			57 to 52	Y_MA
				LUMINANCE AND
	1 to 8	8		HELPER PROCESSING						8			37 to 44
Y_FM1														Y_TO_FM1
					YL								45	U_TO_FM1_0
													61, 62,
	15, 16,										4		63, 64	U_MA, V_MA
U_ADC
	13, 14	4
V_ADC			CHROMINANCE		4		3	1					46, 47,	WE_FM2 / U_TO_FM1_1
												3	48
	11, 12,								MUX					WE_FM3 / V_TO_FM1_1
			PROCESSING				3
U_FM1	9, 10	4						0	SEL					RSTW_FM23 / V_TO_FM1_0
V_FM1
			UV_IFA	CS					IVericN		4		91, 92,	U_TO_FM4
													89, 90
														V_TO_FM4
													99	RE_FM1
													100
														WE_FM1
													94
														RE_FM4
													95
	85, 86,	CHROMINANCE												WE_FM4
U_FM4													93
	87, 88	4												RST_FM14
V_FM4		MOTION DETECTION					CONTROL						79
			AND IRXR											VA_AI
													80
														HREF_MA
													28
	81													WE_MA
VA_FRONT													76
														EVEN_FIELD
	29
CLAMP													77
														FILM
	36
WE_FRONT													78
														INTPOL
			control	CLK_16i						3		98, 75, 35		CLK_16B1,2,3
										3		51, 31, 65
				CLK_32i										CLK_32B1,2,3
SNERT_DA	82
	83				CLOCK								68
SNERT_CL		SNERT INTERFACE							TEST					TDO_MA
	84				BUFFER
SNERT_RST
			25, 49,	26, 50,
			67, 73,	66, 74,									30,
		58	96	97	27	33		70	72	71	69		32, 34
		VERIC_AV_N		VSS1 to VSS5	CLK_16			TDI	TMS			TEST1,2,3
			VDD1 to VDD5		CLK_32			TCK		TRSTN				MHA133

Fig.1 Block diagram.

1996 Oct 28

4

28Oct 1996

VA_FRONT

9

LC_ACQ

VA_AI

EVEN_FIELD

6

(MACPACIC)IC

AdaptiveMotion

Mpip

Mpip

line2_every_field

1

1

VA_FRONT

VA_AI_DIFF

0

VA_FR_DEL

0

HlpM0,1

VA_RES

CLK_16I

2

IVericN

V_RE / WE

LINE

RE_FM1

PRE

DECODER

DELAY

ACQ

WE_FM1

PALplusfor

PlusColour

3

LINE

VA_AI_DIFF

H / V

CLK_16I

COUNTER

RE_FM4

InvO/E

LOGIC

VaDel0-2

9 BIT

VA_RES

IVericN

FIELD LENGTH

WE_FM4

CLAMP

EN

EVEN_FIELD

IVericN

CLP_DIFF

VA_FR_DEL

MEASUREMENT,

LD = 1

RST_FM14

VA_RES

Mpip

FIELD

CLK_16I

CLP_DIFF

VA_AI

DETECTION,

CLK_16I

CLK_16I

VA_AI DELAY

CLK_32I

VA_AI_DIFF

1

PC1

(1/2 LINE)

PC2_PRE

MUX2

PRE

PRE

WE_FM2

And

1

0

SEL

DSP

LC_DSP

PIXEL

16/32 MHz

WE_FM3

MUX1

LINE

PC2

H_RE / WE

9

CLK_16I

PIXEL

CONVERTER

0

COUNTER

COUNTER 2

DECODER

SEL

9 BIT

CLK_16I

10 BIT

11

6

RSTW_FM23

Mpip

EN

CLK_16I

CLK

Control

5

CLK_16I

DELAY

IVericN

LD = 1

LD = 2

CLK_16

IVericN

CLK_32

2 CLK_16

CLAMP

HREF_MA

CLK_16B1

PRE

WE_MA

CLK_16B2

CLOCK

PIXEL

10

WE_MA

WE_MA

GENERATION

CLK_16B3

BUFFER

COUNTER 1

CLK_32I

PC1

10 BIT

CLK_32B1

CLK

WeShift16_0,1

CLK_32B2

CLK_16I

FILM

LD = 2

WeStrtH,V

HlpM0,1

2

CLK_32B3

36

WeStpH,V

VERIC

WE_FRONT

FilmOn

CONTROL

Mpip

line2_every_field

DECODER

Preset

MacpOn

HlpM0,1

FilmOn

MotVis0,1

InvO/E

Mpip

VaDel0-2

EnIRXR

EVEN_FIELD

INTPOL

2

2

3

22Valid

SNERT_DA

SNERT_CL

SNERT INTERFACE

TEST AND BST

TDO_MA

SNERT_RST

64

40

5

7

7

3

SAA4996H

HlpRedThr1-5,

IrxrThr1-4,

Control 3:

Fig.2 Block diagram of the control part.

TRSTN TDI TMS TCK TEST1

TEST3

Control 4:

Control 5:

Control 6:

MacpYhThr1-3

FixHlpMain

22/23/623Valid,

SelSdYl0,1,

BOH0-2,

Interlace,

TEST2

IMacpacicN,

NmYl0,1,

VAA0,1,

EnPreEvFld,

MHA137

IVericN

Rha/Rhb0-2

SEL_SD_YL0,1, PreEvFld

NAIRXR

Semiconductors Philips

specification Preliminary

28 Oct 1996

DATA_OUT

2 ACQ DATA

8

Control 4

(MACPACIC)IC

AdaptiveMotion

SemiconductorsPhilips

8

OUTPUT

8

REGISTER

Control 5

PALplusfor

PlusColour

adr_H65/H66

SNERT_RST

FastTest_Del

FAST TEST DELAY

FastTest

(bit D3)

2 SYNCHRON

SERIAL DATA I/O

Control 1/1

Control 1/2

8

8

DATA

8

Control 1

And

REGISTER

ALE

INPUT

ADDRESS

21

8

Control 2/1

8

Control 2/2

8

REGISTER

Control 2

DLE

DECODER

2 ACQ DATA

adr_en_50h

Control

6

SNERT_RST

DATA AND ADDRESS

INPUT

to

SNERT_DA

Line2_odd_every_field

LATCH ENABLE

adr_en_68h

REGISTER

SNERT_CL

GENERATION

4 BIT COUNTER

DATA_IN

21 ACTUAL

8

DATA

INPUT

2 × 8

2 × 8

WeStrtH,

SEND / RECEIVE

REGISTER

WeStrtH*,

4 ACQ DATA

WeStpH

CONTROLLING

SNERT_RST

WeStpH*

INPUT

2 × 9

2 × 9

WeStrtV,

REGISTER

WeStrtV*,

WeStpV

WeStpV*

HlpRedThr1,2,3,4,5,

SNERT_RST

Interlace

14 × 8

MacpYhThr1,2,3,

IrxrThr1,2,3,4,

FixHlpMain,

LINE 2

1 SYNCHRON

Control 5

Line2_every_field

ODD / EVERY FIELD

8

Control 6/1

DATA

8

Line2_odd_every_field

Control 6

ENABLE SIGNAL

INPUT

SAA4996H

specificationPreliminary

EVEN_FIELD

GENERATION

REGISTER

Line2_every_field

MHA138

Fig.3 Block diagram of the SNERT interface.

Philips Semiconductors	Preliminary specification

Motion Adaptive Colour Plus And Control

SAA4996H

IC (MACPACIC) for PALplus

6 PINNING

SYMBOL	PIN	DESCRIPTION
Y_FM1_7	1	CVBS/helper/luminance input data bit 7 from FM1
Y_FM1_6	2	CVBS/helper/luminance input data bit 6 from FM1
Y_FM1_5	3	CVBS/helper/luminance input data bit 5 from FM1
Y_FM1_4	4	CVBS/helper/luminance input data bit 4 from FM1
Y_FM1_3	5	CVBS/helper/luminance input data bit 3 from FM1
Y_FM1_2	6	CVBS/helper/luminance input data bit 2 from FM1
Y_FM1_1	7	CVBS/helper/luminance input data bit 1 from FM1
Y_FM1_0	8	CVBS/helper/luminance input data bit 0 from FM1
V_FM1_0	9	chrominance input data bit 0 from FM1
V_FM1_1	10	chrominance input data bit 1 from FM1
U_FM1_0	11	chrominance input data bit 0 from FM1
U_FM1_1	12	chrominance input data bit 1 from FM1
V_ADC_0	13	chrominance input data bit 0 from ADC
V_ADC_1	14	chrominance input data bit 1 from ADC
U_ADC_0	15	chrominance input data bit 0 from ADC
U_ADC_1	16	chrominance input data bit 1 from ADC
Y_ADC_0	17	CVBS/helper/luminance data input bit 0 from ADC
Y_ADC_1	18	CVBS/helper/luminance data input bit 1 from ADC
Y_ADC_2	19	CVBS/helper/luminance data input bit 2 from ADC
Y_ADC_3	20	CVBS/helper/luminance data input bit 3 from ADC
Y_ADC_4	21	CVBS/helper/luminance data input bit 4 from ADC
Y_ADC_5	22	CVBS/helper/luminance data input bit 5 from ADC
Y_ADC_6	23	CVBS/helper/luminance data input bit 6 from ADC
Y_ADC_7	24	CVBS/helper/luminance data input bit 7 from ADC
VDD1	25	positive supply voltage 1
VSS1	26	negative supply voltage 1
CLK_16	27	16 MHz line-locked system clock input pulse
WE_MA	28	write enable output signal; defines active video data
CLAMP	29	horizontal reference input pulse
TEST1	30	test pin 1; must be LOW during normal operation
CLK_32B2	31	32 MHz line-locked clock output pulse
TEST2	32	test pin 2; must be LOW during normal operation
CLK_32	33	32 MHz line-locked system clock input pulse
TEST3	34	test pin 3; must be LOW during normal operation
CLK_16B3	35	16 MHz line-locked clock output pulse
WE_FRONT	36	write enable input signal used as horizontal reference in the event of active
		data
Y_TO_FM1_0	37	CVBS/helper/luminance output data bit 0 to FM1; stand-alone MACPACIC
Y_TO_FM1_1	38	CVBS/helper/luminance output data bit 1 to FM1; stand-alone MACPACIC
Y_TO_FM1_2	39	CVBS/helper/luminance output data bit 2 to FM1; stand-alone MACPACIC

1996 Oct 28

7

Philips Semiconductors	Preliminary specification

Motion Adaptive Colour Plus And Control

SAA4996H

IC (MACPACIC) for PALplus

SYMBOL	PIN	DESCRIPTION
Y_TO_FM1_3	40	CVBS/helper/luminance output data bit 3 to FM1; stand-alone MACPACIC
Y_TO_FM1_4	41	CVBS/helper/luminance output data bit 4 to FM1; stand-alone MACPACIC
Y_TO_FM1_5	42	CVBS/helper/luminance output data bit 5 to FM1; stand-alone MACPACIC
Y_TO_FM1_6	43	CVBS/helper/luminance output data bit 6 to FM1; stand-alone MACPACIC
Y_TO_FM1_7	44	CVBS/helper/luminance output data bit 7 to FM1; stand-alone MACPACIC
U_TO_FM1_0	45	chrominance output data to FM1; stand-alone MACPACIC
WE_FM2/U_TO_FM1_1	46	for full PALplus module; write enable for FM2 for stand-alone MACPACIC;
		chrominance output to FM1
RSTW_FM23/V_TO_FM1_0	47	for full PALplus module; reset write for FM2/FM3 for stand-alone
		MACPACIC; chrominance output to FM1
WE_FM3/V_TO_FM1_1	48	for full PALplus module; write enable for FM3 for stand-alone MACPACIC;
		chrominance output to FM1
VDD2	49	positive supply voltage 2
VSS2	50	negative supply voltage 2
CLK_32B1	51	32 MHz line-locked clock output pulse
Y_MA_0	52	luminance output data bit 0 from MACPACIC
Y_MA_1	53	luminance output data bit 1 from MACPACIC
Y_MA_2	54	luminance output data bit 2 from MACPACIC
Y_MA_3	55	luminance output data bit 3 from MACPACIC
Y_MA_4	56	luminance output data bit 4 from MACPACIC
Y_MA_5	57	luminance output data bit 5 from MACPACIC
VERIC_AV_N	58	input configuration signal VERIC available (VERIC_AV_N = 0)
Y_MA_6	59	luminance output data bit 6 from MACPACIC
Y_MA_7	60	luminance output data bit 7 from MACPACIC
U_MA_0	61	chrominance output data bit 0 from MACPACIC
U_MA_1	62	chrominance output data bit 1 from MACPACIC
V_MA_0	63	chrominance output data bit 0 from MACPACIC
V_MA_1	64	chrominance output data bit 1 from MACPACIC
CLK_32B3	65	32 MHz line-locked clock output pulse
VSS3	66	negative supply voltage 3
VDD3	67	positive supply voltage 3
TDO_MA	68	boundary scan test: data output signal
TRSTN	69	boundary scan test: reset input signal
TDI	70	boundary scan test: data input signal
TMS	71	boundary scan test: multiplexer set input
TCK	72	boundary scan test: clock input signal
VDD4	73	positive supply voltage 4
VSS4	74	negative supply voltage 4
CLK_16B2	75	16 MHz line-locked clock output pulse
EVEN_FIELD	76	even field =0 = odd input field; even field =1 = even input field

1996 Oct 28

8

Philips Semiconductors	Preliminary specification

Motion Adaptive Colour Plus And Control

SAA4996H

IC (MACPACIC) for PALplus

SYMBOL	PIN	DESCRIPTION
FILM	77	control output signal to select film or camera mode in VERIC;
		FILM = 0: camera mode; FILM = 1: film mode; FILM = 1 and INTPOL = 0;
		bypass mode for MultiPIP
INTPOL	78	INTPOL = 0 = vertical interpolation in the VERIC not active;
		INTPOL = 1 = vertical interpolation in the VERIC active
VA_AI	79	vertical reference output pulse or vertical reference input pulse in MultiPIP
		mode
HREF_MA	80	horizontal reference output pulse
VA_FRONT	81	vertical reference input pulse or vertical reference output pulse in MultiPIP
		mode
SNERT_DA	82	Synchronous No parity Eight bit Reception and Transmission (SNERT)-bus
		data
SNERT_CL	83	SNERT-bus clock
SNERT_RST	84	SNERT-bus reset
U_FM4_0	85	chrominance input data bit 0 from FM4
U_FM4_1	86	chrominance input data bit 1 from FM4
V_FM4_0	87	chrominance input data bit 0 from FM4
V_FM4_1	88	chrominance input data bit 1 from FM4
V_TO_FM4_1	89	chrominance output data bit 1 to FM4
V_TO_FM4_0	90	chrominance output data bit 0 to FM4
U_TO_FM4_1	91	chrominance output data bit 1 to FM4
U_TO_FM4_0	92	chrominance output data bit 0 to FM4
RST_FM14	93	reset read/write FM1 and FM4 output
RE_FM4	94	read enable FM4 output
WE_FM4	95	write enable FM4 output
VDD5	96	positive supply voltage 5
VSS5	97	negative supply voltage 5
CLK_16B1	98	16 MHz line-locked clock output pulse
RE_FM1	99	read enable FM1 output
WE_FM1	100	write enable FM1 output

1996 Oct 28

9

Philips Semiconductors	Preliminary specification

Motion Adaptive Colour Plus And Control

SAA4996H

IC (MACPACIC) for PALplus

handbook, full pagewidth

Y_FM1_7 1

Y_FM1_6 2

Y_FM1_5 3

Y_FM1_4 4

Y_FM1_3 5

Y_FM1_2 6

Y_FM1_1 7

Y_FM1_0 8

V_FM1_0 9

V_FM1_1 10

U_FM1_0 11

U_FM1_1 12

V_ADC_0 13

V_ADC_1 14

U_ADC_0 15

U_ADC_1 16

Y_ADC_0 17

Y_ADC_1 18

Y_ADC_2 19

Y_ADC_3 20

Y_ADC_4 21

Y_ADC_5 22

Y_ADC_6 23

Y_ADC_7 24

VDD1 25

VSS1 26

CLK_16 27

WE_MA 28

CLAMP 29

TEST1 30

WEFM1		REFM1		CLK16B1		V		V		WEFM4		REFM4		RSTFM14		TOU FM4 0		TOU FM4 1		TOV FM4 0		TOV FM4 1		FM4V 1		FM4V 0		FM4U 1		FM4U 0		SNERTRST		SNERTCL		SNERTDA		VAFRONT
						SS5		DD5
100		99		98		97		96		95		94		93		92		91		90		89		88		87		86		85		84		83		82		81

SAA4996H

31		32		33		34		35		36		37		38		39		40		41		42		43		44		45		46		47		48		49		50
CLK 32B2		TEST2		CLK 32		TEST3		CLK 16B3		WE FRONT		Y TO FM1 0		Y TO FM1 1		Y TO FM1 2		Y TO FM1 3		Y TO FM1 4		Y TO FM1 5		Y TO FM1 6		Y TO FM1 7		U TO FM1 0		FM2/UWETO FM1 1		FM23/VRSTWTO FM1 0		FM3/VWETO FM1 1		V		V
																																				DD2		SS2

Fig.4 Pin configuration.

80	HREF_MA
79	VA_AI
78	INTPOL
77	FILM
76	EVEN_FIELD
75	CLK_16B2
74	VSS4
73	VDD4
72	TCK
71	TMS
70	TDI
69	TRSTN
68	TDO_MA
67	VDD3
66	VSS3
65	CLK_32B3
64	V_MA_1
63	V_MA_0
	U_MA_1
62
61	U_MA_0
60	Y_MA_7
59	Y_MA_6
	VERIC_AV_N
58
57	Y_MA_5
56	Y_MA_4
55	Y_MA_3
	Y_MA_2
54
53	Y_MA_1
52	Y_MA_0
51	CLK_32B1

MHA134

1996 Oct 28

10

Philips Semiconductors	Preliminary specification

Motion Adaptive Colour Plus And Control

SAA4996H

IC (MACPACIC) for PALplus

7 FUNCTIONAL DESCRIPTION

7.1Introduction

The MACPACIC is designed to be used in the PALplus decoder module of a PALplus colour TV receiver. The full PALplus decoder module consists of two special integrated circuits and four field memories, as illustrated in Fig.5.

The special ICs are as follows;

∙Motion Adaptive Colour Plus And Control IC (MACPACIC) for PALplus (SAA4996H)

∙Vertical Reconstruction IC (VERIC) (SAA4997H).

Besides the full PALplus module, a configuration for stand-alone Motion Adaptive Colour Plus processing (MACP) is also possible (see Fig.6). In this event only MACPACIC with FM1 and FM4 are necessary.

This configuration enables the MACP processing in non-PALplus receivers to be performed.

The PALplus module is designed to operate in conjunction with a 100 Hz feature box. All special requirements such as the delay of the PALplus module, bypass modes and generation of the necessary control and clock signals will be fulfilled.

7.1.1DATA PROCESSING

The MACPACIC includes the decompanding functions for the helper lines and the motion adaptive luminance/chrominance separation in accordance with the PALplus system description REV. 3.0 with some modifications;

∙The system operates at a clock frequency of 16 MHz

∙The Y:U:V format is 4:1:1 instead of 4:2:2

∙The filter DEC_MD_UV_LPF is not implemented

∙If noisy helper signals are received, the helper bandwidth and/or amplitude can be reduced

∙Automatic gain control of the helper signal with respect to the luminance signal.

The input signals are the BB(helper)/CVBS and chrominance signals which are derived from the analog-to-digital converter (ADC).

At its outputs the MACPACIC delivers separate luminance and chrominance signals, each one free from cross-artefacts as main signal, as well as decompanded and filtered helper signals. For standard input signals and, in the event of MultiPIP mode with the help of a

PIP module, the MACPACIC can be switched to different bypass modes.

7.1.2CONTROL

Memory control, PALplus system controlling and clock generation (from the incoming 16 MHz and 32 MHz line-locked clocks) are implemented in the MACPACIC. All clocks and control signals necessary for the PALplus module (excluding read control of FM2/FM3) are generated in the controller part. Inputs are reference signals, clocks and control signals delivered by the colour/helper decoder IC (TDA9144), and the 100 Hz memory controller, i.e. ECO4 (SAA4952) or ECOBENDIC (SAA4970). The MACPACIC also receives control information via a three-wire serial interface (SNERT-bus) from the microprocessor in the 100 Hz feature box.

7.2General requirements

The PALplus IC set is designed to operate in conjunction with the PHILIPS 100 Hz feature box. All requirements with respect to this combination are fulfilled.

The special requirements are as follows;

∙The signal processing is adapted to the analog preprocessing in the TDA9144 for luminance, helper and chrominance signals

∙Clock rate and clock generation

∙Some special control signals are generated in the PALplus module

∙The field length must be measured and used to set the delay of the full PALplus module to 1.5 fields

∙A SNERT interface is used to transfer control data to and from the PALplus module

∙MultiPIP with the help of a PIP module is possible

∙Results of noise measurements influence the helper processing

∙Automatic gain and offset control is implemented

∙Reference signals in line 22 are used for inverse set-up operation

∙Noise measurement implemented

∙Boundary scan test implemented

∙Preset of internal recursive parts for testing.

1996 Oct 28

11

Philips Semiconductors	Preliminary specification

Motion Adaptive Colour Plus And Control

SAA4996H

IC (MACPACIC) for PALplus

7.3Hardware configurations and delays

Two general hardware configurations are possible.

7.3.1FULL PALPLUS MODULE (see Fig.5)

The delay from input to output is 1.5 fields rounded to complete lines, also in the bypass mode. Therefore, the number of input lines of the odd and even fields must be measured. The result of this measurement is then used to generate the required delay.

In the MultiPIP mode the delay of the full PALplus module is one line.

7.3.2STAND-ALONE MACPACIC (see Fig.6)

In this situation only the MACPACIC with FM1 and FM4 are necessary. No helper lines are processed and no vertical reconstruction with the VERIC is applied.

The delay from input to output is one field, one line and some clocks of processing delay, this also applies in the bypass mode. In the MultiPIP mode the delay is two clocks (CLK_16).

7.4Analog processing in front of the PALplus module

In front of the MACPACIC an analog colour/helper decoder (TDA9144) performs the colour and helper demodulation.

Because of the requirement that a standard ADC with clamping on 16 should be used for CVBS and helper analog-to-digital conversion, a black (letter box lines) and mid grey (helper lines) shift is applied in the colour/helper decoder. For reshifting without errors in the digital domain these shift levels are inserted as a reference in line 22.

In the event of stand-alone MACPACIC and PALplus input signals the helper demodulation must be switched off.

No special actions are taken in the colour/helper decoder for chrominance processing.

In this document U will refer to −(B − Y) and V will refer to −(R − Y).

In combination with the full PALplus module with letter box input signals (16:9), the PAL delay line of the colour/helper decoder must be switched off. This is because this function is also implemented in the vertical reconstruction filter of the VERIC. For all other input signals and for stand-alone MACPACIC the PAL delay line must be switched on.

1996 Oct 28

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Philips Semiconductors	Preliminary specification

Motion Adaptive Colour Plus And Control

SAA4996H

IC (MACPACIC) for PALplus

SAA4996H

3

CLK_16B1, 2, 3

SAA4997H

8

3

CLK_32B1, 2, 3

CLK_32B1

Y_VE_0...7

Y_VE_[0...7]

8

Y_ADC_0...7

Y_FRONT[0...7]

8

8

8

Y_FM23_0...7

FIELD MEMORY

FIELD MEMORY

8

Y_FM1_0...7

8

FM2

Y_MA_0...7

4

4

4

U_FM23_0,1

FM1

4

U_FM1_0,1

V_FM23_0,1

V_FM1_0,1

8

8

SWCK

SRCK

FIELD MEMORY

U_MA_0,1

4

V_MA_0,1

CLK_16B1

FM3

U_VE_[0,1]

4

U_VE_0,1

4

CLK_16

4

4

U_ADC_0,1

V_VE_[0,1]

V_VE_0,1

U_FRONT[0,1]

V_ADC_0,1

V_FRONT[0,1]

CLK_32B3

8

Y_TO_FM1_0...7

5

BB-DECOMPANDING

U_TO_FM1_0

INVERSE QMF

VDD1-5

WE_FM2 (1)

4

5

VDD1-4

RECONSTRUCTION

VSS1-5

MOTION ADAPTIVE

U_TO_FM1_1

4

VSS1-4

FILTER

CLK_16

LUMINANCE /

RSTW_FM23 (1)

CLK_32

CHROMINANCE

V_TO_FM1_0

CLK_16B2

SEPARATION

WE_FM3 (1)

CLK_32B3

TDO_VE

VERTICAL

VA_FRONT

V_TO_FM1_1

HREF_MA

CHROMINANCE

OE_FM2

WE_FRONT

MEMORY CONTROL

2

WE_FM1, RE_FM1

SRC

CLAMP

VA_AI

OE_FM3

PALplus CONTROL

RST_FM14

2

SNERT_DA

WE_FM4, RE_FM4

FILM

RE_FM2

CLOCK GENERATION

FM2 / FM3

SNERT_CL

VA_AI

EVEN_FIELD

RE_FM3

SNERT_RST

INTPOL

READ CONTROL

SYNC GENERATION

WE_MA

RSTR_FM23

TRSTN

HREF_MA

TRSTN

SNERT INTERFACE

TDI

FILM

TDI

TMS

TMS

EVEN_FIELD

TCK

TCK

INTPOL

3

3

TEST1-3

TDO_MA

TEST1-3

U_TO_FM4_0,1

U_FM4_0,1

VERIC_AV_N (2)

11

NC

V_TO_FM4_0,1 V_FM4_0,1

4

4

MHA136

FIELD MEMORY

FM4

CLK_16B1

(1)In case of stand-alone MACPACIC the output signals are U_TO_FM1_1, V_TO_FM1_0 or V_TO_FM1_1. Otherwise the output signals are WE_FM2, RSTW_FM23 or WE_FM3.

(2)VERIC available: VERIC_AV_N is connected to VSS.

Fig.5 PALplus decoder module.

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Philips Semiconductors	Preliminary specification

Motion Adaptive Colour Plus And Control

SAA4996H

IC (MACPACIC) for PALplus

Y_TO_FM1_0...7

8

Y_ADC_0...7

Y_FRONT[0...7]

Y_TO_FM1_0

8

Y_FM1_0...7

FIELD MEMORY

Y_MA_0...7

FM1

4

U_FM1_0,1

U_MA_0,1

SWCK SRCK

V_FM1_0,1

V_MA_0,1

SAA4996H

CLK_16B1

4

CLK_

16

U_ADC_0,1

U_FRONT[0,1]

V_ADC_0,1

V_FRONT[0,1]

5

VDD1-5

5

VSS1-5

MOTION ADAPTIVE

CLK_16

LUMINANCE /

CLK_32

CHROMINANCE

SEPARATION

VA_FRONT

MEMORY CONTROL

WE_FRONT

CLAMP

PALplus CONTROL

SNERT_DA

CLOCK GENERATION

SNERT_CL

SNERT_RST

SYNC GENERATION

TRSTN

SNERT INTERFACE

TDI

TMS

TCK

3

TEST1-3

U_TO_FM4_0,1

U_FM4_0,1

VERIC_AV_N (2)

V_TO_FM4_0,1 V_FM4_0,1

4

4

8

8

4

RSTW_FM23

V_TO_FM1_0 (1)

WE_FM2

U_TO_FM1_1 (1)

WE_FM3

V_TO_FM1_1 (1)

3

CLK_16B1, 2, 3

3

CLK_32B1, 2, 3

2

WE_FM1, RE_FM1

RST_FM14

2

WE_FM4, RE_FM4 VA_AI

WE_MA

HREF_MA

FILM

EVEN_FIELD

INTPOL

TDO_MA

FIELD MEMORY

CLK_16B1

FM4

Y_MA_0...7

U_MA_0,1

V_MA_0,1

MHA135

(1)In case of stand-alone MACPACIC the output signals are U_TO_FM1_1, V_TO_FM1_0 or V_TO_FM1_1. Otherwise the output signals are WE_FM2, RSTW_FM23 or WE_FM23.

(2)VERIC not available: VERIC_AV_N is connected to VDD.

Fig.6 Stand-alone MACPACIC.

1996 Oct 28

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Philips Semiconductors	Preliminary specification

Motion Adaptive Colour Plus And Control

SAA4996H

IC (MACPACIC) for PALplus

7.5Block diagram

The functional block diagram of the MACPACIC for PALplus is illustrated in Fig.1. The device consists of 4 main parts:

∙Luminance and helper processing

∙Chrominance processing

∙Chrominance motion detection

∙Control.

The clock rate of the input data is 16 MHz. Internally, the device operates at a 32 MHz clock frequency. The clock rate of the output data is either 32 MHz (in combination with FM2, FM3 and VERIC) or 16 MHz for stand-alone MACP processing.

The delay of the full PALplus module is 1.5 fields in the PALplus and bypass mode. A field length measurement is implemented. For MultiPIP with the help of a PIP module the delay of the PALplus module is one line.

For stand-alone MACP the delay is one field, one line and some clocks of processing delay.

For MultiPIP with the help of a PIP module the delay of MACPACIC is two clocks (CLK_16).

7.6Luminance and helper processing

7.6.1INPUT RANGE

To use a standard ADC with clamping on 16, a black set-up for the CVBS signal and a black/mid grey set-up for the helper signal has to be performed in the colour/helper decoder. The shift values for black set-up and mid grey set-up are inserted in line 22.

All values are nominal values.

CVBS:

clamp level: 16

black set-up: 51

white: 191

format: 8-bit, straight binary

Helper:

mid grey set-up: 121

range: (121 − 60) to (121 + 60) = 61 to 181 format: 8-bit, offset binary

Y (standard input):

black: 16

peak white: 191

format: 8-bit, straight binary

7.7Luminance processing

The luminance and the helper processing have two input branches. One input is an 8-bit wide 16 MHz data stream from the ADC. The other is an 8-bit wide 16 MHz data stream from the field memory (FM1). The odd field of an input frame is stored in the field memory FM1. In the even field of a frame, the even field together with the delayed odd field is processed by the MACPACIC.

To remove the chrominance part of the incoming composite video signal, the Motion Adaptive Colour Plus technique is applied. Colour Plus is a dedicated comb filter technique, which makes full use of the correlation of two successive fields.

During processing the data of the odd and even fields are separated in a high-pass and low-pass part. The high-pass part consists of the luminance high-pass component and the modulated chrominance signal. Due to the phase difference of the colour carrier of 180° from the odd to the even field, the chrominance signal can be removed by adding the high-pass signals.

This processing will work successfully in the film mode, because scanned film material is motionless within the two fields of one frame. In the camera mode a motion detector fades down the luminance high-pass component if motion is detected.

The following vertical low-pass filters perform a vertical interpolation of the high-pass part by the factor of two.

In the event of bad signal conditions, the residual cross-luminance signal, caused by clock jitter between two fields, can be reduced by using this filter as a 2D comb filter. Therefore different sets of coefficients can be selected via SNERT.

The luminance high-pass part and the luminance low-pass part are then added.

The automatic gain control (AGC) and automatic offset control (AOC) functions use reference lines 23,

623 and 22 to reduce errors in the vertical reconstruction in the VERIC. This is to reduce the effects of any errors that might be caused due to variations in the conventional PAL references in the signal during the transmission chain with respect to the levels of the luminance letter box and helper signals.

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Philips Semiconductors	Preliminary specification

Motion Adaptive Colour Plus And Control

SAA4996H

IC (MACPACIC) for PALplus

7.7.1LUMINANCE HELPER PROCESSING

In the event of incoming helper, the switchable low-pass filter acts as an inverse shaping and bandwidth reduction filter for the helper lines. If a distorted helper signal is transmitted, the bandwidth can be reduced from 2.2 MHz (0 dB) to 1.0 MHz or to 0.5 MHz (-3 dB).

The high-pass part of the luminance processing is not used for the helper processing.

To stabilize the transmitted helper signal against noise disturbances, the encoder performs a companding of the signal. In the decoder the decompanding is performed in the AGOC block (see Fig.7).

7.8Output signals

In the event of full PALplus configuration, odd and even field data are multiplexed to a 32 MHz data stream.

For the stand-alone MACPACIC, the processed even field data is connected to the field memory FM1 and the odd field data is switched to the output Y_MA. In the next field the stored even field data is read out of the field memory FM1 and then connected to the output of the MACPACIC.

If MultiPIP mode is selected, the luminance input data from the ADC (Y_ADC) is switched directly to the output Y_MA.

In the bypass mode the luminance data processing is switched off and multiplexed data is connected to the MACPACIC output.

The clock frequency of the output data Y_MA is 32 MHz for the MACPACIC in combination with the VERIC, or 16 MHz for the stand-alone MACPACIC.

7.9Measurements

The digital data stream at the input of the PALplus decoder module contains three reference lines;

·Reference line 22 consists of the black and mid grey set-up, inserted by the colour/helper decoder

·The second half of line 23 contains the black level reference and the maximum negative reference for the PALplus helper lines

·The first half of line 623 contains reference values for the black level and the peak white level for the main lines.

The reference lines 23 and 623 are generated by the PALplus encoder and are used to reduce the effects of any errors that might be caused due to variations in the transmission chain with respect to the levels of the luminance letter box and helper signals.

The content and the timing of the reference lines are illustrated in Figs 13, 14 and 15.

7.9.1LINE 22 OFFSET REFERENCE MEASUREMENT

Due to the fact that a standard ADC with a clamping level of 16 should be inserted for CVBS and helper analog-to-digital conversion, a black offset for the letter box lines and a mid grey offset for the helper lines are carried out in the colour/helper decoder. These offset values are inserted as references in line 22 to reshift the CVBS and helper signals in the digital domain without errors. Therefore, a measurement of the offsets in line 22 is necessary. The average value of the real offset is calculated from 64 samples and substacted from the CVBS and helper signal. The CVBS and helper input signal are illustrated in Fig.16.

7.9.2LINE 23 AND 623 AMPLITUDE REFERENCE

MEASUREMENT

The helper and luminance amplitude measurement consists of averaging 64 samples each of;

Helper zero (MHZ).

Helper maximum (MHM).

Luminance black (MLB).

Luminance white (MLW).

Measured helper amplitude = helper maximum minus helper zero.

Measured luminance amplitude = luminance white minus luminance black.

Frame integration is performed with a feed back factor of (1 - K) = 1¤16. The frame integration part can be preset with the first measured value. Preset is controlled with the preset bit transmitted via SNERT.

7.9.3NOISE MEASUREMENT IN LINE 23 AND 623

For the helper lines the noise measurement is carried out in reference line 23 and for the letter box lines in reference line 623. Both measurements are active in the black reference levels of line 23 and line 623 respectively.

The processing of the noise measurement for the helper signal and the letter box signal is performed in the same way.

First the average value of 64 samples is calculated.

The single actual sample values are subtracted from this average value and the sum of these absolute differences are frame integrated. The integration factor is 1 - K = 1¤16.

1996 Oct 28

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Philips Semiconductors	Preliminary specification

Motion Adaptive Colour Plus And Control

SAA4996H

IC (MACPACIC) for PALplus

The frame integration part can be preset with the first measured value. Preset is controlled via a bit from the SNERT interface.

7.10Automatic gain and offset control

The automatic gain and offset control circuit evaluates the results of the reference data, which are derived from reference lines 22, 23 and 623 to eliminate any offset and gain differences between the letter box lines and the helper lines. This is caused during transmission of the video signal.

7.10.1SNERT CONTROL BITS INFLUENCING THE AGC AND

AOC

MacpOn: If line 22 is not detected this bit will be ignored and the MACP processing (and thus AGC and AOC) is switched off.

FilmOn: If line 22 is not detected, the VERIC operates in Camera mode.

HlpM1, HlpM0: In adaptive and fixed helper processing modes (HlpM1 = 1, HlpM0 = X) AGC and AOC are achieve.

Table 1 Control bits HlpM1 and HlpM0

HlpM1	HlpM0	FUNCTION
0	0	no helper processing
		(any aspect ratio, without helper)
0	1	helper set to zero
		(up-conversion without helper)
1	0	adaptive helper processing (helper
		processing controlled by reference
		amplitudes and noise in the helper
		channel)
1	1	fixed helper processing (fixed gain
		values loaded via SNERT-bus)

7.10.2GAIN CONTROL

If line 22 reference is present in a frame, the luminance input signal contains black set-up and reduced amplitude. The luminance gain then is 1.25. If line 22 is not valid the luminance gain is 1.0.

The helper gain is controlled by the measured helper amplitude in line 23 to match the helper amplitude to the decompanding table. After decompanding the helper amplitude is controlled by the measured luminance amplitude in line 623, to obtain the correct luminance/helper ratio for the QMF filter in the VERIC.

The helper amplitude is reduced when the measured noise exceeds a certain threshold level. These thresholds are conveyed via the SNERT-bus. The reduction of the helper amplitude, before decompanding, ensures that more noise is cancelled by the coring. The adaptive helper gain control is switched off when the SNERT bits HlpM1 and HlpM0 are both at logic 1. In this condition the helper gain is defined by the values FixHlp and FixMain via the SNERT-bus.

If the measured helper or luminance amplitude is below the threshold level, or when line 22 is not valid, the helper is switched off.

7.10.3OFFSET CONTROL

As long as line 22 reference is present, luminance and helper offset are controlled by line 22. If line 22 is not valid the offset value is fixed to 16.

For luminance offset control a hysteresis function, controlled by SNERT, is applied to the measured luminance offset.

7.10.4HELPER AMPLITUDE AND BANDWIDTH CONTROL

In the event of noisy helper signals the helper amplitude and bandwidth can be reduced to avoid disturbances in the inverse QMF processing in VERIC.

Five thresholds are therefore transmitted via SNERT. These thresholds are compared with the measured helper noise value. The results are used to control a state machine with five states.

The state machine is initialized with the preset bit from SNERT or when line 22 is valid for the first time.

The output states are used to control the helper amplitude and bandwidth as shown in Fig.8 and Tables 2 and 3.

7.11Output range

Luminance lines: straight binary, black = 16, white = 191.

PALplus helper lines: offset binary, 128 ±70.

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17

28 Oct 1996

18

SWITCHABLE

Y_LP (even)

Y_ADC

LM

+

AGOC

Y_TO_FM1

LOW-PASS

FILTER

Y_HP (even)

HIGH-PASS

FILTER

YL

(fade controlled

from motion

VERTICAL

detector)

LPF

Y_HP

3 TAB

+

X

MEASUREMENTS

Y_ADC

MUX

Y_MA

Y_FM1

VERTICAL

LPF

measurement

3 TAB

results

HIGH-PASS

FILTER

Y_HP (odd)

SWITCHABLE

Y_LP (odd)

Y_FM1

LOW-PASS

LM

+

AGOC

MHA300

FILTER

Fig.7 Luminance and helper processing.

(MACPACIC) IC	Adaptive Motion
PALplus for	Plus Colour
	Control And

SAA4996H

Semiconductors Philips

specification Preliminary