Philips SAA4992H-V1 Datasheet

DATA SH EET

Product specification
File under Integrated Circuits, IC02

2000 Feb 04

INTEGRATED CIRCUITS

SAA4992H

Field and line rate converter with
noise reduction

2000 Feb 04 2

Philips Semiconductors Product specification

Field and line rate converter with noise
reduction

SAA4992H

CONTENTS

1 FEATURES
2 GENERAL DESCRIPTION
3 QUICK REFERENCE DATA
4 ORDERING INFORMATION
5 BLOCK DIAGRAMS
6 PINNING
7 FUNCTIONAL DESCRIPTION
8 CONTROL REGISTER DESCRIPTION
9 LIMITING VALUES
10 THERMAL CHARACTERISTICS
11 CHARACTERISTICS
12 PACKAGE OUTLINE
13 SOLDERING

13.1 Introduction to soldering surface mount
packages

13.2 Reflow soldering

13.3 Wave soldering

13.4 Manual soldering

13.5 Suitability of surface mount IC packages for
wave and reflow soldering methods

14 DEFINITIONS
15 LIFE SUPPORT APPLICATIONS

2000 Feb 04 3

Philips Semiconductors Product specification

Field and line rate converter with noise
reduction

SAA4992H

1 FEATURES

• Upconversion of all 1fH film and video standards up to

292 active input lines per field

• 100/120 Hz 2 : 1, 50/60 Hz 1 : 1 and 100/120 Hz 1 : 1

output formats

• 4:1:1, 4:2:2 and 4 : 2 : 2 Differential Pulse Code

Modulation (DPCM) input colour formats; 4 :1:1 and
4:2:2 output colour formats

• Full 8-bit accuracy

• Scalable performance by applying 1, 2 or 3 external

field memories

• Improved recursive de-interlacing

• Film (25 Hz, 30 Hz) upconversion to 100/120

movement phases per second

• Variable vertical sharpness enhancement

• Motion compensated 3D dynamic noise reduction

• High quality vertical zoom

• 2 Mbaud serial interface (SNERT).

2 GENERAL DESCRIPTION

The SAA4992H is a completely digital monolithic
integrated circuit which can be used for field and line rate
conversion of all global TV standards.

It features improved‘Natural Motion’ performance and full
film upconversion for all 50 and 60 Hz film material.

It can be configured to emulate the SAA4990H as well as
the SAA4991WP. For demonstration purposes a split
screen mode to show the Dynamic Noise Reduction
(DNR) function and a colour vector overlay is available.

The SAA4992H supports a Boundary Scan Test (BST)
circuit in accordance with IEEE 1149.

3 QUICK REFERENCE DATA

4 ORDERING INFORMATION

SYMBOL PARAMETER MIN. TYP. MAX. UNIT

V

DD

supply voltage 3.0 3.3 3.6 V

I

DD

supply current − 400 550 mA

f

CLK

operating clock frequency − 32 33.3 MHz

T

amb

ambient temperature 0 − 70 °C

TYPE

NUMBER

PACKAGE

NAME DESCRIPTION VERSION

SAA4992H QFP160 plastic quad flat package; 160 leads (lead length 1.6 mm);

body 28 × 28 × 3.4 mm; high stand-off height

SOT322-2

2000 Feb 04 4

Philips Semiconductors Product specification

Field and line rate converter with noise

reduction

SAA4992H

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5 BLOCK DIAGRAMS

n

dbook, full pagewidth

MHB645

COMPRESS

DYNAMIC

NOISE

REDUCTION

MUX

SPM TPM ESM

MUX

FIELD MEMORY 2

YB7 to YB0
151, 152,

154 to 159

YC0 to YC7
2 to 9

DECOMPRESS

SAA4992H

61 to 68

45 to 52

YF7 to YF0

YG7 to YG0

YA0 to YA7

MPR
LEFT

UPCONVERSION

DE-INTERLACER

SNERT

INTERFACE

MOTION ESTIMATOR

MPR

RIGHT

82 to 89

27

SNCL

26

SNDA

25

SNRST

BST/TEST

35

vectors

vectors

TCK

34

TDO

33

TDI

32

TMS

31

TRST

30

TEST

79

CLK32

CONTROL

SEQUENCER

FIELD MEMORY 3

YD7 to YD0
111, 112,

114 to 119

YE0 to YE7
122 to 129

VERTICAL

ZOOM

VERTICAL

PEAKING

Fig.1 Block diagram of the luminance part.

The solid lines represent pixel data; the broken lines represent controls.

2000 Feb 04 5

Philips Semiconductors Product specification

Field and line rate converter with noise

reduction

SAA4992H

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d

book, full pagewidth

MHB646

COMPRESS/

FORMAT

UVB3 to UVB0
147 to 150

UVC0 to UVC3
10 to 13

DECOMPRESS/

REFORMAT

DNR

MPR
LEFT

DECOMPRESS/

REFORMAT

FORMAT

SAA4992H

70 to 77

37 to 44

UVA0 to UVA7

91 to 98

vectors

UPCONVERSION

MPR

RIGHT

VERTICAL

ZOOM

UVD3 to UVD0
107 to 110

UVE0 to UVE3

130 to 133

FIELD MEMORY 2 FIELD MEMORY 3

UVF7 to YVF0

UVG7 to YVG0

Fig.2 Block diagram of the chrominance part.

The solid lines represent pixel data; the broken lines represent controls.

2000 Feb 04 6

Philips Semiconductors Product specification

Field and line rate converter with noise
reduction

SAA4992H

6 PINNING

SYMBOL PIN TYPE DESCRIPTION

(1)(2)

V

SSE

1 ground ground of output pads
YC0 2 input bus C luminance input from field memory 2 bit 0 (LSB)
YC1 3 input bus C luminance input from field memory 2 bit 1
YC2 4 input bus C luminance input from field memory 2 bit 2
YC3 5 input bus C luminance input from field memory 2 bit 3
YC4 6 input bus C luminance input from field memory 2 bit 4
YC5 7 input bus C luminance input from field memory 2 bit 5
YC6 8 input bus C luminance input from field memory 2 bit 6
YC7 9 input bus C luminance input from field memory 2 bit 7 (MSB)
UVC0 10 input bus C chrominance input from field memory 2 bit 0 (LSB)
UVC1 11 input bus C chrominance input from field memory 2 bit 1
UVC2 12 input bus C chrominance input from field memory 2 bit 2
UVC3 13 input bus C chrominance input from field memory 2 bit 3 (MSB)
REC 14 output read enable output for busC
V

SSE

15 ground ground of output pads

V

DDE

16 supply supply voltage of output pads

V

SSI

17 ground core ground

V

DDI

18 supply core supply voltage

JUMP0 19 input configuration pin 0; will be stored in register 0B3 e.g. to indicate presence of 3rd field

memory; should be connected to ground or to V

DDI

via pull-up resistor; note 3

JUMP1 20 input configuration pin 1; will be stored in register 0B5 e.g. to indicate presence of 16-bit

1st field memory for full 4:2:2; should be connected to ground or to V

DDI

via

pull-up resistor; note 3

V

DDE

21 supply supply voltage of output pads

V

DDI

22 supply core supply voltage

V

SSI

23 ground core ground
RAMTST1 24 input test pin 1 for internal RAM testing; connect to ground for normal operation
SNRST 25 input SNERT bus reset
SNDA 26 I/O SNERT bus data
SNCL 27 input SNERT bus clock
V

SSE

28 ground ground of output pads
RAMTST2 29 input test pin 2 for internal RAM testing; connect to ground for normal operation
TEST 30 input test mode input; if not used it has to be connected to ground
TRST 31 input boundary scan test: reset input signal; if not used it has to be connected to ground via

pull-down resistor; note 3

TMS 32 input boundary scan test: test mode select; if not used it has to be connected to V

DDI

via

pull-up resistor; note 3

TDI 33 input boundary scan test: data input signal; if not used it has to be connected to V

DDI

via

pull-up resistor; note 3

TDO 34 output boundary scan test: data output signal

2000 Feb 04 7

Philips Semiconductors Product specification

Field and line rate converter with noise
reduction

SAA4992H

TCK 35 input boundary scan test: clock input signal; if not used it has to be connected to V

DDI

via

pull-up resistor; note 3

V

SSE

36 ground ground of output pads
UVA0 37 input bus A chrominance input from field memory 1 bit 0 (LSB)
UVA1 38 input bus A chrominance input from field memory 1 bit 1
UVA2 39 input bus A chrominance input from field memory 1 bit 2
UVA3 40 input bus A chrominance input from field memory 1 bit 3
UVA4 41 input bus A chrominance input from field memory 1 bit 4
UVA5 42 input bus A chrominance input from field memory 1 bit 5
UVA6 43 input bus A chrominance input from field memory 1 bit 6
UVA7 44 input bus A chrominance input from field memory 1 bit 7 (MSB)
YA0 45 input bus A luminance input from field memory 1 bit 0 (LSB)
YA1 46 input bus A luminance input from field memory 1 bit 1
YA2 47 input bus A luminance input from field memory 1 bit 2
YA3 48 input bus A luminance input from field memory 1 bit 3
YA4 49 input bus A luminance input from field memory 1 bit 4
YA5 50 input bus A luminance input from field memory 1 bit 5
YA6 51 input bus A luminance input from field memory 1 bit 6
YA7 52 input bus A luminance input from field memory 1 bit 7 (MSB)
REA 53 output read enable output for bus A
V

SSE

54 ground ground of output pads
V

SSI

55 ground core ground
V

DDI

56 supply core supply voltage
V

DDI

57 supply core supply voltage
V

SSI

58 ground core ground
V

SSE

59 ground ground of output pads
REF 60 input read enable input for bus F and G
YF7 61 output bus F luminance output bit 7 (MSB)
YF6 62 output bus F luminance output bit 6
YF5 63 output bus F luminance output bit 5
YF4 64 output bus F luminance output bit 4
YF3 65 output bus F luminance output bit 3
YF2 66 output bus F luminance output bit 2
YF1 67 output bus F luminance output bit 1
YF0 68 output bus F luminance output bit 0 (LSB)
V

DDE

69 supply supply voltage of output pads
UVF7 70 output bus F chrominance output bit 7 (MSB)
UVF6 71 output bus F chrominance output bit 6
UVF5 72 output bus F chrominance output bit 5
UVF4 73 output bus F chrominance output bit 4
UVF3 74 output bus F chrominance output bit 3

SYMBOL PIN TYPE DESCRIPTION

(1)(2)

2000 Feb 04 8

Philips Semiconductors Product specification

Field and line rate converter with noise
reduction

SAA4992H

UVF2 75 output bus F chrominance output bit 2
UVF1 76 output bus F chrominance output bit 1
UVF0 77 output bus F chrominance output bit 0 (LSB)
V

SSE

78 ground ground of output pads
CLK32 79 input system clock input
V

SSI

80 ground core ground
V

SSE

81 ground ground of output pads
YG7 82 output bus G luminance output bit 7 (MSB)
YG6 83 output bus G luminance output bit 6
YG5 84 output bus G luminance output bit 5
YG4 85 output bus G luminance output bit 4
YG3 86 output bus G luminance output bit 3
YG2 87 output bus G luminance output bit 2
YG1 88 output bus G luminance output bit 1
YG0 89 output bus G luminance output bit 0 (LSB)
V

DDE

90 supply supply voltage of output pads
UVG7 91 output bus G chrominance output bit 7 (MSB)
UVG6 92 output bus G chrominance output bit 6
UVG5 93 output bus G chrominance output bit 5
UVG4 94 output bus G chrominance output bit 4
UVG3 95 output bus G chrominance output bit 3
UVG2 96 output bus G chrominance output bit 2
UVG1 97 output bus G chrominance output bit 1
UVG0 98 output bus G chrominance output bit 0 (LSB)
V

SSE

99 ground ground of output pads
V

SSI

100 ground core ground

V

DDI

101 supply core supply voltage

V

DDE

102 supply supply voltage of output pads

V

DDI

103 supply core supply voltage

V

SSI

104 ground core ground

V

SSE

105 ground ground of output pads
WED 106 output write enable output for bus D
UVD3 107 output bus D chrominance output to field memory 3 bit 3 (MSB)
UVD2 108 output bus D chrominance output to field memory 3 bit 2
UVD1 109 output bus D chrominance output to field memory 3 bit 1
UVD0 110 output bus D chrominance output to field memory 3 bit 0 (LSB)
YD7 111 output bus D luminance output to field memory 3 bit 7 (MSB)
YD6 112 output bus D luminance output to field memory 3 bit 6
V

DDE

113 supply supply voltage of output pads
YD5 114 output bus D luminance output to field memory 3 bit 5
YD4 115 output bus D luminance output to field memory 3 bit 4

SYMBOL PIN TYPE DESCRIPTION

(1)(2)

2000 Feb 04 9

Philips Semiconductors Product specification

Field and line rate converter with noise
reduction

SAA4992H

YD3 116 output bus D luminance output to field memory 3 bit 3
YD2 117 output bus D luminance output to field memory 3 bit 2
YD1 118 output bus D luminance output to field memory 3 bit 1
YD0 119 output bus D luminance output to field memory 3 bit 0 (LSB)
V

SSE

120 ground ground of output pads
V

SSE

121 ground ground of output pads
YE0 122 input bus E luminance input from field memory 3 bit 0 (LSB)
YE1 123 input bus E luminance input from field memory 3 bit 1
YE2 124 input bus E luminance input from field memory 3 bit 2
YE3 125 input bus E luminance input from field memory 3 bit 3
YE4 126 input bus E luminance input from field memory 3 bit 4
YE5 127 input bus E luminance input from field memory 3 bit 5
YE6 128 input bus E luminance input from field memory 3 bit 6
YE7 129 input bus E luminance input from field memory 3 bit 7 (MSB)
UVE0 130 input bus E chrominance input from field memory 3 bit 0 (LSB)
UVE1 131 input bus E chrominance input from field memory 3 bit 1
UVE2 132 input bus E chrominance input from field memory 3 bit 2
UVE3 133 input bus E chrominance input from field memory 3 bit 3 (MSB)
REE 134 output read enable output for bus E
V

SSE

135 ground ground of output pads
n.c. 136 − not connected
V

SSI

137 ground core ground
V

DDI

138 supply core supply voltage
n.c. 139 − not connected
n.c. 140 − not connected
V

DDE

141 supply supply voltage of output pads
V

DDI

142 supply core supply voltage
V

SSI

143 ground core ground
n.c. 144 − not connected
V

SSE

145 ground ground of output pads
WEB 146 output write enable output for bus B
UVB3 147 output bus B chrominance output to field memory 2 bit 3 (MSB)
UVB2 148 output bus B chrominance output to field memory 2 bit 2
UVB1 149 output bus B chrominance output to field memory 2 bit 1
UVB0 150 output bus B chrominance output to field memory 2 bit 0 (LSB)
YB7 151 output bus B luminance output to field memory 2 bit 7 (MSB)
YB6 152 output bus B luminance output to field memory 2 bit 6
V

DDE

153 supply supply voltage of output pads
YB5 154 output bus B luminance output to field memory 2 bit 5
YB4 155 output bus B luminance output to field memory 2 bit 4
YB3 156 output bus B luminance output to field memory 2 bit 3

SYMBOL PIN TYPE DESCRIPTION

(1)(2)

2000 Feb 04 10

Philips Semiconductors Product specification

Field and line rate converter with noise
reduction

SAA4992H

Notes

1. Not used input pins (e.g. bus E) should be connected to ground.

2. Because of the noisy characteristic of the output pad supply it is recommended not to connect the core supply and
the output pad supply directly at the device. The output pad supply should be buffered as close as possible to the
device.

3. The external pull-up resistor should be 47 kΩ.

YB2 157 output bus B luminance output to field memory 2 bit 2
YB1 158 output bus B luminance output to field memory 2 bit 1
YB0 159 output bus B luminance output to field memory 2 bit 0 (LSB)
V

SSE

160 ground ground of output pads

SYMBOL PIN TYPE DESCRIPTION

(1)(2)

2000 Feb 04 11

Philips Semiconductors Product specification

Field and line rate converter with noise
reduction

SAA4992H

handbook, full pagewidth

MHB647

SAA4992H

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18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40

120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100

99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81

V

SSE

YD0
YD1
YD2
YD3
YD4
YD5

V

DDE

YD6
YD7
UVD0
UVD1
UVD2
UVD3
WED

V

SSE

V

SSI

V

DDI

V

DDE

V

DDI

V

SSI

V

SSE

UVG0
UVG1
UVG2
UVG3
UVG4
UVG5
UVG6
UVG7

V

DDE

YG0
YG1
YG2
YG3
YG4
YG5
YG6
YG7

V

SSE

V

SSE
YC0

YC1
YC2
YC3
YC4
YC5
YC6

YC7
UVC0
UVC1
UVC2
UVC3

REC
V

SSE
V

DDE

V

SSI

V

DDI

JUMP0
JUMP1

V

DDE

V

DDI

V

SSI

RAMTST1

SNRST

SNDA
SNCL

V

SSE

RAMTST2

TEST

TRST

TMS

TDI
TDO
TCK

V

SSE

UVA0
UVA1
UVA2
UVA3

V

SSE

YB0

YB1

YB2

YB3

YB4

YB5

V

DDE

YB6

YB7

UVB0

UVB1

UVB2

UVB3

WEB

V

SSE

n.c.

V

SSIVDDI

V

DDE

n.c.

n.c.

V

DDIVSSI

n.c.

V

SSE

REE

UVE3

UVE2

UVE1

UVE0

YE7

YE6

YE5

YE4

YE3

YE2

YE1

YE0

V

SSE

UVA4

UVA5

UVA6

UVA7

YA0

YA1

YA2

YA3

YA4

YA5

YA6

YA7

REA

V

SSE

V

SSI

V

DDIVDDI

V

SSI

V

SSE

REF

YF7

YF6

YF5

YF4

YF3

YF2

YF1

YF0

V

DDE

UFV7

UFV6

UFV5

UFV4

UFV3

UFV2

UFV1

UFV0

V

SSE

CLK32

V

SSI

160

159

158

157

156

155

154

153

152

151

150

149

148

147

146

145

144

143

142

141

140

139

138

137

136

135

134

133

132

131

130

129

128

127

126

125

124

123

122

121

414243444546474849505152535455565758596061626364656667686970717273747576777879

80

Fig.3 Pin configuration.