Philips saa4992h DATASHEETS

INTEGRATED CIRCUITS

DATA SH EET

SAA4992H

Field and line rate converter with
noise reduction

Product specification
Supersedes data of 2000 Feb 04
File under Integrated Circuits, IC02

2000 May 19

Philips Semiconductors Product specification

Field and line rate converter with noise
reduction

CONTENTS

1 FEATURES
2 GENERAL DESCRIPTION
3 QUICK REFERENCE DATA
4 ORDERING INFORMATION
5 BLOCK DIAGRAMS
6 PINNING
7 FUNCTIONAL DESCRIPTION
8 CONTROL REGISTER DESCRIPTION
9 LIMITING VALUES
10 THERMAL CHARACTERISTICS
11 CHARACTERISTICS
12 PACKAGE OUTLINE
13 SOLDERING

13.1 Introduction to soldering surface mount
packages

13.2 Reflow soldering

13.3 Wave soldering

13.4 Manual soldering

13.5 Suitability of surface mount IC packages for
wave and reflow soldering methods

14 DATA SHEET STATUS
15 DEFINITIONS
16 DISCLAIMERS

SAA4992H

2000 May 19 2

Philips Semiconductors Product specification

Field and line rate converter with noise
reduction

1 FEATURES

• Upconversion of all 1fH film and video standards up to

292 active input lines per field

• 100/120 Hz 2 : 1, 50/60 Hz 1 : 1 and 100/120 Hz 1 : 1

output formats

• 4:1:1, 4:2:2 and 4 : 2 : 2 Differential Pulse Code

Modulation (DPCM) input colour formats; 4 :1:1 and
4:2:2 output colour formats

• Full 8-bit accuracy

• Scalable performance by applying 1, 2 or 3 external

field memories

• Improved recursive de-interlacing

• Film (25 Hz, 30 Hz) upconversion to 100/120

movement phases per second

• Variable vertical sharpness enhancement

• Motion compensated 3D dynamic noise reduction

• High quality vertical zoom

• 2 Mbaud serial interface (SNERT).

SAA4992H

2 GENERAL DESCRIPTION

The SAA4992H is a completely digital monolithic
integrated circuit which can be used for field and line rate
conversion of all global TV standards.

It features improved‘Natural Motion’ performance and full
film upconversion for all 50 and 60 Hz film material.

It can be configured to emulate the SAA4990H as well as
the SAA4991WP. For demonstration purposes a split
screen mode to show the Dynamic Noise Reduction
(DNR) function and a colour vector overlay is available.

The SAA4992H supports a Boundary Scan Test (BST)
circuit in accordance with IEEE 1149.

3 QUICK REFERENCE DATA

SYMBOL PARAMETER MIN. TYP. MAX. UNIT

V

DD

I

DD

f

CLK

T

amb

4 ORDERING INFORMATION

TYPE

NUMBER

SAA4992H QFP160 plastic quad flat package; 160 leads (lead length 1.6 mm);

supply voltage 3.0 3.3 3.6 V
supply current − 400 550 mA
operating clock frequency − 32 33.3 MHz
ambient temperature 0 − 70 °C

PACKAGE

NAME DESCRIPTION VERSION

SOT322-2

body 28 × 28 × 3.4 mm; high stand-off height

2000 May 19 3

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2000 May 19 4

dbook, full pagewidth

5 BLOCK DIAGRAMS

Philips Semiconductors Product specification

Field and line rate converter with noise

reduction

YA0 to YA7

SNCL

SNDA

SNRST

TCK

TDO

TDI

TMS
TRST
TEST

CLK32

45 to 52

27
26
25

35
34
33
32
31
30

79

SNERT

INTERFACE

CONTROL

BST/TEST

DYNAMIC

NOISE

REDUCTION

LEFT

MPR

FIELD MEMORY 2

YB7 to YB0
151, 152,

154 to 159

COMPRESS

MUX

MUX

DE-INTERLACER

vectors

SPM TPM ESM

MOTION ESTIMATOR

vectors

UPCONVERSION

YC0 to YC7
2 to 9

DECOMPRESS

FIELD MEMORY 3

YD7 to YD0
111, 112,

114 to 119

MPR

RIGHT

VERTICAL

PEAKING

YE0 to YE7
122 to 129

SEQUENCER

SAA4992H

VERTICAL

ZOOM

61 to 68

82 to 89

YF7 to YF0

YG7 to YG0

The solid lines represent pixel data; the broken lines represent controls.

Fig.1 Block diagram of the luminance part.

MHB645

SAA4992H

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2000 May 19 5

FIELD MEMORY 2 FIELD MEMORY 3

book, full pagewidth

Philips Semiconductors Product specification

Field and line rate converter with noise

reduction

UVA0 to UVA7

37 to 44

DECOMPRESS/

REFORMAT

DNR

MPR

LEFT

UVB3 to UVB0

147 to 150

COMPRESS/

FORMAT

UPCONVERSION

vectors

UVC0 to UVC3
10 to 13

DECOMPRESS/

REFORMAT

MPR

RIGHT

UVD3 to UVD0
107 to 110

SAA4992H

VERTICAL

ZOOM

UVE0 to UVE3

130 to 133

FORMAT

70 to 77

91 to 98

MHB646

UVF7 to YVF0

UVG7 to YVG0

SAA4992H

The solid lines represent pixel data; the broken lines represent controls.

Fig.2 Block diagram of the chrominance part.

Philips Semiconductors Product specification

Field and line rate converter with noise

SAA4992H

reduction

6 PINNING

SYMBOL PIN TYPE DESCRIPTION

V

SSE

1 ground ground of output pads
YC0 2 input bus C luminance input from field memory 2 bit 0 (LSB)
YC1 3 input bus C luminance input from field memory 2 bit 1
YC2 4 input bus C luminance input from field memory 2 bit 2
YC3 5 input bus C luminance input from field memory 2 bit 3
YC4 6 input bus C luminance input from field memory 2 bit 4
YC5 7 input bus C luminance input from field memory 2 bit 5
YC6 8 input bus C luminance input from field memory 2 bit 6
YC7 9 input bus C luminance input from field memory 2 bit 7 (MSB)
UVC0 10 input bus C chrominance input from field memory 2 bit 0 (LSB)
UVC1 11 input bus C chrominance input from field memory 2 bit 1
UVC2 12 input bus C chrominance input from field memory 2 bit 2
UVC3 13 input bus C chrominance input from field memory 2 bit 3 (MSB)
REC 14 output read enable output for busC
V
V
V
V

SSE
DDE
SSI
DDI

15 ground ground of output pads
16 supply supply voltage of output pads
17 ground core ground
18 supply core supply voltage

JUMP0 19 input configuration pin 0; will be stored in register 0B3 e.g. to indicate presence of 3rd field

memory; should be connected to ground or to V

JUMP1 20 input configuration pin 1; will be stored in register 0B5 e.g. to indicate presence of 16-bit

1st field memory for full 4:2:2; should be connected to ground or to V

pull-up resistor; note 3
V
V
V

DDE
DDI
SSI

21 supply supply voltage of output pads
22 supply core supply voltage

23 ground core ground
RAMTST1 24 input test pin 1 for internal RAM testing; connect to ground for normal operation
SNRST 25 input SNERT bus reset
SNDA 26 I/O SNERT bus data
SNCL 27 input SNERT bus clock
V

SSE

28 ground ground of output pads
RAMTST2 29 input test pin 2 for internal RAM testing; connect to ground for normal operation
TEST 30 input test mode input; if not used it has to be connected to ground
TRST 31 input boundary scan test: reset input signal; if not used it has to be connected to ground
TMS 32 input boundary scan test: test mode select; if not used it has to be connected to V

pull-up resistor; note 3

TDI 33 input boundary scan test: data input signal; if not used it has to be connected to V

pull-up resistor; note 3
TDO 34 output boundary scan test: data output signal
TCK 35 input boundary scan test: clock input signal; if not used it has to be connected to V

pull-up resistor; note 3

(1)(2)

via pull-up resistor; note 3

DDI

DDI

via

DDI

DDI

DDI

via

via

via

2000 May 19 6

Philips Semiconductors Product specification

Field and line rate converter with noise
reduction

SYMBOL PIN TYPE DESCRIPTION

V

SSE

36 ground ground of output pads
UVA0 37 input bus A chrominance input from field memory 1 bit 0 (LSB)
UVA1 38 input bus A chrominance input from field memory 1 bit 1
UVA2 39 input bus A chrominance input from field memory 1 bit 2
UVA3 40 input bus A chrominance input from field memory 1 bit 3
UVA4 41 input bus A chrominance input from field memory 1 bit 4
UVA5 42 input bus A chrominance input from field memory 1 bit 5
UVA6 43 input bus A chrominance input from field memory 1 bit 6
UVA7 44 input bus A chrominance input from field memory 1 bit 7 (MSB)
YA0 45 input bus A luminance input from field memory 1 bit 0 (LSB)
YA1 46 input bus A luminance input from field memory 1 bit 1
YA2 47 input bus A luminance input from field memory 1 bit 2
YA3 48 input bus A luminance input from field memory 1 bit 3
YA4 49 input bus A luminance input from field memory 1 bit 4
YA5 50 input bus A luminance input from field memory 1 bit 5
YA6 51 input bus A luminance input from field memory 1 bit 6
YA7 52 input bus A luminance input from field memory 1 bit 7 (MSB)
REA 53 output read enable output for bus A
V
V
V
V
V
V

SSE
SSI
DDI
DDI
SSI
SSE

54 ground ground of output pads

55 ground core ground

56 supply core supply voltage

57 supply core supply voltage

58 ground core ground

59 ground ground of output pads
REF 60 input read enable input for bus F and G
YF7 61 output bus F luminance output bit 7 (MSB)
YF6 62 output bus F luminance output bit 6
YF5 63 output bus F luminance output bit 5
YF4 64 output bus F luminance output bit 4
YF3 65 output bus F luminance output bit 3
YF2 66 output bus F luminance output bit 2
YF1 67 output bus F luminance output bit 1
YF0 68 output bus F luminance output bit 0 (LSB)
V

DDE

69 supply supply voltage of output pads
UVF7 70 output bus F chrominance output bit 7 (MSB)
UVF6 71 output bus F chrominance output bit 6
UVF5 72 output bus F chrominance output bit 5
UVF4 73 output bus F chrominance output bit 4
UVF3 74 output bus F chrominance output bit 3
UVF2 75 output bus F chrominance output bit 2
UVF1 76 output bus F chrominance output bit 1

(1)(2)

SAA4992H

2000 May 19 7

Philips Semiconductors Product specification

Field and line rate converter with noise
reduction

SYMBOL PIN TYPE DESCRIPTION

UVF0 77 output bus F chrominance output bit 0 (LSB)
V

SSE

78 ground ground of output pads
CLK32 79 input system clock input
V
V

SSI
SSE

80 ground core ground

81 ground ground of output pads
YG7 82 output bus G luminance output bit 7 (MSB)
YG6 83 output bus G luminance output bit 6
YG5 84 output bus G luminance output bit 5
YG4 85 output bus G luminance output bit 4
YG3 86 output bus G luminance output bit 3
YG2 87 output bus G luminance output bit 2
YG1 88 output bus G luminance output bit 1
YG0 89 output bus G luminance output bit 0 (LSB)
V

DDE

90 supply supply voltage of output pads
UVG7 91 output bus G chrominance output bit 7 (MSB)
UVG6 92 output bus G chrominance output bit 6
UVG5 93 output bus G chrominance output bit 5
UVG4 94 output bus G chrominance output bit 4
UVG3 95 output bus G chrominance output bit 3
UVG2 96 output bus G chrominance output bit 2
UVG1 97 output bus G chrominance output bit 1
UVG0 98 output bus G chrominance output bit 0 (LSB)
V
V
V
V
V
V
V

SSE
SSI
DDI
DDE
DDI
SSI
SSE

99 ground ground of output pads

100 ground core ground
101 supply core supply voltage
102 supply supply voltage of output pads
103 supply core supply voltage
104 ground core ground

105 ground ground of output pads
WED 106 output write enable output for bus D
UVD3 107 output bus D chrominance output to field memory 3 bit 3 (MSB)
UVD2 108 output bus D chrominance output to field memory 3 bit 2
UVD1 109 output bus D chrominance output to field memory 3 bit 1
UVD0 110 output bus D chrominance output to field memory 3 bit 0 (LSB)
YD7 111 output bus D luminance output to field memory 3 bit 7 (MSB)
YD6 112 output bus D luminance output to field memory 3 bit 6
V

DDE

113 supply supply voltage of output pads
YD5 114 output bus D luminance output to field memory 3 bit 5
YD4 115 output bus D luminance output to field memory 3 bit 4
YD3 116 output bus D luminance output to field memory 3 bit 3
YD2 117 output bus D luminance output to field memory 3 bit 2

(1)(2)

SAA4992H

2000 May 19 8

Philips Semiconductors Product specification

Field and line rate converter with noise
reduction

SYMBOL PIN TYPE DESCRIPTION

YD1 118 output bus D luminance output to field memory 3 bit 1
YD0 119 output bus D luminance output to field memory 3 bit 0 (LSB)
V
V

SSE
SSE

120 ground ground of output pads

121 ground ground of output pads
YE0 122 input bus E luminance input from field memory 3 bit 0 (LSB)
YE1 123 input bus E luminance input from field memory 3 bit 1
YE2 124 input bus E luminance input from field memory 3 bit 2
YE3 125 input bus E luminance input from field memory 3 bit 3
YE4 126 input bus E luminance input from field memory 3 bit 4
YE5 127 input bus E luminance input from field memory 3 bit 5
YE6 128 input bus E luminance input from field memory 3 bit 6
YE7 129 input bus E luminance input from field memory 3 bit 7 (MSB)
UVE0 130 input bus E chrominance input from field memory 3 bit 0 (LSB)
UVE1 131 input bus E chrominance input from field memory 3 bit 1
UVE2 132 input bus E chrominance input from field memory 3 bit 2
UVE3 133 input bus E chrominance input from field memory 3 bit 3 (MSB)
REE 134 output read enable output for bus E
V

SSE

135 ground ground of output pads
n.c. 136 − not connected
V

SSI

V

DDI

137 ground core ground

138 supply core supply voltage
n.c. 139 − not connected
n.c. 140 − not connected
V
V
V

DDE
DDI
SSI

141 supply supply voltage of output pads

142 supply core supply voltage

143 ground core ground
n.c. 144 − not connected
V

SSE

145 ground ground of output pads
WEB 146 output write enable output for bus B
UVB3 147 output bus B chrominance output to field memory 2 bit 3 (MSB)
UVB2 148 output bus B chrominance output to field memory 2 bit 2
UVB1 149 output bus B chrominance output to field memory 2 bit 1
UVB0 150 output bus B chrominance output to field memory 2 bit 0 (LSB)
YB7 151 output bus B luminance output to field memory 2 bit 7 (MSB)
YB6 152 output bus B luminance output to field memory 2 bit 6
V

DDE

153 supply supply voltage of output pads
YB5 154 output bus B luminance output to field memory 2 bit 5
YB4 155 output bus B luminance output to field memory 2 bit 4
YB3 156 output bus B luminance output to field memory 2 bit 3
YB2 157 output bus B luminance output to field memory 2 bit 2

(1)(2)

SAA4992H

2000 May 19 9

Philips Semiconductors Product specification

Field and line rate converter with noise

SAA4992H

reduction

SYMBOL PIN TYPE DESCRIPTION

YB1 158 output bus B luminance output to field memory 2 bit 1
YB0 159 output bus B luminance output to field memory 2 bit 0 (LSB)
V

SSE

Notes

1. Not used input pins (e.g. bus E) should be connected to ground.

2. Because of the noisy characteristic of the output pad supply it is recommended not to connect the core supply and
the output pad supply directly at the device. The output pad supply should be buffered as close as possible to the
device.

3. The external pull-up resistor should be 47 kΩ.

160 ground ground of output pads

(1)(2)

2000 May 19 10

Philips Semiconductors Product specification

Field and line rate converter with noise
reduction

handbook, full pagewidth

V

1

SSE

2

YC0

3

YC1

4

YC2

5

YC3

6

YC4

7

YC5

8

YC6

9

YC7

10

UVC0

11

UVC1

12

UVC2

13

UVC3

14

REC

V

15

SSE

V

16

DDE

V

17

SSI

V

18

DDI

19

JUMP0

20

JUMP1

V

21

DDE

V

22

DDI

V

23

SSI

SNRST

SNDA
SNCL

V

SSE

TEST

TRST

TMS

TDI
TDO
TCK

V

SSE

UVA0
UVA1
UVA2
UVA3

24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40

RAMTST1

RAMTST2

SSE

V
160

YB0
159

YB1
158

YB2
157

YB3
156

YB4
155

YB5
154

V

153

DDE

YB6
152

YB7
151

UVB0
150

UVB1
149

UVB2
148

UVB3
147

WEB
146

V

145

SSE

n.c.
144

SSIVDDI

DDE

V

V

n.c.

143

142

141

140

SAA4992H

n.c.
139

DDIVSSI

V

138

137

n.c.
136

V

135

SSE

REE
134

UVE3
133

UVE2
132

UVE1
131

UVE0
130

YE7
129

YE6
128

YE5
127

YE4
126

SAA4992H

YE2
124

YE1
123

YE0
122

V

121

SSE

YE3
125

120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100

V

SSE
YD0
YD1
YD2
YD3
YD4
YD5
V

DDE
YD6
YD7
UVD0
UVD1
UVD2
UVD3
WED
V

SSE
V

SSI
V

DDI
V

DDE
V

DDI
V

SSI
V

99

SSE

98

UVG0

97

UVG1

96

UVG2

95

UVG3

94

UVG4

93

UVG5

92

UVG6

91

UVG7
V

90

DDE

89

YG0

88

YG1

87

YG2

86

YG3

85

YG4

84

YG5

83

YG6

82

YG7
V

81

SSE

414243444546474849505152535455565758596061626364656667686970717273747576777879

SSI

SSI

UVA4

UVA5

UVA6

UVA7

YA0

YA1

YA2

YA3

YA4

YA5

YA6

YA7

REA

SSE

V

DDIVDDI

V

SSE

V

V

V

Fig.3 Pin configuration.

2000 May 19 11

REF

YF7

YF6

YF5

YF4

YF3

YF2

YF1

YF0

DDE

V

UFV7

UFV6

UFV5

UFV4

UFV3

UFV2

UFV1

UFV0

V

SSE

80

V

CLK32

SSI

MHB647

Philips Semiconductors Product specification

Field and line rate converter with noise
reduction

7 FUNCTIONAL DESCRIPTION

The FAL (fal_top) module builds the functional top level of
theSAA4992H.It connects the luminance data path (KER,
kernel), the chrominance data path (COL, colour) and the
luminance (de)compression (YDP, Y-DPCM) with
SAA4992H inputs and outputs as well as controlling logic
(LSE, line sequencer; SNE, SNERT interface). Outside of
fal_top there are only the pad cells, boundary scan test
cells, the boundary scan test controller, the clock tree, the
test enable tree and the input port registers.

Figure 4 shows a simplified block diagram of fal_top. It
displays the flow of pixel data (solid lines) and controls
(broken lines) between the modules inside.

Basic functionality of the modules in fal_top is as follows:

• KER (kernel): Y (luminance) data path

• COL (colour): UV (chrominance) data path

• YDP (Y-DPCM): compression (and decompression) of

luminance output (and input) data by Differential Pulse
Code Modulation (DPCM)

• LSE (line sequencer): generate line frequent control
signals

• SNE: Synchronous No parity Eight bit Reception and
Transmission (SNERT) interface to a microcontroller.

The SNERT interface operates in a slave receive and
transmit mode for communication with a microprocessor,
which resides on peripheral circuits (e.g. SAA4978H)
together with a SNERT master. The SNERT interface
transforms serial data from the microprocessor (via the
SNERT bus) into parallel data to be written into the
SAA4992Hs write registers and parallel data from
SAA4992Hsreadregisters into serial data to be sent to the
microprocessor. The SNERT bus consists of 3 signals:

1. SNCL: used as serial clock signal, generated by the

master

2. SNDA: used as bidirectional data line

3. SNRST: used as a reset signal, generated by the

microprocessor to indicate the start of a transmission.

SAA4992H

Table 1 Clock cycle references

SIGNAL LATENCY

RE_F 0
RE_C and

RE_E
YC, YE, UVC

and UVE
RE_A 94 cycles + REaShift
YA and UVA 94 cycles
YF, YG, UVF

and UVG
WE_B and

WE_D
YB, YD, UVB

and UVD

There is an algorithmic delay of 3 lines between input and
output data. Therefore, the main data output on the
F and G bus begins while the fourth input line is read.
Writing to the B and D bus starts one input line later.
The read and write enable signals RE_A, WE_B, RE_C,
WE_D and RE_E can be shifted by control registers
REaShift, WEbdShift and REceShift, which are
implemented in the line sequencer.

The fal_top module itself reads the following control
register bits(addresses):

• NrofFMs (017)

• MatrixOn (026)

• MemComp and MemDecom (026).

NrofFMs and MatrixOn are used to enable the D and G
output bus, respectively. MemComp and MemDecom are
connected to YDP to control luminance data compression
and decompression. These control register signals are not
displayed in Fig.4. Further information on the control
registers is given in Chapter 8.

63 cycles + REceShift

63 cycles

148 cycles + 3 input lines

160 cycles + 4 input lines + WEbdShift

160 cycles + 4 input lines

The processing of a video field begins on the rising edge
of the RE_F input signal. As indicated in Fig.4, the
SAA4992H expects its inputs and generates its outputs at
the following clock cycles after RE_F (see Table 1).

2000 May 19 12