Philips SAA4981T, SAA4981 Datasheet

INTEGRATED CIRCUITS

SAA4981

Monolithic integrated 16 : 9 compressor

Preliminary specification

1995 Oct 05

Supersedes data of May 1994

File under Integrated Circuits, IC02

Philips Semiconductors	Preliminary specification
Monolithic integrated 16 : 9 compressor	SAA4981

FEATURES

·Fixed horizontal compression by a factor of 4¤3 for most video standards

·Three fixed screen positions (left, centre and right)

·5 MHz bandwidth

·Bypass function

·Inputs for luminance and chrominance of side panels

·Standard video inputs and outputs (Y, (B-Y) and (R-Y))

·Horizontal and vertical sync signals are not processed

·Pre filters and post filters on chip.

GENERAL DESCRIPTION

The integrated 16 : 9 compressor is an IC which compresses the active part of a video line by a factor of 4¤3 from, for example, 52 ms to 39 ms. This is necessary to display 4:3 video software on a 16 : 9 tube in the correct proportion. The capacitively coupled video inputs are Y, (B-Y) and (R-Y).

QUICK REFERENCE DATA

The synchronisation input HREF is a line frequency reference signal. The bandwidth of the IC is up to 5 MHz and the signal delay is realized with SC Line Memories (Switched Capacitors Line Memories). The output of the 16 : 9 compressor also has the format Y, (B-Y) and (R-Y) and provides the following two possibilities:

1.Bypass function (the input signal is not compressed)

2.Compressed video by a factor of 4¤3 with three different fixed screen positions (left, centre and right). The luminance and chrominance of the side panels are determined by the external signals YSIDE, BYSIDE and RYSIDE.

The horizontal compression is a time discrete and amplitude continuous signal processing. This provides pre and post filters which are realized on-chip. The internal clock generation is achieved with a 54 MHz horizontal PLL which is synchronized to the positive edge of the HREF signal. The function of the IC is controlled by the three control signals CTRL1, CTRL2 and CTRL3.

Voltages for video signals are peak-to-peak values for 75% colour bars. All voltages are referenced to VEEA = VEED = 0 V.

SYMBOL	PARAMETER	MIN.	TYP.	MAX.	UNIT
VCCA	analog supply voltage	4.75	5.0	5.5	V
VCCD	digital supply voltage	4.75	5.0	5.5	V
ViY(p-p)	Y input voltage (peak-to-peak value)	-	0.32	0.45	V
ViU(p-p)	(B-Y) input voltage (peak-to-peak value)	-	1.33	1.9	V
ViV(p-p)	(R-Y) input voltage (peak-to-peak value)	-	1.05	1.5	V
ViHREF	input HREF top pulse	3.0	-	6.5	V
VoY(p-p)	YOUT output voltage (peak-to-peak value)	-	0.32	0.5	V
VoU(p-p)	(B-Y)OUT output voltage (peak-to-peak value)	-	1.33	2.1	V
VoV(p-p)	(R-Y)OUT output voltage (peak-to-peak value)	-	1.05	1.7	V

ORDERING INFORMATION

	TYPE NUMBER		PACKAGE
		NAME	DESCRIPTION	VERSION
	SAA4981	DIP24	plastic dual in-line package; 24 leads (600 mil)	SOT101-1
	SAA4981T	SO24	plastic small outline package; 24 leads; body width 7.5 mm	SOT137-1

1995 Oct 05

2

VCCA

VEEA

VCCD

VEED

SUB

20

19

8

7

4

23

5 MHz

SC LINE MEMORY

MUX

6.7 MHz

YIN

CLAMP

SC LINE

LOW-PASS FILTER

LOW-PASS FILTER

18

MEMORIES

MUX Y

YOUT

SC LINE MEMORY

1995Oct05

DIAGRAMBLOCK

integratedMonolithic

SemiconductorsPhilips

SAA4981

: 16

C1

C2

C3

22

5 MHz

SC LINE MEMORY

MUX

6.7 MHz

9

(B-Y)IN

CLAMP

SC LINE

17

compressor

LOW-PASS FILTER

LOW-PASS FILTER

(B-Y)OUT

MEMORIES

MUX BY

SC LINE MEMORY

C1

C2

C3

3

21

5 MHz

SC LINE MEMORY

MUX

6.7 MHz

CLAMP

(R-Y)IN

SC LINE

LOW-PASS FILTER

LOW-PASS FILTER

16

MEMORIES

(R-Y)OUT

SC LINE MEMORY

MUX RY

6

HORIZONTAL

3

C1

C2

C3

HREF

SEPARATION

C1

C2

3

CONTROLLER

54 MHz

C3

CLAMP REFERENCE

PLL

12

9

10

11

1

2

3

24

5

15

14

13

MHA277

specification Preliminary

TEST

CTRL2

BYSIDE

CTRL1

CTRL3

handbook, full pagewidth

YSIDE

RYSIDE

CLMY

CLMRY

CLAOUT

SAA4981

CLMBY

BGREF

Fig.1

Block diagram.

Philips Semiconductors	Preliminary specification
Monolithic integrated 16 : 9 compressor	SAA4981

PINNING

SYMBOL	PIN	DESCRIPTION
CLMY	1	decoupling capacitor for Y
		reference voltage
CLMBY	2	decoupling capacitor for BY
		reference voltage
CLMRY	3	decoupling capacitor for RY
		reference voltage
SUB	4	substrate connection (see Fig.5)
CLAOUT	5	internal clamping reference voltage
		output
HREF	6	horizontal reference input
VEED	7	ground for digital section
VCCD	8	positive digital supply voltage
CTRL1	9	control input 1
CTRL2	10	control input 2
CTRL3	11	control input 3
TEST	12	test mode activation
RYSIDE	13	side panel input for RY
BYSIDE	14	side panel input for BY
YSIDE	15	side panel input for Y
(R−Y)OUT	16	output signal for (R−Y)
(B−Y)OUT	17	output signal for (B−Y)
YOUT	18	output signal for Y
VEEA	19	ground for analog section
VCCA	20	positive analog supply voltage
(R−Y)IN	21	input signal for (R−Y)
(B−Y)IN	22	input signal for (B−Y)
YIN	23	input signal for Y
BGREF	24	decoupling capacitor for internal
		reference voltage

handbook, halfpage CLMY		1		24	BGREF
CLMBY		2		23	YIN
CLMRY		3		22	(B-Y)IN
SUB		4		21	(R-Y)IN
CLAOUT		5		20	VCCA
HREF		6	SAA4981	19	VEEA
VEED		7		18	YOUT
					(B−Y)OUT
VCCD		8		17
					(R−Y)OUT
CTRL1		9		16
CTRL2		10		15	YSIDE
CTRL3		11		14	BYSIDE
TEST		12		13	RYSIDE
			MHA276

Fig.2 Pin configuration.

1995 Oct 05

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Philips Semiconductors	Preliminary specification
Monolithic integrated 16 : 9 compressor	SAA4981

FUNCTIONAL DESCRIPTION

Applicable video standards

The integrated 16 : 9 compressor can be used for the following video standards; B, C, D, G, H, I, K, K1, L,

M and N. standards D, I, K, K1 and L will show a reduced video bandwidth above 5 MHz.

Clamping circuit

The clamping circuits clamp the video input signals Y, (B-Y) and (R-Y) to the DC level of the clamp reference signal fed from the clamp reference circuit. This is necessary to ensure that the input signals are in the correct input voltage range for the 5 MHz low-pass filters and the SC line memories.

Internal pre filters

Before the signals are sampled in the time discrete and amplitude continuous area, low-pass filtering is necessary to avoid any aliasing. Even if the inputs have already been low-pass filtered further filtering is advantageous for the electromagnetic compatibility (EMC). The same transfer function is used for all three low-pass filters because of the same bandwidth for the luminance and chrominance signals (up to 5 MHz).

SC line memories

After the low-pass filters the input signals are fed to the SC line memories. The signals are sampled at a clock frequency of 13.5 MHz. One video line later the signals are read with a clock frequency of 18 MHz in the compression mode. The result of the different clock frequencies is a horizontal compression by a factor of 4¤3. The clocks and the horizontal starting pulses for the SC line memories are fed from the controller.

Two line memories are required for each signal path because in the compression mode, in one video line the signals are sampled to the SC line memories with

13.5 MHz and one video line later the signals are read with 18 MHz. In the bypass mode, via the SC line memories, in one video line the signals are sampled with 13.5 MHz and one video line later the signals are read with 13.5 MHz.

The SC line memories are suitable for signals with a bandwidth up to 5 MHz. With a multiplexer (MUX) behind the SC line memories, the sampled video signal is connected to the internal post filters.

Output multiplexer MUX Y, MUX (B-Y) and MUX (R-Y)

The output multiplexers are controlled via C1 and C2 fed from the controller. The multiplexers are used to connect one of the four input signals to the output and, also, enable fast switching.

The input signals of the multiplexers for one component [Y, (B-Y) or (R-Y)] are as follows:

·The output signal of the post filter

·The uncompressed signal after the input clamping

·The clamping reference signal

·The signal for the side panel determined by YSIDE, BYSIDE and RYSIDE.

The horizontal separation circuit

The 54 MHz horizontal PLL is locked to the positive edge of the digital HREF signal, which is generated in the horizontal separation circuit. It is also possible to use the positive edge of the burst key of a sandcastle signal.

54 MHz horizontal PLL

The 13.5 MHz clock frequency for the sampling clock and the 18 MHz clock frequency for the reading clock are generated in the 54 MHz horizontal PLL. The 13.5 MHz clock and the 18 MHz clock are line locked.

Clamp reference

Reference voltages are generated In the clamp reference block. These DC signals are used in the clamping circuits as input signals for the output multiplexers and as reference voltages for the SC line memories.

Four external capacitors at the pins CLMY, CLMBY, CLMRY and BGREF respectively are necessary to provide

smoothing for the reference voltages. A black level reference signal is available at CLAOUT.

1995 Oct 05

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Philips Semiconductors	Preliminary specification
Monolithic integrated 16 : 9 compressor	SAA4981

Controller

The controller generates the clocks and the horizontal start signals for the SC line memories and, also, the control signals for the output multiplexers. The timing for the start reading signal for three different screen positions (left, centre and right) and the control signals for the multiplexers (C1 and C2) is fixed. For the uncompressed signals a bypass via the SC line memories and a bypass not via the SC line memories is available. When the signals do not pass the line memories, the frequency response is not affected by the si-function. The compression and bypass mode via the line memories is delayed by one line with respect to the bypass mode not via the line memory.

The 16 : 9 compressor is controlled via the control signals CTRL1, CTRL2 and CTRL3 (see Table 1). The test input must be LOW level.

Table 1 Functions of the control signals

CTRL1	CTRL2	CTRL3	FUNCTION
LOW	LOW	LOW	bypass (through the line
			memories)
LOW	HIGH	LOW	compression, left position
HIGH	LOW	LOW	compression, centre position
HIGH	HIGH	LOW	compression, right position
LOW	LOW	HIGH	bypass (not through the line
			memories)

Internal post filters

The output signals of the SC line memories have to be filtered with three 6.7 MHz low-pass filters to eliminate the high frequencies caused by the time discrete signal processing. The cut-off frequency of 6.7 MHz is necessary because, as a result of the 3¤4 compression factor, the frequencies are shifted to a higher frequency band with the inverse compression factor (e.g. 5 MHz ® compression ® 6.67 MHz). Due to the common bandwidth requirements for all three outputs of the SC line memories the same transfer function for the filters can be used.

Remark: These filters do not provide an si-correction. This means that an input signal with a frequency of 5 MHz will be damped by 2.1 dB at the output if the signal passes an SC line memory.

Signals for the side panels

The luminance and chrominance of the side panels is determined by the external signals YSIDE, BYSIDE and RYSIDE. This external generated side panel signal can be referenced to the internal black level reference signal via the output CLAOUT (pin 5).

Horizontal timing (see Fig.3)

The horizontal timing refers to the positive edge of the input HREF signal.

The following timing parameters are valid for a horizontal frequency of 15.625 kHz.

Input clamping typically starts at tA = 1.55 ms and ends at tB = 3.78 ms.

1995 Oct 05

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