Philips SAA4977H-V1, SAA4977H-V1-002 Datasheet

DATA SH EET

Preliminary speciﬁcation File under Integrated Circuits, IC02

1998 Jul 23

INTEGRATED CIRCUITS

SAA4977H

Besic

1998 Jul 23 2

Philips Semiconductors Preliminary speciﬁcation

Besic SAA4977H

CONTENTS

1 FEATURES 2 GENERAL DESCRIPTION 3 QUICK REFERENCE DATA 4 ORDERING INFORMATION 5 BLOCK DIAGRAM 6 PINNING INFORMATION

6.1 Pinning

6.2 Pin description 7 FUNCTIONAL DESCRIPTION

7.1 Analog-to-digital conversion

7.2 Digital processing at 1fH level

7.3 Digital processing at 2fH level

7.4 Digital-to-analog conversion

7.5 Microprocessor

7.6 Memory controller

7.7 Line locked clock generation

7.8 Clock and sync interfacing

7.9 4:1:1 I/O interfacing

7.10 Test mode operation

7.11 I2C-bus control registers 8 LIMITING VALUES 9 THERMAL CHARACTERISTICS 10 CHARACTERISTICS 11 APPLICATION 12 PACKAGE OUTLINE 13 SOLDERING

13.1 Introduction

13.2 Reflow soldering

13.3 Wave soldering

13.4 Repairing soldered joints 14 DEFINITIONS 15 LIFE SUPPORT APPLICATIONS 16 PURCHASE OF PHILIPS I2C COMPONENTS

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1 FEATURES

• Internal prefilter

• Clamp circuit

• Analog AGC

• Line locked PLL

• Triple YUV 8-bit Analog-to-Digital Converter (ADC)

• Horizontal compression

• Field rate up-conversion (50 to 100 Hz or 60 to 120 Hz)

• 4:1:1 digital I/O interface

• Digital CTI (DCTI)

• Digital luminance peaking

• Triple 10-bit Digital-to-Analog Converter (DAC)

• Memory controller

• Embedded microprocessor

• 16 kbyte ROM

• 256 byte RAM

• I

C-bus interface

• Synchronous No parity Eight bit Reception and Transmission (SNERT) interface.

2 GENERAL DESCRIPTION

The SAA4977H is a video processing IC providing analog YUV interfacing, video enhancing features, memory controlling and an embedded 80C51 microprocessor core. It is applicable especially for field rate up-conversion (50 to 100 Hz or 60 to 120 Hz) in cooperation with a

2.9 Mbit field memory. It is designed for applications

together with:

SAA4955/56TJ, TMS4C2972/73 (serial field memories) SAA4990H (PROZONIC) SAA4991WP (MELZONIC).

3 QUICK REFERENCE DATA

4 ORDERING INFORMATION

SYMBOL PARAMETER MIN. TYP. MAX. UNIT

DDA(1,2,3)

analog supply voltage front-end 4.75 5.0 5.25 V

DDD(1,2,3)

digital supply voltage front-end 4.75 5.0 5.25 V

DDA(4,5)

analog supply voltage back-end 3.15 3.3 3.45 V

DDD(4,5,6)

digital supply voltage back-end 3.15 3.3 3.45 V

DDIO

I/O supply voltage back-end 4.75 5.0 5.25 V

DDA(1,2,3)

analog supply current front-end − 85 100 mA

DDD(1,2,3)

digital supply current front-end − 65 80 mA

DDA(4,5)

analog supply current back-end − 25 35 mA

DDD(4,5,6)

digital supply current back-end − 40 55 mA

DDIO

I/O supply current back-end − 110mA

tot

total power dissipation −−1.3 W

amb

operating ambient temperature −20 − +60 °C

TYPE NUMBER

PACKAGE

NAME DESCRIPTION VERSION

SAA4977H QFP80 plastic quad ﬂat package; 80 leads (lead length 1.95 mm);

body 14 × 20 × 2.8 mm

SOT318-2

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5 BLOCK DIAGRAM

Fig.1 Block diagram.

ll pagewidth

MGM592

CLAMP

AGC

ANALOG

PREFILTER

TRIPLE

ADC

8 BIT

VARIABLE Y-DELAY

CLAMP

CORRECTION

DOWN

SAMPLING

4 : 4 : 4

4 : 1 : 1

HORIZONTAL

COMPRESSION

FORMATTER

SAA4977H

VARIABLE

Y-DELAY

REFORMATTER

SAMPLING

4 : 1 : 1

4 : 2 : 2

Y-PEAKING

DCTI

SAMPLING

4 : 2 : 2

4 : 4 : 4

BLANKING

SIDE-

PANELS

TRIPLE

DAC

10 BIT

RAM

MICROPROCESSOR

I2CBUS

SNERT-

BUS

I/O

PORT

ROM

YIN

UIN

VIN

YOUT

UOUT

VOUT

37 to 34

59 to 62

51 to 5845 to 38

YI7 to YI0YO7 to YO0

UVI7 to UVI4UVO7 to UVO4

8 44 8

CONTROL

INTERFACE

MEMORY CONTROL

(DISPLAY)

3 to 7 5

12, 13, 10

1, 2 2

P1.5

P1.1

SNDA, SNCL,

SNRST

68 9

HRD

71, 72

HDFL VDFL

BLND

63, 64

RE IE2

LLD

CONTROL

INTERFACE

MEMORY CONTROL

(ACQUISITION)

RSTW

ACQUISITION

PLL

SWC

LLA

22HA17

SELCLK

TEST

CONTROL

BLOCK

TMS

TRST

SDA,

SCL

RST

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6 PINNING INFORMATION

6.1 Pinning

Fig.2 Pin configuration.

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SAA4977H

MGM593

1 2 3 4 5 6 7 8

9 10 11 12 13 14 15 16 17 18 19 20

60 59 58 57 56

64 63 62 61

55 54 53 52 51 50 49 48 47 46 45 44 43 42 41

UVI6 UVI7 YI0 YI1 YI2

IE2 RE UVI4 UVI5

YI3 YI4 YI5 YI6 YI7

SSD3 TRST V

SSD2 SWC V

DDD3 YO7

YO6 YO5 YO4 YO3

P1.3 P1.2 P1.1

DDD5

RST

SDA

SCL P1.5 P1.4

SNRST V

DDD6 SNDA

SNCL

SSD4

TMS

SSD1

SELCLK

DDD1

DDD2

SSA1

DDA1

RSTW

21 22 23 24

DDA2

YIN

SSA2

UIN

DDA3

VIN

SSA3

LLA

UVO4

UVO5

UVO6

UVO7

YO0

YO1

YO2

DDA5

YOUT

SSA6

SSA5

UOUT

DDA4

VOUT

SSA4

VDFL

HDFL

LLD

DDD4

HRD

DDIO

BLND

SSIO

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6.2 Pin description Table 1 QFP80 package

SYMBOL PIN DESCRIPTION

SDA 1 I

C-bus serial data (P1.7)

SCL 2 I

C-bus serial clock (P1.6) P1.5 3 Port 1 data input/output signal 5 P1.4 4 Port 1 data input/output signal 4 P1.3 5 Port 1 data input/output signal 3 P1.2 6 Port 1 data input/output signal 2 P1.1 7 Port 1 data input/output signal 1 V

DDD5

8 digital supply voltage 5 (3.3 V) RST 9 microprocessor reset input SNRST 10 SNERT restart (port 1.0) V

DDD6

11 digital supply voltage 6 (3.3 V) SNDA 12 SNERT data SNCL 13 SNERT clock V

SSD4

14 digital ground 4 TMS 15 test mode select V

SSD1

16 digital ground 1 SELCLK 17 select acquisition clock input; internal PLL if HIGH, external clock if LOW V

DDD1

18 digital supply voltage 1 (5 V) V

DDD2

19 digital supply voltage 2 (5 V) VA 20 vertical synchronization input, acquisition part V

SSA1

21 analog ground 1 HA 22 analog/digital horizontal reference input V

DDA1

23 analog supply voltage 1 (5 V) RSTW 24 reset write signal output, memory 1 V

DDA2

25 analog supply voltage 2 (5 V) YIN 26 Y analog input V

SSA2

27 analog ground 2 UIN 28 U analog input V

DDA3

29 analog supply voltage 3 (5 V) VIN 30 V analog input V

SSA3

31 analog ground 3 WE 32 write enable signal output, memory 1 LLA 33 acquisition clock input UVO4 34 V digital output bit 0 UVO5 35 V digital output bit 1 UVO6 36 U digital output bit 0 UVO7 37 U digital output bit 1 YO0 38 Y digital output bit 0

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YO1 39 Y digital output bit 1 YO2 40 Y digital output bit 2 YO3 41 Y digital output bit 3 YO4 42 Y digital output bit 4 YO5 43 Y digital output bit 5 YO6 44 Y digital output bit 6 YO7 45 Y digital output bit 7 (MSB) V

DDD3

46 digital supply voltage 3 (5 V) SWC 47 serial write clock output V

SSD2

48 digital ground 2 TRST 49 test reset, active LOW V

SSD3

50 digital ground 3 YI7 51 Y digital input bit 7 (MSB) YI6 52 Y digital input bit 6 YI5 53 Y digital input bit 5 YI4 54 Y digital input bit 4 YI3 55 Y digital input bit 3 YI2 56 Y digital input bit 2 YI1 57 Y digital input bit 1 YI0 58 Y digital input bit 0 UVI7 59 U digital input bit 1 UVI6 60 U digital input bit 0 UVI5 61 V digital input bit 1 UVI4 62 V digital input bit 0 RE 63 read enable signal output, memory 1 IE2 64 input enable signal output, memory 2 V

SSIO

65 I/O ground BLND 66 horizontal blanking signal output, display part V

DDIO

67 I/O supply voltage (5 V) HRD 68 horizontal reference signal output, deﬂection part V

DDD4

69 digital supply voltage 4 (3.3 V) LLD 70 display clock input HDFL 71 horizontal synchronization signal output, deﬂection part VDFL 72 vertical synchronization signal output, deﬂection part V

SSA4

73 analog ground 4 VOUT 74 V analog output V

DDA4

75 analog supply voltage 4 (3.3 V) UOUT 76 U analog output V

SSA5

77 analog ground 5

SYMBOL PIN DESCRIPTION

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SSA6

78 analog ground 6 YOUT 79 Y analog output V

DDA5

80 analog supply voltage 5 (3.3 V)

SYMBOL PIN DESCRIPTION

7 FUNCTIONAL DESCRIPTION

7.1 Analog-to-digital conversion

7.1.1 C

LAMP CIRCUIT, CLAMPING Y TO DIGITAL LEVEL 16

AND UV TO 0 (2’S COMPLEMENT)

A clamp circuit is applied for each input channel, to map the colourless black level in each video line (on the sync back porch) to level 16 for Y and to the centre level of the converters for U and V. During the clamp period, an internally generated clamp pulse is used to switch on the clamp action. An operational transconductance amplifier like construction, which references to voltage reference points in the ladders of the ADCs, will provide a current on the input of the YUV signals, in order to bring the signals to the correct DC value. This current is proportional to the DC error, but is limited to ±100 µA. When the clamping action is off, the residual clamp current should be very low in order not to drift away within a video line.

7.1.2 G

AIN ELEMENTS FOR AUTOMATIC GAIN CONTROL

A variable amplifier is used to map the possible YUV input range to the ADC range. A rise of 6 dB up to a drop fall of 6 dB w.r.t. the nominal values can be achieved. The gain setting within this range is done digitally via control registers. For this purpose a gain setting DAC is incorporated. The smallest step in the gain setting should be hardly visible on the picture, which can be met with smallest steps of 0.4%/step.

Luminance and chrominance gain settings can be separately controlled. The reason for this split is that U and V may be gain adjusted already, whereas luminance is to be adjusted by the SAA4977H AGC. On the other hand, for RGB originated sources, Y, U and V should be adjusted with the same AGC gain.

7.1.3 A

NALOG ANTI-ALIASING PREFILTERING

A third order linear phase filter is applied on each of the Y, U and V channels. It provides a notch on f

CLK

(16 MHz) to strongly prevent aliasing to low frequencies, which would be the most disturbing. The bandwidth of the filters is designed for −3 dB at 5.6 MHz. The filters can be bypassed if external filtering with other characteristics is desired.

7.1.4 T

RIPLE 8-BIT ANALOG-TO-DIGITAL CONVERSION

Three identical ADCs are used to convert Y, U and V with 16 MHz data rate. A multi-step type ADC is applied here.

7.2 Digital processing at 1f

level

7.2.1 O

VERLOAD DETECTION

The overload detection provides information to make efficient use of the AGC. The number of overflows per video field in the luminance channel is accumulated by a 14-bit counter. The 8 MSBs of this counter can be read out by the microprocessor respectively via the I2C-bus. Overflow levels can be programmed as 216, 224, 232 and 240.

7.2.2 D

IGITAL CLAMP CORRECTION FOR UV

During 32 samples within the clamp position the clamp error is measured and accumulated to make a low-pass filtered value of the clamp error. Then a vertical recursive filter is used to further low-pass this error value. This value can be read by the microprocessor or directly be used to correct the clamp error. It is also possible to give a fixed correction value by the microprocessor.

7.2.3 4:4:4

TO 4:1:1DOWN-SAMPLING AND UV

CORING

The U and V samples from the ADC are low-pass filtered, before being subsampled with a factor of 2. Coring is applied to the subsampled signal to obtain no gain for low amplitudes which is considered to be noise. Coring levels can be programmed as 0 (off), ±1⁄2, ±1 and ±2 LSB.

The U and V samples from the 4 :2:2 data are low-pass filtered again, before being subsampled a second time with a factor of 2 and formatted to 4 :1:1 format.

7.2.4 Y-

DELAY

The Y samples can be shifted onto 8 positions w.r.t. the UV samples. This shift is meant to account for a possible difference in delay previous to the SAA4977H. The zero delay setting is suitable for the nominal case of aligned input data according to the interface format standard. The other settings provide four samples less delay to three sample more delay in Y.

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7.2.5 HORIZONTAL COMPRESSION For displaying 4 : 3 sources on 16 : 9 screens a horizontal

signal compression can be done by data interpolation. Therefore two horizontal compression factors of either

⁄3or7⁄6 are possible. Via the I2C-bus the compression can

be switched on or off and the compression mode 16 : 9 or 14 : 9 can be selected. When the compression mode is active, a reduced number of the interpolated data is stored in the field memory. To achieve sufficiently high accuracy in interpolation Variable Phase Delay filters are used (VPD10 for luminance, a multiplexed VPD06 for UV).

7.3 Digital processing at 2f

level

7.3.1 4:1:1

TO 4:2:2UP-CONVERSION

An up-converter to 4:2:2 is applied with a linear interpolation filter for creation of the extra samples. These are combined with the original samples from the 4 :1:1 stream.

7.3.2 DCTI The Digital Colour Transient Improvement (DCTI) is

intended for U and V signals originating from a 4 :1:1 source. Horizontal transients are detected and enhanced without overshoots by differentiating, make absolute and again differentiating the U and V signals separately.

This results in a 4:4:4 U and V bandwidth. To prevent third harmonic distortion, typical for this processing, a so called over the hill protection prevents peak signals becoming distorted. Via the I

C-bus it is possible to control: gain width (see Fig.4), threshold (i.e. immunity against noise), selection of simple or improved first differentiating filter (see Fig.3), limit for pixel shift range (see Fig.5), common or separate processing of U and V signals, hill protection mode (i.e. no discolourations in narrow colour gaps), low-pass filtering for U and V signals (see Fig.6) and a so called super hill mode, which avoids discolourations in transients within a colour component.

7.3.3 Y-

PEAKING

A linear peaking is applied, which amplifies the luminance signal in the middle and the upper ranges of the bandwidth.

The filtering is an addition of:

• The original signal

• The original signal high-passed with maximum gain at

frequency =1⁄2fs (8 MHz)

• The original signal band-passed with centre

frequency =1⁄4fs (4 MHz)

• The original signal band-passed with centre frequency of 2.38 MHz.

The band-passed and high-passed signals are weighted with factors 0,

⁄16,2⁄16,3⁄16,4⁄16,5⁄16,6⁄16, and8⁄16, resulting

in a maximum gain difference of 2 dB at the centre frequencies.

Coring is added to obtain no gain for low amplitudes in the high-pass and band-pass filtered signal, which is considered to be noise. Coring levels can be programmed as 0 (off), ±8, ±16, ±24 to ±120 LSB w.r.t. the (signed) 11-bit filtered signal.

In addition the peaking gain can be reduced depending on the signal amplitude, programming range 0 (no attenuation),1⁄4,2⁄4, and4⁄4. It is also possible to make larger undershoots than overshoots, programming range 0 (no attenuation of undershoots),1⁄4,2⁄4, and4⁄4.

7.3.4 Y-

DELAY

The Y samples can be shifted onto 8 positions w.r.t. the UV samples. This shift is meant to account for a possible difference in delay previous to the SAA4977H. The zero delay setting is suitable for the nominal case of aligned input data. The other settings provide one to seven samples less delay in Y.

7.3.5 S

IDEPANELS AND BLANKING

Sidepanels are generated by switching Y and the 4 MSBs of U and V to certain programmable values. The start and stop values for the sidepanels w.r.t. the rising edge of the HRD signal are programmable in a resolution of 4 LLD clock cycles. In addition, a fine shift of 0 to 3 LLD clock cycles of both values can be achieved.

Blanking is done by switching Y to value 64 at 10-bit word and UV to value 0 (in 2’s complement). Blanking is controlled by a composite signal HVBDA, consisting of a horizontal part HBDA and a vertical part VBDA. Set and reset value of the horizontal control signal HBDA are programmable w.r.t. the rising edge of the HRD signal, set and reset value of the vertical control signal VBDA are programmable w.r.t. the rising edge of the VA signal.

The range of the Y output signal can be selected between 9 and 10 bits. In the case of 9 bits for the nominal signal there is room left for undershoot and overshoot (adding up to a total of 10 bits). In the case of selecting all 10 bits of the luminance DAC for the nominal signal any under or overshoot will be clipped (see Fig.11).

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Fig.3 DCTI first differentiating filter; transfer function with variation of control signal dcti_ddx_sel.

(1) dcti_ddx_sel = 1. (2) dcti_ddx_sel = 0.

handbook, halfpage

0 0.25

0.2

MGM689

signal

amplitude

f/f

0.4

0.6

0.8

0.05 0.1 0.15 0.2

(2)(1)

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MGM690

digital signal

amplitude

samples

(1)

(5)

(4)

(3)

(2)

500

−100

−200

300

400

−300

200

−400

100

−500

Fig.4 DCTI with variation of gain setting (limit = 1).

(1) input signal. (2) gain = 1. (3) gain = 3. (4) gain = 5. (5) gain = 7.

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