Philips SAA4977H-V1, SAA4977H-V1-002 Datasheet

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INTEGRATED CIRCUITS

DATA SHEET

SAA4977H

Besic

Preliminary speciﬁcation			1998 Jul 23
File under Integrated Circuits, IC02

Philips Semiconductors	Preliminary speciﬁcation

Besic	SAA4977H

CONTENTS

1FEATURES

2GENERAL DESCRIPTION

3QUICK REFERENCE DATA

4ORDERING INFORMATION

5BLOCK DIAGRAM

6PINNING INFORMATION

6.1Pinning

6.2Pin description

7	FUNCTIONAL DESCRIPTION

7.1Analog-to-digital conversion

7.2Digital processing at 1fH level

7.3Digital processing at 2fH level

7.4Digital-to-analog conversion

7.5Microprocessor

7.6Memory controller

7.7Line locked clock generation

7.8Clock and sync interfacing

7.94 : 1 : 1 I/O interfacing

7.10Test mode operation

7.11I2C-bus control registers

8LIMITING VALUES

9THERMAL CHARACTERISTICS

10CHARACTERISTICS

11APPLICATION

12PACKAGE OUTLINE

13SOLDERING

13.1Introduction

13.2Reflow soldering

13.3Wave soldering

13.4Repairing soldered joints

14DEFINITIONS

15LIFE SUPPORT APPLICATIONS

16PURCHASE OF PHILIPS I2C COMPONENTS

1998 Jul 23

Philips Semiconductors	Preliminary speciﬁcation

Besic	SAA4977H

1 FEATURES

∙Internal prefilter

∙Clamp circuit

∙Analog AGC

∙Line locked PLL

∙Triple YUV 8-bit Analog-to-Digital Converter (ADC)

∙Horizontal compression

∙Field rate up-conversion (50 to 100 Hz or 60 to 120 Hz)

∙4 : 1 : 1 digital I/O interface

∙Digital CTI (DCTI)

∙Digital luminance peaking

∙Triple 10-bit Digital-to-Analog Converter (DAC)

∙Memory controller

∙Embedded microprocessor

∙16 kbyte ROM

∙256 byte RAM

∙I2C-bus interface

3 QUICK REFERENCE DATA

∙Synchronous No parity Eight bit Reception and Transmission (SNERT) interface.

2 GENERAL DESCRIPTION

The SAA4977H is a video processing IC providing analog YUV interfacing, video enhancing features, memory controlling and an embedded 80C51 microprocessor core. It is applicable especially for field rate up-conversion

(50 to 100 Hz or 60 to 120 Hz) in cooperation with a 2.9 Mbit field memory. It is designed for applications together with:

SAA4955/56TJ, TMS4C2972/73 (serial field memories)

SAA4990H (PROZONIC)

SAA4991WP (MELZONIC).

SYMBOL		PARAMETER		MIN.	TYP.	MAX.	UNIT

VDDA(1,2,3)	analog supply voltage front-end			4.75	5.0	5.25	V
VDDD(1,2,3)	digital supply voltage front-end			4.75	5.0	5.25	V
VDDA(4,5)	analog supply voltage back-end			3.15	3.3	3.45	V
VDDD(4,5,6)	digital supply voltage back-end			3.15	3.3	3.45	V
VDDIO	I/O supply voltage back-end			4.75	5.0	5.25	V
IDDA(1,2,3)	analog supply current front-end			−	85	100	mA
IDDD(1,2,3)	digital supply current front-end			−	65	80	mA
IDDA(4,5)	analog supply current back-end			−	25	35	mA
IDDD(4,5,6)	digital supply current back-end			−	40	55	mA
IDDIO	I/O supply current back-end			−	1	10	mA
Ptot	total power dissipation			−	−	1.3	W
Tamb	operating ambient temperature			−20	−	+60	°C
4 ORDERING INFORMATION

TYPE NUMBER			PACKAGE

	NAME		DESCRIPTION				VERSION
	NAME		DESCRIPTION				VERSION

SAA4977H	QFP80	plastic quad ﬂat package; 80 leads (lead length 1.95 mm);					SOT318-2
		body 14 × 20 × 2.8 mm

1998 Jul 23

Jul1998

pagewidthll

UVO7 to UVO4

UVI7 to UVI4

YO7 to YO0

YI7 to YI0

45 to 38

51 to 58

VARIABLE

VARIABLE Y-DELAY

Y-PEAKING

Y-DELAY

YIN

HORIZONTAL

YOUT

BLANKING

CLAMP

TRIPLE

COMPRESSION

REFORMATTER

DCTI

TRIPLE

AGC

ADC

DOWN

DAC

UOUT

UIN

SAMPLING

ANALOG

8 BIT

CLAMP

4 : 4 : 4

SAMPLING

10 BIT

CORRECTION

FORMATTER

SIDE-

PREFILTER

4 : 1 : 1

4 : 2 : 2

VIN

PANELS

VOUT

4 : 1 : 1

4 : 2 : 2

4 : 4 : 4

SAA4977H

ROM

RAM

CONTROL

MICROPROCESSOR

INTERFACE

TEST

ACQUISITION

I2C-

MEMORY CONTROL

I/O

SNERT-

CONTROL

PLL

BLOCK

(ACQUISITION)

(DISPLAY)

PORT

BUS

63,

71,

12,

3 to 7

13, 10

1, 2

MGM592

TMS

SWC

RSTW

LLD

BLND

HRD

P1.5

SNDA,

SDA,

TRST

LLA

SELCLK

HDFL

RST

SNCL,

SCL

IE2

VDFL

P1.1

SNRST

Fig.1 Block diagram.

DIAGRAM BLOCK 5

Besic

SAA4977H

Semiconductors Philips

speciﬁcation Preliminary

Philips Semiconductors	Preliminary speciﬁcation

Besic	SAA4977H

6 PINNING INFORMATION

6.1Pinning

SDA 1

SCL 2

P1.5 3

P1.4 4

P1.3 5

P1.2 6

P1.1 7

VDDD5 8 RST 9

SNRST 10

VDDD6 11 SNDA 12

SNCL 13 VSSD4 14

TMS 15

VSSD1 16

SELCLK 17

VDDD1 18 VDDD2 19

VA 20

VSSA1 21 HA 22

VDDA1 23 RSTW 24

DDA5

YOUT

SSA6

SSA5

UOUT

DDA4

VOUT

SSA4

VDFL

HDFL

LLD

DDD4

HRD

DDIO

BLND

SSIO

SAA4977H

DDA2

YIN

SSA2

UIN

DDA3

VIN

SSA3

LLA

UVO4

UVO5

UVO6

UVO7

YO0

YO1

YO2

64 IE2

63 RE

62 UVI4

61 UVI5

60 UVI6

59 UVI7

58 YI0

57 YI1

56 YI2

55 YI3

54 YI4

53 YI5

52 YI6

51 YI7

50 VSSD3

49 TRST

48 VSSD2

47 SWC

46 VDDD3

45 YO7

44 YO6

43 YO5

42 YO4

41 YO3

MGM593

Fig.2 Pin configuration.

1998 Jul 23

Philips Semiconductors		Preliminary speciﬁcation

Besic		SAA4977H

6.2 Pin description
Table 1 QFP80 package

SYMBOL	PIN	DESCRIPTION

SDA	1	I2C-bus serial data (P1.7)
SCL	2	I2C-bus serial clock (P1.6)
P1.5	3	Port 1 data input/output signal 5

P1.4	4	Port 1 data input/output signal 4

P1.3	5	Port 1 data input/output signal 3

P1.2	6	Port 1 data input/output signal 2

P1.1	7	Port 1 data input/output signal 1

VDDD5	8	digital supply voltage 5 (3.3 V)
RST	9	microprocessor reset input

SNRST	10	SNERT restart (port 1.0)

VDDD6	11	digital supply voltage 6 (3.3 V)
SNDA	12	SNERT data

SNCL	13	SNERT clock

VSSD4	14	digital ground 4
TMS	15	test mode select

VSSD1	16	digital ground 1
SELCLK	17	select acquisition clock input; internal PLL if HIGH, external clock if LOW

VDDD1	18	digital supply voltage 1 (5 V)
VDDD2	19	digital supply voltage 2 (5 V)
VA	20	vertical synchronization input, acquisition part

VSSA1	21	analog ground 1
HA	22	analog/digital horizontal reference input

VDDA1	23	analog supply voltage 1 (5 V)
RSTW	24	reset write signal output, memory 1

VDDA2	25	analog supply voltage 2 (5 V)
YIN	26	Y analog input

VSSA2	27	analog ground 2
UIN	28	U analog input

VDDA3	29	analog supply voltage 3 (5 V)
VIN	30	V analog input

VSSA3	31	analog ground 3
WE	32	write enable signal output, memory 1

LLA	33	acquisition clock input

UVO4	34	V digital output bit 0

UVO5	35	V digital output bit 1

UVO6	36	U digital output bit 0

UVO7	37	U digital output bit 1

YO0	38	Y digital output bit 0

1998 Jul 23

Philips Semiconductors				Preliminary speciﬁcation

	Besic			SAA4977H


		SYMBOL	PIN	DESCRIPTION

	YO1		39	Y digital output bit 1

	YO2		40	Y digital output bit 2

	YO3		41	Y digital output bit 3

	YO4		42	Y digital output bit 4

	YO5		43	Y digital output bit 5

	YO6		44	Y digital output bit 6

	YO7		45	Y digital output bit 7 (MSB)

	VDDD3		46	digital supply voltage 3 (5 V)
	SWC		47	serial write clock output

	VSSD2		48	digital ground 2
			49	test reset, active LOW
	TRST		49	test reset, active LOW

	VSSD3		50	digital ground 3
	YI7		51	Y digital input bit 7 (MSB)

	YI6		52	Y digital input bit 6

	YI5		53	Y digital input bit 5

	YI4		54	Y digital input bit 4

	YI3		55	Y digital input bit 3

	YI2		56	Y digital input bit 2

	YI1		57	Y digital input bit 1

	YI0		58	Y digital input bit 0

	UVI7		59	U digital input bit 1

	UVI6		60	U digital input bit 0

	UVI5		61	V digital input bit 1

	UVI4		62	V digital input bit 0

	RE		63	read enable signal output, memory 1

	IE2		64	input enable signal output, memory 2

	VSSIO		65	I/O ground
	BLND		66	horizontal blanking signal output, display part

	VDDIO		67	I/O supply voltage (5 V)
	HRD		68	horizontal reference signal output, deﬂection part

	VDDD4		69	digital supply voltage 4 (3.3 V)
	LLD		70	display clock input

	HDFL		71	horizontal synchronization signal output, deﬂection part

	VDFL		72	vertical synchronization signal output, deﬂection part

	VSSA4		73	analog ground 4
	VOUT		74	V analog output

	VDDA4		75	analog supply voltage 4 (3.3 V)
	UOUT		76	U analog output

	VSSA5		77	analog ground 5

1998 Jul 23

Philips Semiconductors		Preliminary speciﬁcation

Besic		SAA4977H


SYMBOL	PIN	DESCRIPTION

VSSA6	78	analog ground 6
YOUT	79	Y analog output

VDDA5	80	analog supply voltage 5 (3.3 V)

7 FUNCTIONAL DESCRIPTION

7.1Analog-to-digital conversion

7.1.1CLAMP CIRCUIT, CLAMPING Y TO DIGITAL LEVEL 16

AND UV TO 0 (2’S COMPLEMENT)

A clamp circuit is applied for each input channel, to map the colourless black level in each video line (on the sync back porch) to level 16 for Y and to the centre level of the converters for U and V. During the clamp period, an internally generated clamp pulse is used to switch on the clamp action. An operational transconductance amplifier like construction, which references to voltage reference points in the ladders of the ADCs, will provide a current on the input of the YUV signals, in order to bring the signals to the correct DC value. This current is proportional to the DC error, but is limited to ±100 mA. When the clamping action is off, the residual clamp current should be very low in order not to drift away within a video line.

7.1.2GAIN ELEMENTS FOR AUTOMATIC GAIN CONTROL

A variable amplifier is used to map the possible YUV input range to the ADC range. A rise of 6 dB up to a drop fall of 6 dB w.r.t. the nominal values can be achieved. The gain setting within this range is done digitally via control registers. For this purpose a gain setting DAC is incorporated. The smallest step in the gain setting should be hardly visible on the picture, which can be met with smallest steps of 0.4%/step.

Luminance and chrominance gain settings can be separately controlled. The reason for this split is that U and V may be gain adjusted already, whereas

luminance is to be adjusted by the SAA4977H AGC. On the other hand, for RGB originated sources, Y, U and V should be adjusted with the same AGC gain.

7.1.3ANALOG ANTI-ALIASING PREFILTERING

A third order linear phase filter is applied on each of the Y, U and V channels. It provides a notch on fCLK (16 MHz) to strongly prevent aliasing to low frequencies, which would be the most disturbing. The bandwidth of the filters is designed for -3 dB at 5.6 MHz. The filters can be bypassed if external filtering with other characteristics is desired.

7.1.4TRIPLE 8-BIT ANALOG-TO-DIGITAL CONVERSION

Three identical ADCs are used to convert Y, U and V with 16 MHz data rate. A multi-step type ADC is applied here.

7.2Digital processing at 1fH level

7.2.1OVERLOAD DETECTION

The overload detection provides information to make efficient use of the AGC. The number of overflows per video field in the luminance channel is accumulated by a 14-bit counter. The 8 MSBs of this counter can be read out by the microprocessor respectively via the I2C-bus. Overflow levels can be programmed as 216, 224,

232 and 240.

7.2.2DIGITAL CLAMP CORRECTION FOR UV

During 32 samples within the clamp position the clamp error is measured and accumulated to make a low-pass filtered value of the clamp error. Then a vertical recursive filter is used to further low-pass this error value. This value can be read by the microprocessor or directly be used to correct the clamp error. It is also possible to give a fixed correction value by the microprocessor.

7.2.34 : 4 : 4 TO 4 : 1 : 1 DOWN-SAMPLING AND UV

CORING

The U and V samples from the ADC are low-pass filtered, before being subsampled with a factor of 2. Coring is applied to the subsampled signal to obtain no gain for low amplitudes which is considered to be noise. Coring levels can be programmed as 0 (off), ±1¤2, ±1 and ±2 LSB.

The U and V samples from the 4 : 2 : 2 data are low-pass filtered again, before being subsampled a second time with a factor of 2 and formatted to 4 : 1 : 1 format.

7.2.4Y-DELAY

The Y samples can be shifted onto 8 positions w.r.t. the UV samples. This shift is meant to account for a possible difference in delay previous to the SAA4977H. The zero delay setting is suitable for the nominal case of aligned input data according to the interface format standard. The other settings provide four samples less delay to three sample more delay in Y.

1998 Jul 23

Philips Semiconductors	Preliminary speciﬁcation

Besic	SAA4977H

7.2.5HORIZONTAL COMPRESSION

For displaying 4 : 3 sources on 16 : 9 screens a horizontal signal compression can be done by data interpolation. Therefore two horizontal compression factors of either 4¤3 or 7¤6 are possible. Via the I2C-bus the compression can be switched on or off and the compression mode 16 : 9 or 14 : 9 can be selected. When the compression mode is active, a reduced number of the interpolated data is stored in the field memory. To achieve sufficiently high accuracy in interpolation Variable Phase Delay filters are used (VPD10 for luminance, a multiplexed VPD06 for UV).

7.3Digital processing at 2fH level

7.3.14 : 1 : 1 TO 4 : 2 : 2 UP-CONVERSION

An up-converter to 4 : 2 : 2 is applied with a linear interpolation filter for creation of the extra samples. These are combined with the original samples from the 4 : 1 : 1 stream.

7.3.2DCTI

The Digital Colour Transient Improvement (DCTI) is intended for U and V signals originating from a 4 : 1 : 1 source. Horizontal transients are detected and enhanced without overshoots by differentiating, make absolute and again differentiating the U and V signals separately.

This results in a 4 : 4 : 4 U and V bandwidth. To prevent third harmonic distortion, typical for this processing, a so called over the hill protection prevents peak signals becoming distorted. Via the I2C-bus it is possible to control: gain width (see Fig.4), threshold (i.e. immunity against noise), selection of simple or improved first differentiating filter (see Fig.3), limit for pixel shift range (see Fig.5), common or separate processing of U and V signals, hill protection mode (i.e. no discolourations in narrow colour gaps), low-pass filtering for U and V signals (see Fig.6) and a so called super hill mode, which avoids discolourations in transients within a colour component.

7.3.3Y-PEAKING

A linear peaking is applied, which amplifies the luminance signal in the middle and the upper ranges of the bandwidth.

The filtering is an addition of:

·The original signal

·The original signal high-passed with maximum gain at frequency = 1¤2fs (8 MHz)

·The original signal band-passed with centre frequency = 1¤4fs (4 MHz)

·The original signal band-passed with centre frequency of 2.38 MHz.

The band-passed and high-passed signals are weighted

with factors 0, 1¤16, 2¤16, 3¤16, 4¤16, 5¤16, 6¤16, and 8¤16, resulting in a maximum gain difference of 2 dB at the centre

frequencies.

Coring is added to obtain no gain for low amplitudes in the high-pass and band-pass filtered signal, which is considered to be noise. Coring levels can be programmed as 0 (off), ±8, ±16, ±24 to ±120 LSB w.r.t. the (signed) 11-bit filtered signal.

In addition the peaking gain can be reduced depending on the signal amplitude, programming range 0 (no attenuation), 1¤4, 2¤4, and 4¤4. It is also possible to make larger undershoots than overshoots, programming range 0 (no attenuation of undershoots), 1¤4, 2¤4, and 4¤4.

7.3.4Y-DELAY

The Y samples can be shifted onto 8 positions w.r.t. the UV samples. This shift is meant to account for a possible difference in delay previous to the SAA4977H. The zero delay setting is suitable for the nominal case of aligned input data. The other settings provide one to seven samples less delay in Y.

7.3.5SIDEPANELS AND BLANKING

Sidepanels are generated by switching Y and the 4 MSBs of U and V to certain programmable values. The start and stop values for the sidepanels w.r.t. the rising edge of the HRD signal are programmable in a resolution of 4 LLD clock cycles. In addition, a fine shift of 0 to 3 LLD clock cycles of both values can be achieved.

Blanking is done by switching Y to value 64 at 10-bit word and UV to value 0 (in 2’s complement). Blanking is controlled by a composite signal HVBDA, consisting of a horizontal part HBDA and a vertical part VBDA. Set and reset value of the horizontal control signal HBDA are programmable w.r.t. the rising edge of the HRD signal, set and reset value of the vertical control signal VBDA are programmable w.r.t. the rising edge of the VA signal.

The range of the Y output signal can be selected between 9 and 10 bits. In the case of 9 bits for the nominal signal there is room left for undershoot and overshoot (adding up to a total of 10 bits). In the case of selecting all 10 bits of the luminance DAC for the nominal signal any under or overshoot will be clipped (see Fig.11).

1998 Jul 23

Philips SAA4977H-V1, SAA4977H-V1-002 Datasheet

Philips Semiconductors	Preliminary speciﬁcation

Besic	SAA4977H

MGM689

signal amplitude

0.8

(1)(2)

0.6

0.4

0.2

0.05

0.1

0.15

0.2

0.25

f/fs

(1)dcti_ddx_sel = 1.

(2)dcti_ddx_sel = 0.

Fig.3 DCTI first differentiating filter; transfer function with variation of control signal dcti_ddx_sel.

handbook, full pagewidth		500		MGM690
		500
	digital
	signal	400
	amplitude
		300		(1)
		300		(2)
			(4)	(2)
			(4)	(3)
		200		(3)
		200	(5)
		100
		0
				samples
		−100
		−200
		−300
(1)	input signal.	−400
(2)	gain = 1.
(3)	gain = 3.	−500

(4)gain = 5.

(5)gain = 7.

Fig.4	DCTI with variation of gain setting (limit = 1).

1998 Jul 23	10

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