Philips SAA4974H-V1 Datasheet

DATA SH EET

Product specification
File under Integrated Circuits, IC02

1998 Apr 21

INTEGRATED CIRCUITS

SAA4974H

Besic without ADC

1998 Apr 21 2

Philips Semiconductors Product specification

Besic without ADC SAA4974H

CONTENTS

1 FEATURES
2 GENERAL DESCRIPTION
3 QUICK REFERENCE DATA
4 ORDERING INFORMATION
5 BLOCK DIAGRAM
6 PINNING INFORMATION

6.1 Pinning

6.2 Pin description
7 FUNCTIONAL DESCRIPTION

7.1 Digital processing at 2fH level

7.1.1 4:1:1 to 4:2:2 up-conversion

7.1.2 DCTI

7.1.3 Y-peaking

7.1.4 Y-delay

7.1.5 Sidepanels and blanking

7.2 Digital-to-analog conversion

7.3 Microprocessor

7.3.1 I2C-bus

7.3.2 SNERT-bus

7.3.3 I/O-ports

7.3.4 Watchdog timer

7.4 Memory controller

7.4.1 WE

7.4.2 RSTW

7.4.3 RE

7.4.4 IE2

7.4.5 HDFL

7.4.6 VDFL

7.4.7 BLND

7.5 Clock and sync interfacing

7.6 4:1:1 digital input interfacing

7.7 Test mode operation

7.8 I2C-bus control registers
8 LIMITING VALUES
9 THERMAL CHARACTERISTICS
10 CHARACTERISTICS
11 APPLICATION
12 PACKAGE OUTLINE
13 SOLDERING

13.1 Introduction

13.2 Reflow soldering

13.3 Wave soldering

13.4 Repairing soldered joints
14 DEFINITIONS
15 LIFE SUPPORT APPLICATIONS
16 PURCHASE OF PHILIPS I2C COMPONENTS

1998 Apr 21 3

Philips Semiconductors Product specification

Besic without ADC SAA4974H

1 FEATURES

• Field rate up-conversion (50 to 100 Hz or 60 to 120 Hz)

• 4:1:1 digital input

• Digital Colour Transient Improvement (DCTI)

• Digital luminance peaking

• Triple 10-bit Digital-to-Analog Converter (DAC)

• Memory controller

• Embedded microprocessor

• 16 kbyte ROM

• 256 byte RAM

• I

2

C-bus interface

• Synchronous No parity Eight bit Reception and
Transmission (SNERT) interface.

2 GENERAL DESCRIPTION

The SAA4974H is a video processing IC providing a digital
YUV 4:1:1 input interface, analog YUV output, video
enhancing features, memory controlling and an embedded
80C51 microprocessor core. It is applicable especially for
field rate up-conversion (50 to 100 Hz or 60 to 120 Hz) in
cooperation with a 2.9 Mbit field memory. It is designed for
applications together with:

SAA7111A, VPC3200 (video decoder)
SAA4955/56TJ, TMS4C2972/73 (serial field memories)
SAA4990H (PROZONIC)
SAA4991WP (MELZONIC).

3 QUICK REFERENCE DATA

4 ORDERING INFORMATION

SYMBOL PARAMETER MIN. TYP. MAX. UNIT

V

DDA(1,2)

analog supply voltage 3.15 3.3 3.45 V

V

DDD(1,2,3)

digital supply voltage 3.0 3.3 3.6 V

V

DDIO(1,2,3)

I/O supply voltage 4.5 5.0 5.5 V

I

DDA(1,2)

analog supply current − 25 40 mA

I

DDD(1,2,3)

digital supply current − 50 70 mA

I

DDIO(1,2,3)

I/O supply current − 10 20 mA

P

tot

total power dissipation −−0.5 W

T

amb

operating ambient temperature −20 − +70 °C

TYPE NUMBER

PACKAGE

NAME DESCRIPTION VERSION

SAA4974H QFP80 plastic quad flat package; 80 leads (lead length 1.95 mm);

body 14 × 20 × 2.8 mm

SOT318-2

1998 Apr 21 4

Philips Semiconductors Product specification

Besic without ADC SAA4974H

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5 BLOCK DIAGRAM

o

ok, full pagewidth

MGM687

SAA4974H

VARIABLE

Y-DELAY

REFORMATTER

UP-CONVERSION

4 : 1 : 1

TO

4 : 2 : 2

Y-PEAKING

DCTI

UP-CONVERSION

4 : 2 : 2

TO

4 : 4 : 4

BLANKING

SIDEPANELS

OVERLAY

RAM

MICROPROCESSOR

I2C­BUS

SNERT-

BUS

I/O

PORT

ROM

YOUT

79

UOUT

76

VOUT

74

4

8

CONTROL

INTERFACE

MEMORY CONTROL

(DISPLAY)

3 to 7
5

10 2

P1.5

to

P1.1

SNRST

13

SNCL

12

SNDA

68 9

HRD

71

HDFL

72

VDFL

66

BLND

63RE64

IE2

70

LLD

CONTROL

INTERFACE

MEMORY CONTROL

(ACQUISITION)

24

RSTW

32

WE

47

SWC

33

LLA

22HA20

VA

TEST

CONTROL

BLOCK

15

30

TMS

49

TRST

ANATEST

59 to 62

UVI7 to UVI4

51 to 58

YI7 to YI0

SCL

1

SDA

RST

TRIPLE

10-BIT DAC

Fig.1 Block diagram.

1998 Apr 21 5

Philips Semiconductors Product specification

Besic without ADC SAA4974H

6 PINNING INFORMATION

6.1 Pinning

Fig.2 Pin configuration.

handbook, full pagewidth

SAA4974H

MGM688

1
2
3
4
5
6
7
8

9
10
11
12
13
14
15
16
17
18
19
20

60
59
58
57
56

64
63
62
61

55
54
53
52
51
50
49
48
47
46
45
44
43
42
41

UVI6
UVI7
YI0
YI1
YI2

IE2
RE
UVI4

UVI5

YI3
YI4
YI5
YI6

YI7

V

SSD3

V

SSIO2
SWC
V

DDIO2
n.c.

n.c.
n.c.
n.c.
n.c.

P1.3
P1.2
P1.1

V

DDD1

RST

SDA

SCL
P1.5
P1.4

SNRST
V

DDD2
SNDA

SNCL

V

SSD1

TMS

V

SSIO1

n.c.

V

DDIO1

n.c.

VA

V

SSD2

HA

n.c.

RSTW

21
22
23
24

25

26

27

28

29

30

31

n.c.

n.c.

n.c.

n.c.

32

33

34

35

36

37

38

39

40

n.c.

n.c.

ANATEST

WE

LLA

n.c.

n.c.

n.c.

n.c.

n.c.

n.c.

n.c.

V

DDA2

YOUT

V

SSA3

V

SSA2

UOUT

V

DDA1

VOUT

V

SSA1

VDFL

HDFL

LLD

V

DDD3

HRD

V

DDIO3

BLND

V

SSIO3

80

79

78

77

76

75

74

73

72

71

70

69

68

67

66

65

TRST

1998 Apr 21 6

Philips Semiconductors Product specification

Besic without ADC SAA4974H

6.2 Pin description
Table 1 SOT318-2 package

SYMBOL PIN DESCRIPTION

SDA 1 I

2

C-bus serial data (P 1.7)

SCL 2 I

2

C-bus serial clock (P 1.6)
P1.5 3 Port 1 data input/output signal 5
P1.4 4 Port 1 data input/output signal 4
P1.3 5 Port 1 data input/output signal 3
P1.2 6 Port 1 data input/output signal 2
P1.1 7 Port 1 data input/output signal 1
V

DDD1

8 digital supply voltage 1 (3.3 V)
RST 9 microprocessor reset input
SNRST 10 SNERT restart (port 1.0)
V

DDD2

11 digital supply voltage 2 (3.3 V)
SNDA 12 SNERT data
SNCL 13 SNERT clock
V

SSD1

14 digital ground 1
TMS 15 test mode select
V

SSIO1

16 I/O ground 1
n.c. 17 not connected
V

DDIO1

18 I/O supply voltage 1 (5 V)
n.c. 19 not connected
VA 20 vertical synchronization input, acquisition part
V

SSD2

21 digital ground 2
HA 22 digital horizontal reference input
n.c. 23 not connected
RSTW 24 reset write signal output, memory 1
n.c. 25 not connected
n.c. 26 not connected
n.c. 27 not connected
n.c. 28 not connected
n.c. 29 not connected
ANATEST 30 analog test input
n.c. 31 not connected
WE 32 write enable signal output, memory 1
LLA 33 acquisition clock input
n.c. 34 not connected
n.c. 35 not connected
n.c. 36 not connected
n.c. 37 not connected
n.c. 38 not connected

1998 Apr 21 7

Philips Semiconductors Product specification

Besic without ADC SAA4974H

n.c. 39 not connected
n.c. 40 not connected
n.c. 41 not connected
n.c. 42 not connected
n.c. 43 not connected
n.c. 44 not connected
n.c. 45 not connected
V

DDIO2

46 I/O supply voltage 2 (5 V)
SWC 47 serial write clock output
V

SSIO2

48 I/O ground 2
TRST 49 test reset, LOW active
V

SSD3

50 digital ground 3
YI7 51 Y digital input bit 7 (MSB)
YI6 52 Y digital input bit 6
YI5 53 Y digital input bit 5
YI4 54 Y digital input bit 4
YI3 55 Y digital input bit 3
YI2 56 Y digital input bit 2
YI1 57 Y digital input bit 1
YI0 58 Y digital input bit 0
UVI7 59 U digital input bit 1
UVI6 60 U digital input bit 0
UVI5 61 V digital input bit 1
UVI4 62 V digital input bit 0
RE 63 read enable signal output, memory 1
IE2 64 input enable signal output, memory 2
V

SSIO3

65 I/O ground 3
BLND 66 horizontal blanking signal output, display part
V

DDIO3

67 I/O supply voltage 3 (5 V)
HRD 68 horizontal reference signal output, deflection part
V

DDD3

69 digital supply voltage 3 (3.3 V)
LLD 70 display clock input
HDFL 71 horizontal synchronization signal output, deflection part
VDFL 72 vertical synchronization signal output, deflection part
V

SSA1

73 analog ground 1
VOUT 74 V analog output
V

DDA1

75 analog supply voltage 1 (3.3 V)
UOUT 76 U analog output
V

SSA2

77 analog ground 2

SYMBOL PIN DESCRIPTION

1998 Apr 21 8

Philips Semiconductors Product specification

Besic without ADC SAA4974H

V

SSA3

78 analog ground 3
YOUT 79 Y analog output
V

DDA2

80 analog supply voltage 2 (3.3 V)

SYMBOL PIN DESCRIPTION

7 FUNCTIONAL DESCRIPTION

7.1 Digital processing at 2f

H

level

7.1.1 4:1:1

TO 4:2:2UP-CONVERSION

An up-converter to 4:2:2 is applied with a linear
interpolation filter for creation of the extra samples. These
are combined with the original samples from the 4 :1:1
stream.

7.1.2 DCTI
The Digital Colour Transient Improvement (DCTI) is

intended for U and V signals originating from a 4:1:1
source. Horizontal transients are detected and enhanced
without overshoots by differentiating, make absolute and
again differentiating the U and V signals separately. This
results in a 4:4:4 UandV bandwidth. To prevent third
harmonic distortion, typical for this processing, a so called
over the hill protection prevents peak signals to become
distorted.

Via I

2

C-bus it is possible to control: gain width (see Fig.4),
threshold (i.e. immunity against noise), selection of simple
or improved first differentiating filter (see Fig.3), limit for
pixel shift range (see Fig.5), common or separate
processing of U and V signals, hill protection mode (i.e. no
discolourations in narrow colour gaps), low-pass filtering
for U and V signals (see Fig.6) and a so called super hill
mode, which avoids discolourations in transients within a
colour component.

1998 Apr 21 9

Philips Semiconductors Product specification

Besic without ADC SAA4974H

Fig.3 DCTI first differentiating filter; transfer function with variation of control signal dcti_ddx_sel.

(1) dcti_ddx_sel = 1.
(2) dcti_ddx_sel = 0.

handbook, halfpage

0 0.25

1

0

0.2

MGM689

signal

amplitude

f/f

s

0.4

0.6

0.8

0.05 0.1 0.15 0.2

(2)(1)

Fig.4 DCTI with variation of gain setting (limit = 1).

handbook, full pagewidth

MGM690

digital
signal

amplitude

samples

(1)

(5)

(4)

(3)

(2)

500

−100

−200

300

400

−300

200

−400

100

0

−500

(1) Input signal.
(2) Gain = 1.
(3) Gain = 3.
(4) Gain = 5.
(5) Gain = 7.