Philips SAA2505H-M1 Datasheet
DATA SH EET
Preliminary specification
File under Integrated Circuits, IC01
1998 Mar 10
INTEGRATED CIRCUITS
SAA2505H
Digital multi-channel audio IC
(DUET)
1998 Mar 10 2
Philips Semiconductors Preliminary specification
Digital multi-channel audio IC (DUET) SAA2505H
FEATURES
Hardware features
• Two 40 MIPS 20-bit DSP cores
• All input and output buffer RAM is on-chip
• Program ROM on-chip for all decoding modes
• Two I
2
S-bus inputs with normal, double and quad speed
mode (slave only)
• Second serial input usable for ADC (Karaoke input)
• Three normal and double speed I2S-bus outputs (slave
and master from 256 and 384fs)
• One normal, double, quad speed I2S-bus output (slave
and master from 256 and 384fs)
• Japanese EIAJ serial input and output formats
• Sony Philips Digital Interface (SPDIF) output
• I2C-bus control (up to 400 kHz)
• 3.3 V supply with 5 V TTL compatible inputs/outputs
• Boundary scan for printed-circuit board testing.
Software features
• AC-3 up to 5.1 channels
• MPEG 2 L2 up to 7.1 channels
• MPEG 1 L2 (Video-CD) 2 channels at 44.1 kHz
• Dolby pro-logic decoding at 32, 44.1 and 48 kHz
• Output configuration for 7, 5, 4, 3, 2 and 1 channels
with or without Low Frequency Enhancement (LFE)
• Bass redirection for small satellite loudspeakers plus
subwoofer
• Karaoke voice mix
• Dynamic range compression (AC-3 and MPEG)
• Adjustable delay up to 15 ms for surround channels
(1.5 kbyte words)
• Adjustable delay up to 5 ms for centre channel
(250 words)
• Rounding to DAC word length
• Mute by pin and I
2
C-bus command
• AC-3 and MPEG bitstream information available via the
I2C-bus
• Concealment of CRC errors
• SPDIF coded output
• Fully programmable SPDIF channel status information.
APPLICATIONS
The SAA2505H is intended for all markets where a
multi-channel audio decoder for Dolby AC-3 and MPEG 2
is required.
Primary markets are for DVD video players, TV sets and
audio/video amplifiers.
GENERAL
The SAA2505H decodes multi-channel audio up to
MPEG 7.1, AC-3 5.1 and pro-logic on a dual DSP core.
The device contains all of the RAM and ROM necessary
for operation. This minimises the need for external
components and no microcode download is required.
The device is primarily intended for audio/video surround
sound amplifiers where the amplifier is connected to the
data source by means of SPDIF (IEC 60958). The input
interface is, therefore, made for SPDIF (IEC 60958) and
formatted for the I
2
S-bus.
The primary device output is PCM, sent via four I2S-bus
ports. There is also a SPDIF (IEC 60958) formatted
output.
User control is achieved via an I2C-bus. However, the
SAA2505H is capable of stand-alone operation.
1998 Mar 10 3
Philips Semiconductors Preliminary specification
Digital multi-channel audio IC (DUET) SAA2505H
QUICK REFERENCE DATA
Notes
1. Human body model: equivalent to discharging a 100 pF capacitor through a 1500 Ω resistor.
2. Machine model: equivalent to discharging a 200 pF capacitor through a 0 Ω resistor.
ORDERING INFORMATION
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
V
DDD
digital supply voltage 3.0 3.3 3.6 V
I
DDD
digital supply current − 160 − mA
V
DDA
analog supply voltage 3.0 3.3 3.6 V
I
DDA
analog supply current − tbf − mA
f
xtal
crystal frequency − 35 − MHz
T
amb
operating ambient temperature 0 − 70 °C
V
ESD
electrostatic discharge sensitivity
for all pins
note 1 −2000 − +2000 V
note 2 −300 − +300 V
TYPE
NUMBER
PACKAGE
NAME DESCRIPTION VERSION
SAA2505H QFP64 plastic quad flat package; 64 leads (lead length 1.6 mm);
body 14 × 14 × 2.7 mm
SOT393-1
1998 Mar 10 4
Philips Semiconductors Preliminary specification
Digital multi-channel audio IC (DUET) SAA2505H
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BLOCK DIAGRAM
Fig.1 Simplified block diagram.
o
k, full pagewidth
IIS0
I
2
S-bus
interface
bitstream
IEC 1397
PARSER
PRO LOGIC
NOISE
GENERATOR
MPEG2
OR
AC-3
DECODER
SWITCH
DOWNMIXING
AND
VOLUME
CONTROL
DELAY
audio clock
256 or 384f
s
PCM
AND
DOWN-
SAMPLING
IIS1
bitstream
e.g. from
microphone
L
8 channels
8 channels
microphone
L, R, C, S
R
C
LFE
LS
LT, RT
RS
LC
RC
channels
1 to 8
channels
1 to 8
I2S-BUS
OUTPUTS
SPDIF
L, R
bitstream
DOWNMIXING
MGL324
1998 Mar 10 5
Philips Semiconductors Preliminary specification
Digital multi-channel audio IC (DUET) SAA2505H
PINNING
SYMBOL PIN
DRIVE/
LOAD
(1)
TYPE DESCRIPTION
STANDALONE 1 A I select stand-alone mode input
EFO1 2 F O output flag FO1; from DSP2
EFO2 3 F O output flag FO2; from DSP2
EFO3 4 F O output flag FO3; from DSP2
EFO4 5 F O output flag FO4; from DSP1
EFO5 6 F O output flag FO5; from DSP1
EFO6 7 F O output flag FO6; from DSP1
V
SSDI
8 − S digital ground for internal logic and memories; note 2
V
DDDI
9 − S digital supply voltage for internal logic and memories (+3.3 V); note 3
EFI1 10 A I input flag FI1; toDSP2
EFI2 11 A I input flag FI2; toDSP1
EFI3 12 A I input flag FI3; toDSP1
V
DDDE
13 − S digital supply voltage for I/O cells (+3.3 V); note 4
WSO 14 G I/O word select input/output for ports 0 to 2; also used for output port 3
when not in quad mode (I
2
S-bus)
SCK 15 G I/O serial clock input/output for ports 0 to 2; also used for output port 3
when not in quad mode (I
2
S-bus)
V
SSDE
16 − S digital ground for I/O cells; note 5
SDO0 17 F O serial data output for port 0 (I
2
S-bus)
SDO1 18 F O serial data output for port 1 (I
2
S-bus)
V
DDDE
19 − S digital supply voltage for I/O cells (+3.3 V); note 4
V
SSDI
20 − S digital ground for internal logic and memories; note 2
V
DDDI
21 − S digital supply voltage for internal logic and memories (+3.3 V); note 3
V
SSDI
22 − S digital ground for internal logic and memories; note 2
V
DDDI
23 − S digital supply voltage for internal logic and memories (+3.3 V); note 3
V
DDDI
24 − S digital supply voltage for internal logic and memories (+3.3 V); note 3
V
SSDI
25 − S digital ground for internal logic and memories; note 2
V
DDDE
26 − S digital supply voltage for I/O cells (+3.3 V); note 4
SDO2 27 F O serial data output for port 2 (I
2
S-bus)
SDO3 28 F O serial data output for port 3 (I
2
S-bus)
V
SSDE
29 − S digital ground for I/O cells; note 5
WSO3 30 F O word select output for port 3; used in quad mode (I
2
S-bus)
SCKO3 31 F O serial clock output for port 3; used in quad mode (I
2
S-bus)
V
DDDE
32 − S digital supply voltage for I/O cells (+3.3 V); note 4
SDB 33 F O serial data begin output for port 3; used in quad mode (I
2
S-bus)
SPDIF 34 F O SPDIF output
V
SSDE
35 − S digital ground for I/O cells; note 5
V
SSDI
36 − S digital ground for internal logic and memories; note 2
V
DDDI
37 − S digital supply voltage for internal logic and memories (+3.3 V); note 3
1998 Mar 10 6
Philips Semiconductors Preliminary specification
Digital multi-channel audio IC (DUET) SAA2505H
Notes
1. See Table 1.
2. All V
SSDI
pins are internally connected.
3. All V
DDDI
pins are internally connected.
4. All V
DDDE
pins are internally connected.
5. All V
SSDE
pins are internally connected.
V
SSDE
38 − S digital ground for I/O cells; note 5
SYSCLK 39 E O programmable system clock output
V
DDDE
40 − S digital supply voltage for I/O cells (+3.3 V); note 4
V
DDA
41 − S analog supply voltage for crystal oscillator (+3.3 V)
CLKI 42 H I oscillator input
CLKO 43 H O oscillator output
V
SSDA
44 − S digital ground for crystal oscillator
ACLK 45 A I audio clock input for master mode
V
SSDE
46 − S digital ground for I/O cells; note 5
TDI 47 B I boundary scan test data input (this pin should be pulled HIGH for
normal operation)
TMS 48 B I boundary scan test mode select input (this pin should be pulled HIGH
for normal operation)
TCK 49 B I boundary scan test clock input
TRST 50 B I boundary scan test reset input (this pin should be pulled LOW for
normal operation)
TDO 51 B O boundary scan test data output
V
DDDI
52 − S digital supply voltage for internal logic and memories (+3.3 V); note 3
V
SSDI
53 − S digital ground for internal logic and memories; note 2
WSI 54 A I word select input for ports 0 and 1 (I
2
S-bus)
SDBI 55 A I serial data begin input for port 0 (I
2
S-bus)
SDI0 56 A I serial data input for port 0 (I
2
S-bus)
SDI1 57 A I serial data input for port 1 (I
2
S-bus)
SCKI 58 A I serial clock input for ports 0 and 1 (I
2
S-bus)
V
SSDI
59 − S digital ground for internal logic and memories; note 2
V
DDDI
60 − S digital supply voltage for internal logic and memories (+3.3 V); note 3
RESET 61 C I hardware reset
ADDR 62 A I select address input (I
2
C-bus)
SCL 63 C I serial clock input; external pull-up to +5 V (I
2
C-bus)
SDA 64 D I/O serial data input/output; external pull-up to +5 V (I
2
C-bus)
SYMBOL PIN
DRIVE/
LOAD
(1)
TYPE DESCRIPTION
1998 Mar 10 7
Philips Semiconductors Preliminary specification
Digital multi-channel audio IC (DUET) SAA2505H
Table 1 Pin drive and load descriptions
DRIVE/LOAD DESCRIPTION
A +5V tolerant input; TTL characterized with internal pull-down resistor
B +5V tolerant input; TTL characterized with internal pull-up resistor
C +5 V tolerant input; TTL Schmitt-trigger characterized
D +5 V tolerant 400 kHz (I2C-bus)
E TTL characterised +5 V tolerant 3-state output with 3 mA drive capability
F TTL characterised +5 V tolerant 3-state slew rate limited output with 3 mA drive capability
G +5 V tolerant bidirectional 3-state pin; with 3 mA output drive and slew rate limiting; TTL level input;
without pull-up or pull-down resistor
H crystal pins
Fig.2 Pin configuration.
handbook, full pagewidth
SAA2505H
MGL323
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
TMS
TDI
V
SSDE
ACLK
V
SSDA
CLKO
CLKI
V
DDA
V
DDDE
SYSCLK
V
SSDE
V
DDDI
V
SSDI
V
SSDE
SPDIF
SDB
STANDALONE
EFO1
EFO2
EFO3
EFO4
EFO5
EFO6
V
SSDI
V
DDDI
EFI1
EFI2
EFI3
V
DDDE
WSO
SCK
V
SSDE
33
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
SDA
SCL
ADDR
RESET
V
DDDIVSSDI
SCKI
SDI1
SDI0
SDBI
WSI
V
SSDIVDDDI
TDO
TRST
TCK
SDO0
SDO1
V
DDDE
V
SSDI
V
DDDI
V
SSDI
V
DDDIVDDDI
V
SSDI
V
DDDE
SDO2
SDO3VSSDE
WSO3
SCKO3
V
DDDE
49
1998 Mar 10 8
Philips Semiconductors Preliminary specification
Digital multi-channel audio IC (DUET) SAA2505H
CLOCK BUILD-UP
Up to four clocks provide the timing information for the
SAA2505H. These are as follows:
1. Data source clock
2. Data processing clock
3. I2C-bus data/control clock
4. Data sink clock.
Data source clock
Clocking of the input data is derived from the serial clock
input at pin 58 and is compliant with the I
2
S-bus and EIAJ
transfer formats. The ports are capable of operating at
normal, double and quad speed.
Data processing clock
This clock is used for data processing and internal data
transfer. The clock can either be provided by an external
clock generator having a duty cycle between 40 and 60%
or by using the internal crystal clock generator and an
external crystal. The external clock should be connected
between pins 42 (CLKI) and 43 (CLKO) (see Fig.11).
To use the internal clock a 35 MHz crystal operating on the
3rd harmonic must be connected between pins 42 and 43
(CLKI and CLKO).
A buffered version of this clock is available at pin 39
(SYSCLK). This can be optionally disabled or, a divided
version (4, 2 and 1) of the clock input at pin 42 (CLKI) can
be made available.
I
2
C-bus data/control clock
The I2C-bus control logic supports I2C-bus clock speeds
up to 400 kHz. This is supplied to pin 63 (SCL). If the
SAA2505H is in the stand-alone mode (pin 1 HIGH) no
I2C-bus clock needs to be supplied.
Data sink clock
The data sink clock source is dependant on the mode of
operation of the I
2
S-bus output ports.
In the master mode the I2S-bus clock is derived form an
external 256 or 384fs source connected to pin 45 (ACLK).
This is internally divided and used to drive the serial clock
at pins 15 and 31 (SCK and SCKO3). To ensure that the
digital outputs poses good timing qualities (jitter and
wander) pin 45 should be a connected to a high quality
timing source.
In the I
2
S-bus slave mode the output data is clocked to
pin 15. This can either be the serial clock input at pin 58
(SCKI) or a suitable external clock. When in slave mode
the signal at pin 15 is replicated at pin 31.
FUNCTIONAL DESCRIPTION
Data sinks
Coded audio data or PCM audio data can be input to both
DSPs from two slave-only serial interfaces capable of
receiving data in either I
2
S-bus or EIAJ formats. Both serial
interfaces use the same serial clock (pin 58) and word
select input (pin 54). The serial clock must be at least 32fs.
Serial data is applied to pins 56 and 57 (SDI0 and SDI1).
These pins are mode shared between the I2S-bus and
EIAJ formatted serial data. Port mode selection is
achieved via the I2C-bus interface, see Table 3.
I
2
S-BUS FORMATTED SPDIF INFORMATION
In the I2S-bus mode ‘big-endian’ data is received, MSB
justified to 1 clock period after a falling edge of the word
select output. The data stream should be formatted
according to
“IEC 60958 - SPDIF”
including the extensions
for non-PCM encoded audio data (“
IEC 61937”
).
AC-3 and MPEG coded data is formatted in 16-bit words.
These words are expected at a sample rate (fs) of 48 kHz
and thus a minimum serial clock of 1.536 MHz; two 16-bit
words per word select period. If the transmission word
length is in excess of 16 bits all additional bits are
discarded.
PCM sample lengths of up to 20-bit words are supported
with sample rates of 44.1 and 48 kHz. This mode is used
to transfer PCM and PCM with Dolby pro-logic encoded
data. Word select LOW corresponds to transmission of
data for the left channel, word select HIGH corresponds to
transmission of data for the right channel.
Pin 55 (SDBI) is reserved for a multi-channel extension to
the I2S-bus and is currently not supported.
1998 Mar 10 9
Philips Semiconductors Preliminary specification
Digital multi-channel audio IC (DUET) SAA2505H
EIAJ FORMATTED INPUTS
In EIAJ mode ‘big-endian’ data is received LSB justified to the rising edge of word select output. Formatting of the data
is identical to that used in the I2S-bus mode.
Fig.3 I2S-bus format (MSB fixed).
handbook, full pagewidth
MGL327
first
readwrite
SCK
SD MSB
WS
MSB − 1
second
readwrite
SCK
SD MSB
WS
MSB − 1
LSBLSB + 1
Fig.4 EIAJ format (LSB justified).
handbook, full pagewidth
MGL328
first first
readwrite
SCK
SD
WS
second
readwrite
SCK
SD LSB
WS
LSB + 1
LSBLSB + 1
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