Philips saa2505h DATASHEETS

INTEGRATED CIRCUITS

DATA SH EET

SAA2505H

Digital multi-channel audio IC
(DUET)

Preliminary specification
File under Integrated Circuits, IC01

1998 Mar 10

Philips Semiconductors Preliminary specification

Digital multi-channel audio IC (DUET) SAA2505H

FEATURES
Hardware features

• Two 40 MIPS 20-bit DSP cores

• All input and output buffer RAM is on-chip

• Program ROM on-chip for all decoding modes

• Two I

• Second serial input usable for ADC (Karaoke input)

• Three normal and double speed I2S-bus outputs (slave

• One normal, double, quad speed I2S-bus output (slave

• Japanese EIAJ serial input and output formats

• Sony Philips Digital Interface (SPDIF) output

• I2C-bus control (up to 400 kHz)

• 3.3 V supply with 5 V TTL compatible inputs/outputs

• Boundary scan for printed-circuit board testing.

Software features

• AC-3 up to 5.1 channels

• MPEG 2 L2 up to 7.1 channels

• MPEG 1 L2 (Video-CD) 2 channels at 44.1 kHz

• Dolby pro-logic decoding at 32, 44.1 and 48 kHz

• Output configuration for 7, 5, 4, 3, 2 and 1 channels

• Bass redirection for small satellite loudspeakers plus

• Karaoke voice mix

• Dynamic range compression (AC-3 and MPEG)

• Adjustable delay up to 15 ms for surround channels

• Adjustable delay up to 5 ms for centre channel

• Rounding to DAC word length

• Mute by pin and I

• AC-3 and MPEG bitstream information available via the

• Concealment of CRC errors

• SPDIF coded output

• Fully programmable SPDIF channel status information.

2

S-bus inputs with normal, double and quad speed

mode (slave only)

and master from 256 and 384fs)

and master from 256 and 384fs)

with or without Low Frequency Enhancement (LFE)

subwoofer

(1.5 kbyte words)

(250 words)

2

C-bus command

I2C-bus

APPLICATIONS

The SAA2505H is intended for all markets where a
multi-channel audio decoder for Dolby AC-3 and MPEG 2
is required.

Primary markets are for DVD video players, TV sets and
audio/video amplifiers.

GENERAL

The SAA2505H decodes multi-channel audio up to
MPEG 7.1, AC-3 5.1 and pro-logic on a dual DSP core.

The device contains all of the RAM and ROM necessary
for operation. This minimises the need for external
components and no microcode download is required.

The device is primarily intended for audio/video surround
sound amplifiers where the amplifier is connected to the
data source by means of SPDIF (IEC 60958). The input
interface is, therefore, made for SPDIF (IEC 60958) and
formatted for the I

2

S-bus.

The primary device output is PCM, sent via four I2S-bus
ports. There is also a SPDIF (IEC 60958) formatted
output.

User control is achieved via an I2C-bus. However, the
SAA2505H is capable of stand-alone operation.

1998 Mar 10 2

Philips Semiconductors Preliminary specification

Digital multi-channel audio IC (DUET) SAA2505H

QUICK REFERENCE DATA

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

V

DDD

I

DDD

V

DDA

I

DDA

f

xtal

T

amb

V

ESD

Notes

1. Human body model: equivalent to discharging a 100 pF capacitor through a 1500 Ω resistor.

2. Machine model: equivalent to discharging a 200 pF capacitor through a 0 Ω resistor.

digital supply voltage 3.0 3.3 3.6 V
digital supply current − 160 − mA
analog supply voltage 3.0 3.3 3.6 V
analog supply current − tbf − mA
crystal frequency − 35 − MHz
operating ambient temperature 0 − 70 °C
electrostatic discharge sensitivity

for all pins

note 1 −2000 − +2000 V
note 2 −300 − +300 V

ORDERING INFORMATION

TYPE

NUMBER

NAME DESCRIPTION VERSION

PACKAGE

SAA2505H QFP64 plastic quad flat package; 64 leads (lead length 1.6 mm);

body 14 × 14 × 2.7 mm

SOT393-1

1998 Mar 10 3

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1998 Mar 10 4

2

I

S-bus

interface

OR

L
R
C
LFE
LS
RS
LC
RC

channels

1 to 8

SWITCH

bitstream
bitstream

e.g. from

microphone

IIS0

IIS1

IEC 1397
PARSER

MPEG2

AC-3

DECODER

PCM
AND

DOWN-

SAMPLING

k, full pagewidth

LT, RT

PRO LOGIC

GENERATOR

8 channels

NOISE

microphone

L, R, C, S

8 channels

DELAY

DOWN­MIXING

AND

VOLUME

CONTROL

channels

1 to 8

audio clock

256 or 384f

I2S-BUS

OUTPUTS

s

BLOCK DIAGRAM

Digital multi-channel audio IC (DUET) SAA2505H

Philips Semiconductors Preliminary specification

bitstream

Fig.1 Simplified block diagram.

DOWN­MIXING

L, R

SPDIF

MGL324

Philips Semiconductors Preliminary specification

Digital multi-channel audio IC (DUET) SAA2505H

PINNING

SYMBOL PIN

DRIVE/

LOAD

TYPE DESCRIPTION

(1)

STANDALONE 1 A I select stand-alone mode input
EFO1 2 F O output flag FO1; from DSP2
EFO2 3 F O output flag FO2; from DSP2
EFO3 4 F O output flag FO3; from DSP2
EFO4 5 F O output flag FO4; from DSP1
EFO5 6 F O output flag FO5; from DSP1
EFO6 7 F O output flag FO6; from DSP1
V
V

SSDI
DDDI

8 − S digital ground for internal logic and memories; note 2

9 − S digital supply voltage for internal logic and memories (+3.3 V); note 3
EFI1 10 A I input flag FI1; toDSP2
EFI2 11 A I input flag FI2; toDSP1
EFI3 12 A I input flag FI3; toDSP1
V

DDDE

13 − S digital supply voltage for I/O cells (+3.3 V); note 4

WSO 14 G I/O word select input/output for ports 0 to 2; also used for output port 3

when not in quad mode (I

2

S-bus)

SCK 15 G I/O serial clock input/output for ports 0 to 2; also used for output port 3

when not in quad mode (I

V

SSDE

16 − S digital ground for I/O cells; note 5
SDO0 17 F O serial data output for port 0 (I
SDO1 18 F O serial data output for port 1 (I
V

DDDE

V

SSDI

V

DDDI

V

SSDI

V

DDDI

V

DDDI

V

SSDI

V

DDDE

19 − S digital supply voltage for I/O cells (+3.3 V); note 4

20 − S digital ground for internal logic and memories; note 2

21 − S digital supply voltage for internal logic and memories (+3.3 V); note 3

22 − S digital ground for internal logic and memories; note 2

23 − S digital supply voltage for internal logic and memories (+3.3 V); note 3

24 − S digital supply voltage for internal logic and memories (+3.3 V); note 3

25 − S digital ground for internal logic and memories; note 2

26 − S digital supply voltage for I/O cells (+3.3 V); note 4
SDO2 27 F O serial data output for port 2 (I
SDO3 28 F O serial data output for port 3 (I
V

SSDE

29 − S digital ground for I/O cells; note 5
WSO3 30 F O word select output for port 3; used in quad mode (I
SCKO3 31 F O serial clock output for port 3; used in quad mode (I
V

DDDE

32 − S digital supply voltage for I/O cells (+3.3 V); note 4
SDB 33 F O serial data begin output for port 3; used in quad mode (I

2

S-bus)

2
2

2
2

S-bus)
S-bus)

S-bus)
S-bus)

2

S-bus)

2

S-bus)

2

S-bus)
SPDIF 34 F O SPDIF output
V
V
V

SSDE
SSDI
DDDI

35 − S digital ground for I/O cells; note 5
36 − S digital ground for internal logic and memories; note 2
37 − S digital supply voltage for internal logic and memories (+3.3 V); note 3

1998 Mar 10 5

Philips Semiconductors Preliminary specification

Digital multi-channel audio IC (DUET) SAA2505H

SYMBOL PIN

V

SSDE

38 − S digital ground for I/O cells; note 5

DRIVE/

LOAD

TYPE DESCRIPTION

(1)

SYSCLK 39 E O programmable system clock output
V

DDDE

V

DDA

40 − S digital supply voltage for I/O cells (+3.3 V); note 4

41 − S analog supply voltage for crystal oscillator (+3.3 V)
CLKI 42 H I oscillator input
CLKO 43 H O oscillator output
V

SSDA

44 − S digital ground for crystal oscillator
ACLK 45 A I audio clock input for master mode
V

SSDE

46 − S digital ground for I/O cells; note 5
TDI 47 B I boundary scan test data input (this pin should be pulled HIGH for

normal operation)

TMS 48 B I boundary scan test mode select input (this pin should be pulled HIGH

for normal operation)
TCK 49 B I boundary scan test clock input
TRST 50 B I boundary scan test reset input (this pin should be pulled LOW for

normal operation)
TDO 51 B O boundary scan test data output
V

DDDI

V

SSDI

WSI 54 A I word select input for ports 0 and 1 (I
SDBI 55 A I serial data begin input for port 0 (I
SDI0 56 A I serial data input for port 0 (I
SDI1 57 A I serial data input for port 1 (I
SCKI 58 A I serial clock input for ports 0 and 1 (I
V

SSDI

V

DDDI

52 − S digital supply voltage for internal logic and memories (+3.3 V); note 3
53 − S digital ground for internal logic and memories; note 2

2

S-bus)

2

S-bus)

2

S-bus)

2

S-bus)

2

S-bus)
59 − S digital ground for internal logic and memories; note 2
60 − S digital supply voltage for internal logic and memories (+3.3 V); note 3

RESET 61 C I hardware reset
ADDR 62 A I select address input (I
SCL 63 C I serial clock input; external pull-up to +5 V (I
SDA 64 D I/O serial data input/output; external pull-up to +5 V (I

2

C-bus)

2

C-bus)

2

C-bus)

Notes

1. See Table 1.

2. All V

3. All V

4. All V

5. All V

pins are internally connected.

SSDI

pins are internally connected.

DDDI

pins are internally connected.

DDDE

pins are internally connected.

SSDE

1998 Mar 10 6

Philips Semiconductors Preliminary specification

Digital multi-channel audio IC (DUET) SAA2505H

Table 1 Pin drive and load descriptions

DRIVE/LOAD DESCRIPTION

A +5V tolerant input; TTL characterized with internal pull-down resistor
B +5V tolerant input; TTL characterized with internal pull-up resistor
C +5 V tolerant input; TTL Schmitt-trigger characterized
D +5 V tolerant 400 kHz (I2C-bus)
E TTL characterised +5 V tolerant 3-state output with 3 mA drive capability
F TTL characterised +5 V tolerant 3-state slew rate limited output with 3 mA drive capability
G +5 V tolerant bidirectional 3-state pin; with 3 mA output drive and slew rate limiting; TTL level input;

without pull-up or pull-down resistor

H crystal pins

handbook, full pagewidth

STANDALONE

EFO1
EFO2
EFO3
EFO4
EFO5
EFO6

V
V

V

DDDE

V

SSDE

SSDI

DDDI

EFI1
EFI2
EFI3

WSO

SCK

SDA

SCL

ADDR

64

63

62

1
2
3
4
5
6
7
8

9
10
11
12
13
14
15
16

RESET

V

61

DDDIVSSDI

60

59

SCKI

SDI1

SDI0

58

57

56

SAA2505H

SDBI
55

WSI
54

SSDIVDDDI

V

53

52

TDO
51

TRST
50

TCK
49

48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33

TMS
TDI

V

SSDE
ACLK
V

SSDA
CLKO

CLKI
V

DDA
V

DDDE
SYSCLK
V

SSDE
V

DDDI
V

SSDI
V

SSDE
SPDIF

SDB

17

SDO0

18

SDO1

19

DDDE

V

20

SSDI

V

DDDI

V

22

SSDI

V

23

24

DDDIVDDDI

V

21

Fig.2 Pin configuration.

1998 Mar 10 7

25

SSDI

V

26

DDDE

V

27

SDO2

28

29

SDO3VSSDE

30

WSO3

31

32

SCKO3

V

MGL323

DDDE

Philips Semiconductors Preliminary specification

Digital multi-channel audio IC (DUET) SAA2505H

2

CLOCK BUILD-UP

Up to four clocks provide the timing information for the
SAA2505H. These are as follows:

1. Data source clock

2. Data processing clock

3. I2C-bus data/control clock

4. Data sink clock.

Data source clock

Clocking of the input data is derived from the serial clock
input at pin 58 and is compliant with the I

2

S-bus and EIAJ
transfer formats. The ports are capable of operating at
normal, double and quad speed.

Data processing clock

This clock is used for data processing and internal data
transfer. The clock can either be provided by an external
clock generator having a duty cycle between 40 and 60%
or by using the internal crystal clock generator and an
external crystal. The external clock should be connected
between pins 42 (CLKI) and 43 (CLKO) (see Fig.11).

To use the internal clock a 35 MHz crystal operating on the
3rd harmonic must be connected between pins 42 and 43
(CLKI and CLKO).

A buffered version of this clock is available at pin 39
(SYSCLK). This can be optionally disabled or, a divided
version (4, 2 and 1) of the clock input at pin 42 (CLKI) can
be made available.

In the I
pin 15. This can either be the serial clock input at pin 58
(SCKI) or a suitable external clock. When in slave mode
the signal at pin 15 is replicated at pin 31.

FUNCTIONAL DESCRIPTION
Data sinks

Coded audio data or PCM audio data can be input to both
DSPs from two slave-only serial interfaces capable of
receiving data in either I
interfaces use the same serial clock (pin 58) and word
select input (pin 54). The serial clock must be at least 32fs.

Serial data is applied to pins 56 and 57 (SDI0 and SDI1).
These pins are mode shared between the I2S-bus and
EIAJ formatted serial data. Port mode selection is
achieved via the I2C-bus interface, see Table 3.

I
In the I2S-bus mode ‘big-endian’ data is received, MSB

justified to 1 clock period after a falling edge of the word
select output. The data stream should be formatted
according to
for non-PCM encoded audio data (“

AC-3 and MPEG coded data is formatted in 16-bit words.
These words are expected at a sample rate (fs) of 48 kHz
and thus a minimum serial clock of 1.536 MHz; two 16-bit
words per word select period. If the transmission word
length is in excess of 16 bits all additional bits are
discarded.

S-bus slave mode the output data is clocked to

2

S-bus or EIAJ formats. Both serial

2

S-BUS FORMATTED SPDIF INFORMATION

“IEC 60958 - SPDIF”

including the extensions

IEC 61937”

).

2

I

C-bus data/control clock

The I2C-bus control logic supports I2C-bus clock speeds
up to 400 kHz. This is supplied to pin 63 (SCL). If the
SAA2505H is in the stand-alone mode (pin 1 HIGH) no
I2C-bus clock needs to be supplied.

Data sink clock

The data sink clock source is dependant on the mode of
operation of the I

2

S-bus output ports.

In the master mode the I2S-bus clock is derived form an
external 256 or 384fs source connected to pin 45 (ACLK).
This is internally divided and used to drive the serial clock
at pins 15 and 31 (SCK and SCKO3). To ensure that the
digital outputs poses good timing qualities (jitter and
wander) pin 45 should be a connected to a high quality
timing source.

1998 Mar 10 8

PCM sample lengths of up to 20-bit words are supported
with sample rates of 44.1 and 48 kHz. This mode is used
to transfer PCM and PCM with Dolby pro-logic encoded
data. Word select LOW corresponds to transmission of
data for the left channel, word select HIGH corresponds to
transmission of data for the right channel.

Pin 55 (SDBI) is reserved for a multi-channel extension to
the I2S-bus and is currently not supported.

Philips Semiconductors Preliminary specification

Digital multi-channel audio IC (DUET) SAA2505H

handbook, full pagewidth

SCK

SD MSB

WS

SCK

SD MSB

WS

EIAJ FORMATTED INPUTS

readwrite

MSB − 1

first

readwrite

MSB − 1

second

MGL327

Fig.3 I2S-bus format (MSB fixed).

LSBLSB + 1

In EIAJ mode ‘big-endian’ data is received LSB justified to the rising edge of word select output. Formatting of the data
is identical to that used in the I2S-bus mode.

handbook, full pagewidth

SCK

SD

WS

SCK

SD LSB

WS

first first

readwrite

LSB + 1

readwrite

LSBLSB + 1

second

MGL328

Fig.4 EIAJ format (LSB justified).

1998 Mar 10 9