Philips SAA2503 Service Manual

INTEGRATED CIRCUITS

DATA SH EET

SAA2503

MPEG2 audio decoder

Objective speciﬁcation File under Integrated Circuits, IC01

1997 Jul 02

Philips Semiconductors Objective speciﬁcation

MPEG2 audio decoder SAA2503

FEATURES

• Single-chip MPEG2 multichannel audio decoder

• Decodes MPEG high quality audio:

– MPEG1 layer 2 (44.1 kHz) – MPEG2 multichannel layer 2 (48 kHz) – Supports pause frames

• Outputs 2 channels – Quasi surround down-mixing for Left and Right Dolby

surround channel (Lt and Rt) – Stereo down-mixing for stereo reproduction – Stereo signal selection – Single channel down-mixing

• Karaoke modes

• Linear PCM modes:

– Down-sampling from 96 to 48 kHz – Pass 48 kHz signals

• Bitstream input interface I2S-bus (IEC 1937 formatted)

• IEC 958 output interface (IEC 1937 formatted)

• IEC 958 output simultaneously available while decoding

MPEG2

• I2C-bus control

• Output flags for direct control

• Stand-alone operation possible (self-booting)

• No external DRAM or SRAM required

• On-chip PLL for internal clock generation

• 13.5 or 27 MHz master clock

• 100 pins plastic LQFP package

• 5 V power supply.

APPLICATIONS

This IC is mainly intended for use in Digital Versatile Disc (DVD) players. However it may also be used in any application that is able to accept an MPEG2 audio bitstreams such as:

• Set top boxes

• Multimedia PCs

• Digital television

• Next generation audio equipment.

GENERAL DESCRIPTION

The SAA2503 incorporates all necessary functions, such as MPEG2 multichannel audio decoding plus down-mixing, MPEG1 layer 2 decoding, Linear PCM (LPCM) processing all producing high quality audio. Together with the serial audio interfaces and the IEC 958 transmitter this allows for the complete audio function of a DVD player in a single chip.

ORDERING INFORMATION

TYPE

NUMBER

SAA2503HT LQFP100 plastic low proﬁle quad ﬂat package; 100 leads; body 14 x 14 x 1.4 mm SOT407-1

1997 Jul 02 2

NAME DESCRIPTION VERSION

PACKAGE

Philips Semiconductors Objective speciﬁcation

MPEG2 audio decoder SAA2503

FUNCTIONAL I/O DIAGRAM

handbook, full pagewidth

H0 to H7 HA0 to HA2 HR/W HEN HOREQ HACK/PB14

GPIO0 to GPIO3 I2CEN

BUSY MUTE

ADO

ACI

resrved (19)

MODC MODB MODA

RESET

PARALLEL

HOST

INTERFACE

SAA2503

FLAGS

IEC 958

TRANSMITTER

reset interrupt

I2C-BUS

SERIAL

HOST

INTERFACE

SERIAL

AUDIO

INTERFACE

OnCE

PLL

HA2 HA0 SDA SLK

HREQ

SDB

SCKR

WSR

SCKT

WST SDI0

SDI1 SDO0 SDO1 SDO2

DSCK/OS1

DSI/OS0

DSO

PLOCK

PCAP

PINIT

EXTAL

Fig.1 Functional I/O diagram.

1997 Jul 02 3

MGK396

Philips Semiconductors Objective speciﬁcation

MPEG2 audio decoder SAA2503

PINNING

SYMBOL PIN I/O DESCRIPTION

n.c. 1 − not connected n.c. 2 − not connected GNDA1 3 GND ground 1 for some sections of internal logic n.c. 4 − not connected n.c. 5 − not connected H7/PB7 6 I/O not used H6/PB6 7 I/O not used GNDH1 8 GND isolated ground 1 for the HI I/O drivers HOA2/PB10 9 I/O not used V

CCH1

HOA1/PB9 11 I/O not used HR/

W/PB11 12 I/O not used HEN/PB12 13 I/O not used V

CCQ1

GNDQ1 15 GND isolated ground 1 for the internal logic HACK/PB14 16 I/O not used GNDH2 17 GND isolated ground 2 for the HI I/O drivers HOA0/PB8 18 I/O not used H5/PB5 19 I/O not used V

CCH2

H4/PB4 21 I/O not used H3/PB3 22 I/O not used GNDH3 23 GND isolated ground 3 for the HI I/O drivers H2/PB2 24 I/O not used H1/PB1 25 I/O not used H0/PB0 26 I/O not used HOREQ/PB13 27 I/O not used GNDH4 28 GND isolated ground 4 for the HI I/O drivers V

CCH3

ADO 30 O digital audio data output ACI 31 I audio clock input n.c. 32 − not connected n.c. 33 − not connected n.c. 34 − not connected PLOCK 35 O HIGH when PLL is phase locked V

CCQ2

GNDQ2 37 GND isolated ground 2 for the internal logic PINIT 38 I PLL enable/disable control GNDP 39 GND ground dedicated for the PLL PCAP 40 I PLL capacitor input

10 supply isolated power supply 1 for some sections of the internal chip logic

14 supply isolated power supply 1 for the HI I/O drivers

20 supply isolated power supply 2 for the HI I/O drivers

29 supply isolated power supply 3 for the HI I/O drivers

36 supply isolated power supply 2 for some sections of the internal chip logic

1997 Jul 02 4

Philips Semiconductors Objective speciﬁcation

MPEG2 audio decoder SAA2503

SYMBOL PIN I/O DESCRIPTION

CCP

EXTAL 42 I external clock/crystal Input SCL 43 I I GNDS1 44 GND isolated ground 1 for the SHI I/O drivers SDA 45 I/O I RESET 46 I hardware reset for the microcontroller MODA 47 I mode select A MODB 48 I mode select B MODC 49 I mode select C V

CCS1

HA0 51 I/O I HA2 52 I I HREQ 53 I host request GNDS2 54 GND isolated ground 2 for the SHI I/O drivers SDO2 55 O not used SDO1 56 O not used SDO0 57 O serial data output 0 V

CCS2

SCKT 59 O transmit serial clock WST 60 O transmit word select SCKR 61 I receive serial clock GNDQ3 62 GND ground 3 dedicated for the PLL V

CCQ3

GNDS3 64 GND isolated ground 3 for the SHI I/O drivers WSR 65 I receive word select SDI1 66 I serial data input 1 SDI0 67 I not used DSO 68 O not used DSI/OS0 69 O not used DSCK/OS1 70 O not used n.c. 71 − not connected n.c. 72 − not connected n.c. 73 − not connected n.c. 74 − not connected DR 75 I not used SDB 76 I/O general purpose I/O MUTE 77 I/O general purpose I/O GNDD1 78 GND ground 1 for some sections of internal logic BUSY 79 I/O general purpose I/O I2CEN 80 I/O general purpose I/O V

CCD1

41 supply supply voltage for the Phase Locked Loop (PLL)

C-bus serial clock

C-bus data and acknowledge

50 supply isolated power supply 1 for the SHI I/O drivers

C-bus slave address 0

C-bus slave address 2

58 supply isolated power supply 2 for the SHI I/O drivers

63 supply isolated power supply 3 for some sections of the internal chip logic

81 supply isolated power supply 1 for some sections of the internal chip logic

1997 Jul 02 5

Philips Semiconductors Objective speciﬁcation

MPEG2 audio decoder SAA2503

SYMBOL PIN I/O DESCRIPTION

GPIO3 82 I/O not used GPIO2 83 I/O not used GNDD2 84 GND ground 2 for some sections of internal logic GPIO1 85 I/O not used GPIO0 86 I/O not used GNDQ4 87 GND ground 4 for some sections of internal logic V

CCQ4

n.c. 89 − not connected n.c. 90 − not connected GNDA2 91 GND ground 2 for some sections of internal logic n.c. 92 − not connected V

CCA1

n.c. 94 − not connected n.c. 95 − not connected GNDA3 96 GND ground 3 for some sections of internal logic n.c. 97 − not connected n.c. 98 − not connected n.c. 99 − not connected V

CCA2

88 supply isolated power supply 4 for some sections of the internal chip logic

93 supply isolated power supply 1 for some sections of the internal chip logic

100 supply isolated power supply 2 for some sections of the internal chip logic

1997 Jul 02 6

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