Philips SAA2500H Datasheet

INTEGRATED CIRCUITS

DATA SH EET

SAA2500

MPEG Audio Source Decoder

Preliminary speciﬁcation File under Integrated Circuits, IC01

Philips Semiconductors

September 1994

Philips Semiconductors Preliminary speciﬁcation

MPEG Audio Source Decoder SAA2500

FEATURES

• Advanced error protection

• Integrated audio post processing for control of signal

level and inter-channel crosstalk

• Demultiplexing of ancillary data in the input bitstream

• Automatic digital de-emphasis of the decoded

audio signal

• Separate master and slave inputs

• Automatic sample frequency and bit-rate switching in

master input mode

• Automatic synchronization of input and output interface clocks in master input mode

• Selectable audio output precision; 16, 18, 20 or 22 bit

• Low power consumption.

ORDERING INFORMATION

TYPE NUMBER

SAA2500H QFP44

NAME DESCRIPTION VERSION

(1)

Plastic quad flat package; 44 leads (lead length 1.3 mm); body 10 × 10 × 1.75 mm

APPLICATIONS

• Cable and satellite digital radio decoders

• Video CD

• Compact Disc Interactive (CD-I)

• Sold-state audio

• Multimedia Personal Computer (PC).

GENERAL DESCRIPTION

The SAA2500 supports all audio modes (joint stereo, stereo, single channel and dual channel) bit rates and sample frequencies of ISO/MPEG-1 layers I and II, as standardized in

PACKAGE

“ISO/IEC 11172-3”

SOT307-2

Note

1. When using IR reflow soldering it is recommended that the Drypack instructions in the

Pocketbook”

Supply of this right under any patent, or any Industrial or Intellectual Property Right, to use this IC in any ready-to-use electronic product.

(order number 9398 510 34011) are followed.

“ISO/IEC 11172-3”

audio standard Layer I or layer II compatible IC does not convey a licence nor imply a

“Quality Reference

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Philips Semiconductors Preliminary speciﬁcation

MPEG Audio Source Decoder SAA2500

BLOCK DIAGRAM

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CDSEF CDSCL

CDSWA

CDSSY

CDMEF CDMCL

CDMWS

TDI

TDO

TCK

TMS

TRST

CDS

CDM

DD1

534

39 40 38

19 20 18 21 22

15 14

DD2

PROCESSOR

TC0 TC1

MCLK

MCLKIN

MCLKOUT

7444 10 9 3242 43 24 25 23 11 12

X22IN

MCLK24

CLOCK

GENERATOR

X22OUT

FSCLK

FSCLKIN

FSCLKM

FSCLK384

L3DATA

L3MODE

DECODING

CONTROL

L3CLK

SAA2500

SYNTHESYS

SUBBAND

FILTER

BANK

AND

OUTPUT

PROCESSING

INPUT

36 35

PROCESSOR

GND

DEQUANTI-

ZATION

AND

SCALING

GND

TA TB TO TI SCK WS

URDA

STOP

RESET

29 303231332728

MGB489

Fig.1 Functional block diagram.

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MPEG Audio Source Decoder SAA2500

PINNING

SYMBOL PIN DESCRIPTION TYPE

RESET 1 master reset I FSCLK 2 sample rate clock; buffered signal O FSCLKIN 3 sample rate clock input I MCLK 4 master clock; buffered signal O V

DD1

GND 6 supply ground − MCLKOUT 7 master clock oscillator output O MCLKIN 8 master clock oscillator input or signal input I X22OUT 9 22.579 MHz clock oscillator output O X22IN 10 22.579 MHz clock oscillator input or signal input I STOP 11 stop decoding I URDA 12 unreliable data input; interrupt decoding I CDMWS 13 coded data (master input) word select output O CDMEF 14 coded data (master input) error ﬂag input I CDM 15 ISO/MPEG coded data (master input) I CDMCL 16 coded data (master input) bit clock output O GND 17 supply ground − CDSCL 18 coded data (slave input) bit clock I CDS 19 ISO/MPEG coded data (slave input) I CDSEF 20 coded data (slave input) error ﬂag I CDSWA 21 coded data (slave input) window signal I CDSSY 22 coded data (slave input) frame sync I L3CLK 23 L3 interface bit clock I L3DATA 24 L3 interface serial data I/O L3MODE 25 L3 interface address/data select input I SD 26 baseband audio I TA 27 do not connect; reserved O GND 28 supply ground − SCK 29 baseband audio data I WS 30 baseband audio data I TO 31 connect to TI (pin 32) O TI 32 connect to TO (pin 31) I TB 33 do not connect; reserved O V

DD2

TC1 35 do not connect; factory test control 1 input, with integrated pull-down resistor I TC0 36 do not connect; factory test control 0 input, with integrated pull-down resistor I TDO 37 boundary scan test data output O TRST 38 boundary scan test reset input; this pin should be connected to ground for

TCK 39 boundary scan test clock input I

5 supply voltage −

S data output O

S clock output O

S word select output O

34 supply voltage −

normal operation

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MPEG Audio Source Decoder SAA2500

SYMBOL PIN DESCRIPTION TYPE

TMS 40 boundary scan test mode select input I TDI 41 boundary scan test data input I FSCLK384 42 sample rate clock frequency indication input I FSCLKM 43 sample rate clock source selection for the master input I MCLK24 44 master clock frequency indication I

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RESET

FSCLK

FSCLKIN

MCLK

GND

MCLKOUT

MCLKIN

X22OUT

X22IN STOP

MCLK24

FSCLKM

FSCLK384

TDI

TMS

TCK

TRST

TDO

TC0

CDMEF

CDMWS

SAA2500

(QFP44)

CDM

CDMCL

GND

CDS

CDSCL

CDSEF

1 2 3 4 5 6 7 8 9

10 11

URDA

TC1

CDSSY

CDSWA

33 32 31 30 29 28 27 26 25 24 23

TB TI TO WS SCK GND TA SD L3MODE L3DATA L3CLK

MGB490

Fig.2 Pin configuration.

FUNCTIONAL DESCRIPTION Coding system

The perceptual audio encoding/decoding scheme defined within the “

ISO/IEC 11172-3 MPEG Standard”

allows for a high reduction in the amount of data needed for digital audio whilst maintaining a high perceived sound quality. The coding is based upon a psycho-acoustic model of the human auditory system. The coding scheme exploits the fact that the human ear does not perceive weak spectral components that are in the proximity (both in time and frequency) of loud components. This phenomenon is called masking.

September 1994 5

For layers I and II of ISO/MPEG the broadband audio signal spectrum is split into 32 sub-bands of equal bandwidth. For each sub-band signal a masking threshold is calculated. The sub-band samples are then re-quantized to such an accuracy that the spectral distribution of the re-quantization noise does not exceed the masking threshold. It is this reduction of representation accuracy which yields the data reduction. The re-quantized sub-band signals are multiplexed, together with ancillary information regarding the actual re-quantization, into a MPEG audio bitstream.

Philips Semiconductors Preliminary speciﬁcation

MPEG Audio Source Decoder SAA2500

During decoding, the SAA2500 de-multiplexes the MPEG audio bitstream, and with knowledge of the ancillary information, reconstructs and combines the sub-band signals into a broadband audio output signal.

Basic functionality

From a functional point of view, several blocks can be distinguished in the SAA2500. A clock generator section derives the internally and externally required clock signals from its clock inputs. The SAA2500 can switch between a master and a slave input interface to receive the coded input data. The input processor parses and de-multiplexes the input data stream. The de-quantization and scaling processor performs the transformation and scaling operations on the sample representations in the input bitstream to yield sub band domain samples.

The sub band samples are transferred via an external detour to the synthesis sub band filter bank processor. The detour can be used to process the decoded audio in the sub band domain. The baseband audio samples, reconstructed by the sub band filter bank, can be processed before being output.

The decoding control block houses the L3 control interface, and handles the response to external control signals. The L3 control interface enables the application to

configure the SAA2500, to read its decoding status, to read Ancillary Data, and so on.

Several pins are reserved for Boundary Scan Test and Scan Test purposes.

SAA2500 clocks

The SAA2500 clock interfacing is designed for application versatility. It consists of 10 signals (see Table 1).

From a functional point of view, the clock generator inside the device can be represented as shown in Fig.3.

As described above, the SAA2500 incorporates a master input interface on which it requests for coded input data itself, as well as a slave input interface for an imposed coded data input bitstream. The input interface is selected with flags MSEL0 and MSEL1, controlled via the L3 microcontroller interface.

Depending on the selected input interface, only a limited number of the three possible input clocks (MCLKIN, X22IN and FSCLKIN) is actually required. The various clock options are selected with the 3 external control signals MCLK24, FSCLKM and FSCLK384. These control signals must be stationary while the device reset signal RESET is de-activated; changing any of these 3 signals without simultaneously resetting the SAA2500 can result in malfunctioning.

Table 1 Clock interfacing signals.

SIGNAL DIRECTION FUNCTION

MCLKIN input master clock oscillator input or signal input MCLKOUT output master clock oscillator output MCLK output master clock; buffered signal MCLK24 input master clock frequency indication:

MCLK24 = 0; MCLKIN frequency is 12.288 MHz (256 × 48 kHz)

MCLK24 = 1; MCLKIN frequency is 24.576 MHz (512 × 48 kHz) X22IN input 22.5792 MHz (512 × 44.1 kHz) clock oscillator input or signal input X22OUT output 22.5792 MHz (512 × 44.1 kHz) clock oscillator output FSCLKIN input sample rate clock signal input FSCLK output sample rate clock signal; buffered signal FSCLK384 input sample rate clock signal frequency indication:

FSCLK384 = 0; FSCLKIN frequency is 256 times the sample rate

FSCLK384 = 1; FSCLKIN frequency is 384 times the sample rate FSCLKM input sample rate clock source selection when using the master input:

FSCLKM = 0; use MCLKIN or X22IN as source

FSCLKM = 1; use FSCLKIN as source

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MPEG Audio Source Decoder SAA2500

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MCLKOUT

FSCLK384

MCLK24

MCLK

MCLKIN

X22OUT

X22IN

FSCLKIN

FSCLKM

FSCLK

SCK

control

12.288 or

24.576 MHz

OSC

22.5792 MHz 256f or 384f

control

64f

MCKDIS (L3)

FCKENA (L3)

in out

C = 48 kHz C = 32 kHz

C = 44.1 kHz

CONTROL

DIVIDER

256f or 384f

256f

C = 0

C = 1

A=B

0: use master input 1: use slave input

internal master clocks

decoded sample rate index

C = 0

C = 1

to input interfaces

MSEL1 MSEL0 (L3)

MGB491

Italics: internal signal designation.

Fig.3 SAA2500 clock generator.

Crystal oscillator

The recommended crystal oscillator configuration is shown in Fig.4. The specified component values only apply to crystals with a low equivalent series resistance of <40 Ω.

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MPEG Audio Source Decoder SAA2500

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C1 =C2= 33 pF; R1=R4=1MΩ; R2=R3=1kΩ; X1 = 22.5792 MHz; X2 = 24.5760 MHzor 12.2880MHz

The specified component values only apply to crystals with a low equivalent series resistance of <40 Ω.

9 8

SAA2500

MGB492

Fig.4 Crystal oscillator components.

Clock frequencies when using the slave input

If the slave input is used (MSEL1 and MSEL0 = 10 or 11), the SAA2500 clock sources are MCLKIN and FSCLKIN and X22IN is not used. The I2S clocks SCK and WS are generated by the SAA2500 from FSCLKIN. FSCLKIN may be designated to have a frequency of 256 times (indicated by FSCLK384 = 0) or 384 times (indicated by FSCLK384 = 1) the sample frequency of the coded input data. Master clock signal MCLKIN may be chosen to have a frequency of 12.288 MHz (indicated by MCLK24 = 0) or

24.576 MHz (indicated by MCLK24 = 1). MCLKIN and FSCLKIN do not have to be phase or frequency locked. If the application is based on a sample frequency of 48 kHz or 32 kHz, and a sample rate related clock of 12.288 MHz (256 × 48 kHz; 384 × 32 kHz) is available, this can be taken advantage of by using this signal for both MCLKIN and FSCLKIN.

Clock frequencies when using the master input

If the master input is used (MSEL1 and MSEL0 = 00), one out of two configurations is selected with signal FSCLKM with respect to the clock sources:

1. If FSCLKM = 0, MCLKIN and X22IN are the clock sources. FSCLKIN is not used in this configuration. FSCLK384 must be set to 0 for reasons of internal connections in the clock generator circuitry. MCLKIN may have only frequency 24.576 MHz (so mandatory accompanied by MCLK24 = 1), and X22IN must have a frequency of 22.5792 MHz. MCLKIN and X22IN do not have to be phase or frequency locked. The main

advantage of this configuration is that the SAA2500 determines automatically which sample rate is active from the sampling rate setting of the input data bitstream, and then selects either MCLKIN or X22IN

as the clock source for the I

S clocks SCK and WS. This configuration is therefore particularly suited in applications with more than one possible sample rate setting.

2. If FSCLKM = 1, the configuration is comparable to the configuration when using the slave input (see Section “Clock frequencies when using the slave input”). MCLKIN and FSCLKIN are used as the clock sources, and X22IN is not required. MCLKIN may again have a frequency of 12.288 MHz (indicated by MCLK24 = 0) or 24.576 MHz (indicated by MCLK24 = 1), and FSCLKIN may have a frequency of 256 times (indicated by FSCLK384 = 0) or 384 times (indicated by FSCLK384 = 1) the sample frequency of the input data. MCLKIN and FSCLKIN do not have to be phase or frequency locked.

Target applications; applying the SAA2500 with 2 ISO/MPEG sources

In Table 2 the three target applications of the SAA2500 are summarised. The slave input application is labelled S, and the master input applications are labelled M0 and M1.

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MPEG Audio Source Decoder SAA2500

Table 2 Target applications.

ATTRIBUTE CONDITIONS

APPLICATION

SM0M1

INPUT INTERFACE CONDITIONS SLAVE INPUT MASTER INPUT MASTER INPUT

FSCLKM X 0 1 MCLKIN MCLK24 = 1 24.576 MHz 24.576 MHz 24.576 MHz

MCLK24 = 0 12.288 MHz illegal 12.288 MHz X22IN note 1 22.579 MHz note 1 FSCLKIN FSCLK384 = 1 384f

FSCLK384 = 0 256f

s s

FSCLK FCKENA = 1 (L3) copy of FSCLKIN 256f

illegal 384f

note 1 256f

copy of FSCLKIN

s s

Remarks note 2 note 3 −

Notes

1. Must be electrically defined; e.g.: LOW.

2. FSCLKIN must be locked to input data clock CDSCL; see Section “The coded data slave input interface”.

3. FSCLKIN is not used, but FSCLK384 must be LOW. Sections “Clock frequencies when using the slave

input” and “Clock frequencies when using the master input” explain which clock sources are activated by the

format bit rate. Several aspects of the decoding process, as well as the audio post-processing features, offered by

the SAA2500, are described in more detail below. SAA2500 depending on the selected input interface. This automatic clock source selection makes it easy to apply the SAA2500 in systems with two ISO/MPEG coded data sources (one connected to the master input, an one to the slave input), even if these data sources use different clocks.

Buffered clock outputs

The SAA2500 provides a signal MCLK which is a buffered version of MCLKIN. MCLK can be set to 3-state by setting the L3 control interface flag MCKDIS to 1 in applications where MCLK is not needed.

Signal FSCLK is copied from the FSCLKIN input for application types S and M1 or generated with a frequency of 256f

by the SAA2500 for application type M0. After a

device reset, FSCLK must be enabled explicitly by setting L3 flag FCKENA, or can alternatively be left 3-stated in applications where it is not needed.

After a device reset, MCLK is enabled; FSCLK is disabled (i.e. both MCKDIS and FCKENA are set to 0).

Functionality issues

Synchronization to input data bitstreams

After a reset, the SAA2500 mutes both sub band and

baseband audio data. After data inputting has started, the

SAA2500 searches either for a sync pattern or a sync

pulse. The speed at which input data is read by the master

input to search for synchronisation is described below. If

the application is such that the SAA2500 starts at a

random moment in time compared to the bitstream,

maximal one frame is skipped before a synchronisation

pattern or pulse is encountered.

When the SAA2500 has detected the first synchronisation

word or pulse, a number of frames are decoded in order to

verify synchronisation; the input data for these frames is

read and decoded, but meanwhile the audio output is

muted. The number of muted frames depends on whether

the ISO/MPEG CRC is active, and whether the bit rate is

free format. If the synchronisation is found to be false, the

SAA2500 resumes the initial synchronisation as described

above. If the detected pulse/pattern is concluded to be a

real synchronisation pulse/pattern, Table 3 indicates the

number of muted frames.

The SAA2500 fully complies with ISO/MPEG layer I and II with the slave input. With the master input, the SAA2500 complies with ISO/MPEG layer I and II, excluding the free

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MPEG Audio Source Decoder SAA2500

Table 3 Muted frames.

MINIMUM NUMBER OF MUTED FRAMES

CRC

No CRC 2 1 CRC 1 0

Table 4 Defaults master input bit rate.

FSCLKM FSCLK384 FSCLKIN

00 X 1 0 256 × 32 kHz 278.64

DURING SYNCHRONIZATION

FREE FORMA T BIT

RA TE

NON-FREE-FORMA T

BIT RATE

1 384 × 32 kHz 0 256 × 44.1 kHz 384 1 384 × 44.1 kHz 0 256 × 48 kHz 417.96 1 384 × 48 kHz

Master input bit rate selection

As explained above, the SAA2500 can be used to

alternate between two applications: one with the slave

input, and one with the master input. When using the

master input, the SAA2500 should fetch data with the

effective bit rate, but cannot know what the bit rate of the

input data is until it has established synchronisation. To

overcome this paradox, the input requesting is done at the

last selected bit rate.

After a device reset, the master input bit rate selection

defaults to the value indicated in Table 4.

DEFAULT MASTER INPUT

BIT RATE kbits/s

(1)

384

Note

1. X = don’t care.

When FSCLKM = 0, the default master input bit rate is 384 kbits/s. When FSCLKM = 1, the SAA2500 uses signal FSCLKIN to derive the selected bit rate, but it has no indication concerning the sample rate corresponding to FSCLKIN. Therefore, a bit rate of 384 kbits/s is selected at an assumed sample rate of 44.1 kHz; with other sample rates, the bit rate changes proportionally.

The consequence is that while the SAA2500 synchronises (e.g. after a device reset), the application must at least be able to supply at the given default bit rate the required number of frames plus one additional frame (because of the random decoding start point in the input bitstream). Buffers in the application must thus be chosen sufficiently large to prevent under or overflows.

The speed with which input data is requested by the master input is changed by the SAA2500 in each of the following cases:

1. When input synchronization is established after

checking a number of frames and the bit rate index of the newly decoded bitstream indicates a different bit rate than that currently selected. In this case, the bit rate is adapted to the newly decoded index.

2. When the active input interface is changed from the master to the slave input, or the signal STOP is activated; in these cases input requesting stops.

3. When the active input interface is changed from the slave to the master input, or the signal STOP is deactivated; the bit rate is set to the last selected master input bit rate (the last selected master input bit rate is memorised while using the slave input).

In all other cases (e.g. when the SAA2500 goes and stays out of synchronisation), the data requesting speed of the master input is maintained.

Sample rate selection

When using the slave input, or when using the master input with FSCLKM = 1, the application must know the sample rate: FSCLKIN must be applied, which has a frequency which is a multiple of the sample rate; the (sample rate dependent) I are generated from FSCLKIN. These configurations will normally be used in applications with a fixed sample rate. Should the sample rate change, then the SAA2500 must be reset.

S timing signals SCK and WS

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MPEG Audio Source Decoder SAA2500

When using the master input with FSCLKM = 0, the SAA2500 selects the active sample rate autonomously, and generates the signals SCK and WS from its crystal clocks. After a device reset, the SAA2500 selects a sample rate of 44.1 kHz by default.

SCK and WS may, and will only, show phase or frequency changes in any of the following 3 situations:

1. When the SAA2500 establishes synchronization with the coded data input bitstream.

2. When the active input interface is changed from the master input with FSCLKM = 0 to the slave input (i.e. the timing source for the generation of SCK and WS is switched from the crystal clocks to FSCLKIN).

3. When the active input interface is changed from the slave input to the master input with FSCLKM = 0 (i.e. the timing source for the generation of SCK and WS is switched from FSCLKIN to the crystal clocks); the sample rate is set to the last selected sample rate that was used with the master input (the last selected sample rate is memorised while using the slave input).

In all other cases, SCK and WS keep on running without phase or frequency changes, and the sample rate selection remains unchanged.

Handling of errors in the coded input data

The SAA2500 can handle errors in the input data. Errors are assumed to be present in 3 cases:

1. If errors are indicated with the coded input data error flag CDSEF and/or CDMEF.

2. On CRC failure if ISO/MPEG error protection is active.

3. If input bitstream syntax errors are detected.

Errors in the input data have an effect on the decoding process if the corrupted data is inside the header, bit

allocation or scale factor select information field in a frame (then the SAA2500 will mute) or inside the scale factor field (then the previous scale factor will be copied). Errors in other data fields are not handled explicitly. If the ISO/MPEG CRC is active, only the CRC result is interpreted: CDSEF/CDMEF un-reliability indications for bit allocation and scale factor select information are neglected.

In applications where the ISO/MPEG CRC is always present, the protection bit (which itself is not protected) in the ISO/MPEG header may be overruled by making L3 settings flag CRCACT HIGH. In this manner, the SAA2500 is made robust for data errors on the protection bit.

Subband ﬁlter signals

The decoded subband signals are output, so that they can be processed. The optionally processed subband signals are put back into the SAA2500 for synthesis filtering.

Baseband audio processing

The baseband audio de-emphasis as indicated in the ISO/MPEG input data is performed digitally inside the SAA2500. The incorporated 'Audio Processing Unit' (see Fig.5) can be used to apply inter-channel crosstalk or independent volume control per channel. The APU attenuation coefficients LL, LR, RL and RR may be changed dynamically by the host microcontroller, writing their 8 bit indices to the SAA2500 over the L3 control bus. The coefficient changes become effective within one sample period after the coefficient index writing.

To avoid clicks at coefficient changes, the transition from the current attenuation to the next is smoothed. The relation between the APU coefficient index and the actual coefficient (i.e. the gain) is given in Table 5.

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MPEG Audio Source Decoder SAA2500

Table 5 APU coefﬁcient index and actual coefﬁcient.

APU COEFFICIENT INDEX C

BINARY DECIMAL

00000000 to 00111111 0 to 63

01000000 to 01111110 64 to 126

APU

COEFFICIENT

–

-----12

C32–()

–

----------------------6

01111111 127 0 1XXXXXXX 128 to 255 reserved

left decoded

handbook, halfpage

audio

samples

right decoded

audio

samples

MGB493

left output

audio

samples

right output

audio

samples

From Table 5 we learned that up to coefficient index 64 the step size is approximately −0.5 dB per coefficient increment, and from coefficient index 64 to index 126 the step size is approximately −1 dB per increment.

Note that the APU has no built-in overflow protection, so the application must take care that the output signals of the APU cannot exceed 0 dB level. For an update of the APU coefficients, it may be required to increase some of the coefficients and decrease some others. The APU coefficients are always written sequentially in the fixed sequence LL, LR, RL and RR. Therefore, to prevent internal APU data overflow due to non-simultaneous coefficient updating, the following steps can be followed:

1. Write LL, LR, RL, RR once, but change only those coefficients that must decrease; overwrite the coefficients that must increase with their old value (so do not change these yet).

2. Write LL, LR, RL, RR again, but now change those coefficients that must increase, keeping the other coefficients unchanged.

The consequence of this two-pass coefficient updating is that the application must keep a shadow of the current APU coefficients (the L3 APU coefficients data item is write-only).

Fig.5 Audio Processing Unit (APU).

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(1) Step −0.5 dB per coefficient increment. (2) Step −1 dB per coefficient increment.

APU coefficient index

126 127

MGB494

gain (dB)

(1)

(2)

Fig.6 Relation between APU coefficient index and gain.

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MPEG Audio Source Decoder SAA2500

Decoding control signals

The decoding is performed by 3 signals as shown in Table 6.

Table 6 Signals for decoding control.

SIGNAL DIRECTION FUNCTION

RESET input reset SAA2500 to

default state STOP input stop decoding URDA input unreliable input data;

interrupt decoding

The master reset signal RESET forces the SAA2500 into its default state when HIGH. RESET must stay HIGH during at least 24 MCLKIN periods if MCLKIN has frequency 24 MHz (i.e. MCLK24 = 1) or 12 MCLKIN periods if MCLKIN has frequency 12 MHz (MCLK24 = 0). At a reset, the SAA2500 synchronization to the input bitstream is lost, the subband filter and baseband audio output signals are muted, and the SAA2500 settings are initialised.

The decoding can be stopped by making input signal STOP HIGH. Stopping the decoding forces the SAA2500 to end decoding of input data, yet feeding zeroed subband samples to the synthesis subband filter bank to create a soft muting. When using the master input, input requesting is also stopped. CDMWS stays in its current state while STOP is asserted. The SAA2500 assumes the input synchronisation to be lost when the decoding is stopped,

thus causing re-synchronization when STOP is de-activated again. Then the SAA2500 mutes, meanwhile searching for a frame sync pattern or frame sync pulse (the synchronisation mode is selected via the L3 control bus) at the input.

If synchronisation is found, the SAA2500 starts producing output data. The maximum response time to the activation of signal STOP is half a sample period; the re-synchronisation time after STOP going LOW again differs in various situations.

An ‘unreliable data’ indication can be given to the SAA2500 by making signal URDA HIGH. URDA, like STOP, mutes the subband signals and forces the SAA2500 out of synchronisation. However, in contrast to STOP, master input data requesting continues at the bit rate that was decoded before URDA became active. The maximum response time to URDA is half a sample period.

Coded data interfaces

The SAA2500 contains:

• A coded data master input interface

• A coded data slave input interface.

HE CODED DATA MASTER INPUT INTERFACE

T When using the master input, the SAA2500 requests for

input data. With the master input, the coded input data may not use the ISO/MPEG free format bit rate. The coded data master input interface consists of 4 signals (see Fig.7).

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Table 7 Signals of coded data master input interface.

SIGNAL DIRECTION FUNCTION

CDM input ISO/MPEG coded input data (master input) CDMEF input coded data (master input) error ﬂag CDMCL output coded data (master input) clock CDMWS output coded data (master input) word select

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CDM

CDMCL

CDMWS

CDMEF

valid data valid but unreliable data invalid data

1 2 16 17 n 1 2

1 unreliable data bit (example)

Fig.7 Input data serial transfer format (master input).

Data clock CDMCL is being output, having a fixed frequency of 768 kHz. Signal CDM carries the coded data in bursts of 16 valid bits. Coded data input frames may only start either at the first or at the ninth bit of a 16 bit valid data burst (i.e. only at a byte boundary). The value of word select signal CDMWS is changed every time new input data is needed: one CDMCL period after each transition in CDMWS, 16 bits of valid data are read serially. Assume N is the number of CDMCL periods between two transitions of CDMWS, and R is the number of CDMCL periods to obtain the effective bit rate E (in kbits/s) at a transferring data rate of 768 kbits/s, i.e. R = 16*768/E. The SAA2500 keeps N close to R, but N can vary plus or minus two: N ∈ {round(R)-2,...,round(R)+2}.

MGB495

Error flag CDMEF is used to indicate input data insecurities (e.g. due to erratic channel behaviour). In Fig.7, an example with one unreliable bit is shown. The value of CDMEF may vary for each valid data bit, but is combined by the SAA2500 for every group of 8 input bits.

HE CODED DATA SLAVE INPUT INTERFACE

T The coded data slave input interface signals are shown in

Fig.8. The coded data master input interface consists of 5 signals (see Table 8).

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Table 8 Signals of coded data slave input interface.

SIGNAL DIRECTION FUNCTION

CDS input ISO/MPEG coded input data (slave input) CDSEF input coded data (slave input) error ﬂag CDSCL input coded data (slave input) clock CDSWA input coded data (slave input) burst windowing signal CDSSY input coded data (slave input) frame sync

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CDS

CDSCL

CDSWA

CDSSY

CDSEF

valid data valid but unreliable data invalid data

CDSSY indicates frame start during valid data.

frame start

Fig.8 Input data serial transfer format (slave input).

CDS is the SAA2500 input data bitstream. Data clock CDSCL must have a frequency equal to or higher than the bit rate. The maximum CDSCL frequency is 768 kHz. Error flag CDSEF is handled in the same way as CDMEF is handled for the master input (in Fig.8, one unreliable data bit is shown as an example). The value of CDSEF is neglected for those bits where CDSWA is LOW. Window signal CDSWA being HIGH indicates valid data; in this way, burst input data is allowed. The constraints for the ability to use ‘burst signals’ are explained below. Frame sync signal CDSSY indicates the start of each input data frame. CDSSY is synchronous with CDSCL. CDSSY may be present or not: as described below. The first valid CDS bit after a leading edge of CDSSY is interpreted to be the first frame bit.

1 unreliable data bit (example)

MGB496

The minimum time for CDSSY to stay HIGH is one CDSCL period; the maximum HIGH period is constrained by the requirement that CDSSY must be LOW at least during one CDSCL period per frame (a leading edge, i.e. a frame start indication, must be present every frame). Leading edges of CDSSY can occur while CDSWA is HIGH, as in Fig.8. Alternatively, a situation as shown in Fig.9 is also allowed, where CDSSY has a leading edge while CDSWA is LOW, i.e. during invalid data. The first CDS bit after CDSWA going HIGH is now interpreted to be the first frame bit.

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