Philips SAA2022GP Datasheet

INTEGRATED CIRCUITS

DATA SHEET

SAA2022

Tape formatting and error correction for the DCC system

Product specification	February 1994
Supersedes data of February 1993
File under Integrated Circuits, Miscellaneous

Philips Semiconductors

Philips Semiconductors Product specification

Tape formatting and error		SAA2022
correction for the DCC system

FEATURES

∙Integrated error correction encoder/decoder function with Digital Compact Cassette (DCC) optimized algorithms

∙Control of capstan servo during recording and after recording by microcontroller

∙Frequency and phase regulation of capstan servo during playback

∙Choice of two Dynamic Random Access Memory (DRAM) types operating in page mode

∙Scratch pad RAM area available to microcontroller in system DRAM

∙Low power standby mode

∙I2S interface

∙Microcontroller interface for high-speed transfer burst rates up to 170 kbytes per second

∙SYSINFO and AUXILIARY data flags on microcontroller interface

∙Protection against invalid AUXILIARY data

∙+4 V operating voltage capability.

GENERAL DESCRIPTION

Performing the tape formatting and error correction functions for DCC applications, the SAA2022 can be used in conjunction with the PASC (SAA2002/SAA2012), tape equalization (SAA2032), read amplifier (TDA1317 or TDA1318) and write amplifier (TDA1316 or TDA1319) circuits to implement a full signal processing system.

ORDERING INFORMATION

EXTENDED TYPE			PACKAGE
NUMBER
	PINS	PIN POSITION		MATERIAL	CODE
SAA2022GP	64	QFP(1)		plastic	SOT208A

Note

1.When using reflow soldering it is recommended that the Dry Packing instructions in the “Quality Reference Pocketbook” are followed. The pocketbook can be ordered using the code 9398 510 34011.

February 1994

2

1994February			V DD1	V DD2	V DD3	VDD4	PINO2	DIAGRAMBLOCK	systemDCCtheforcorrection	errorandformattingTape	SemiconductorsPhilips
5			43	8	27	59
LTCLK
6
LTEN
3
LTCNT1
4
LTCNT0
49
PINI
57
SBEF
62
SBDA
61
SBCL
60
SBWS
56						2	LTDATA
SBMCLK						29
33–41							WDATA
TCH0 - 7,						28
TAUX							WCLOCK
						32	PINO1
		SB – I 2 S				50
TAPE INPUT	TAPE OUTPUT		MICROCONTROLLER
BUFFER	BUFFER	INTERFACE	INTERFACE			51	PINO3
				ERROR
3			CORRECTION
				CODER
	SAA2022					9	RASN
						15
							CASN
						17–25
	CLOCK			DRAM			A0–8
		CONTROL				11–14
	GENERATOR			INTERFACE
							D0–3
						10	WEN
						16
							OEN
48						1
RESET						64	LTREF
47							URDA
PWRDWN						63
44							SBDIR
CLK24						30
							SPEED
						31
							SPDF
						52
							AZCHK			SAA2022	specificationProduct
						55
							MCLK
			42	7	26	58
			V SS1	V SS2	V SS3	V SS4	MEA711 - 2
	Fig.1	Block diagram.

Philips Semiconductors Product specification

	Tape formatting and error					SAA2022
	correction for the DCC system
PINNING
	SYMBOL	PIN		DESCRIPTION
LTREF		1	timing reference for microcontroller interface
LTDATA		2	data for microcontroller interface (3-state; CMOS levels)
LTCNT1		3	control for microcontroller interface
LTCNT0		4	control for microcontroller interface
LTCLK		5	bit clock for microcontroller interface
LTEN		6	enable for microcontroller interface
VSS2		7	supply ground (0 V)
VDD2		8	supply voltage (+5 V)
RASN		9	DRAM row address strobe
WEN		10	DRAM write enable
D3		11	DRAM data (MSB); 3-state output; TTL compatible input
D2		12	DRAM data; 3-state output; TTL compatible input
D1		13	DRAM data; 3-state output; TTL compatible input
D0		14	DRAM data (LSB); 3-state output; TTL compatible input
CASN		15	DRAM column address strobe
OEN		16	DRAM output enable
A8		17	DRAM address (MSB)
A7		18	DRAM address
A6		19	DRAM address
A5		20	DRAM address
A4		21	DRAM address
A3		22	DRAM address
A2		23	DRAM address
A1		24	DRAM address
A0		25	DRAM address (LSB)
VSS3		26	supply ground (0 V)
VDD3		27	supply voltage (+5 V)
WCLOCK		28	clock for write amplifier transfers
WDATA		29	write amplifier serial data
SPEED		30	capstan phase information
SPDF		31	capstan frequency information
PINO1		32	Port expander output 1
TAUX		33	AUX channel input from SAA2032
TCH7		34	main data channel 7, input from SAA2032
TCH6		35	main data channel 6, input from SAA2032
TCH5		36	main data channel 5, input from SAA2032
TCH4		37	main data channel 4, input from SAA2032
TCH3		38	main data channel 3, input from SAA2032
TCH2		39	main data channel 2, input from SAA2032

February 1994

4

Philips Semiconductors Product specification

	Tape formatting and error					SAA2022
	correction for the DCC system
	SYMBOL	PIN		DESCRIPTION
TCH1		40	main data channel 1, input from SAA2032
TCH0		41	main data channel 0, input from SAA2032
VSS1		42	supply ground (0 V)
VDD1		43	supply voltage (+5 V)
CLK24		44	24.576 MHz clock from SAA2002
TEST0		45	test select LSB; do not connect
TEST1		46	test select MSB; do not connect
PWRDWN		47	sleep mode selection
RESET		48	reset input with hysteresis and pull-down resistor
PINI		49	Port expander input
PINO2		50	Port expander output 2
PINO3		51	Port expander output 3
AZCHK		52	azimuth check (channels 0 and 7)
TEST2		53	symbol error rate measurement output
TEST3		54	do not connect
MCLK		55	master clock output (6.144 MHz)
SBMCLK		56	master clock for SB-I2S-interface
SBEF		57	byte error SB-I2S-interface
VSS4		58	supply ground (0 V)
VDD4		59	supply voltage (+5 V)
SBWS		60	word select SB-I2S-interface; 3-state output; CMOS levels
SBCL		61	bit clock SB-I2S-interface; 3-state output; CMOS levels
SBDA		62	data line SB-I2S-interface; 3-state output; CMOS levels
SBDIR		63	direction SB-I2S-interface
URDA		64	unusable data SB-I2S-interface

February 1994

5

Philips Semiconductors Product specification

	Tape formatting and error		SAA2022
	correction for the DCC system

LTREF 1 LTDATA 2 LTCNT1 3 LTCNT0 4

LTCLK 5 LTEN 6 VSS2 7 VDD2 8

RASN 9

WEN 10

D3 11

D2 12

D1 13

D0 14

CASN 15

OEN 16

A8 17

A7 18

A6 19

URDA		SBDIR		SBDA		SBCL		SBWS		V		V		SBEF		SBMCLK		MCLK		TEST3		TEST2		AZCHK
										DD4		SS4
64		63		62		61		60		59		58		57		56		55		54		53		52

SAA2022

	20		21		22		23		24		25		26		27		28		29		30		31		32
	A5		A4		A3		A2		A1		A0		V		V		WCLOCK		WDATA		SPEED		SPDF		PINO1
													SS3		DD3

51 PINO3

50 PINO2

49 PINI

48 RESET

47 PWRDWN

46 TEST1

45 TEST0

44 CLK24

43 VDD1

42 VSS1

41 TCH0

40 TCH1

39 TCH2

38 TCH3

37 TCH4

36 TCH5

35 TCH6

34 TCH7

33 TAUX

MEA693 - 2

Fig.2 Pin configuration (SOT208A).

February 1994

6

1994 February

RECORDING + PLAY BACK

	analog			ADC
	input
				SAA7360
						I2S
	analog			DAC
	output			SAA7323
	digital input			DAIO
				TDA1315
	digital output

7

AUDIO INPUT/OUTPUT

stereo filter codec

SAA2002 I2S

(sub-band)

SAA2012					SAA2022
adaptive
allocation and
scale factors						RAM

speed control	capstan
	drive
TDA1316 or
TDA1319
	write
	heads
	and
SAA2032	tape
	read
digital	TDA1317 or
equalizer
	TDA1318

	256 kbits
PASC PROCESSING	TAPE DRIVE PROCESSING
	MEA695 - 2

MICROCONTROLLER

Fig.3 DCC data flow diagram.

DESCRIPTION FUNCTIONAL

error and formatting Tape system DCC the for correction

SAA2022

Semiconductors Philips

specification Product

Philips Semiconductors Product specification

	Tape formatting and error		SAA2022
	correction for the DCC system

The SAA2022 provides the following functions:

In Playback Modes

∙Tape channel data and clock recovery

∙10 to 8 demodulation

∙Data placement in DRAM

∙C1 and C2 error correction decoding

∙I2S-interfacing to SB-I2S-bus

∙Interfacing to microcontroller for SYSINFO and AUX data

∙Capstan control for tape deck.

In Record Modes

∙I2S-interfacing to SB-I2S-bus

∙C1 and C2 error correction encoding

∙Formatting for tape transfer

∙8 to 10 modulation

∙Interfacing to microcontroller for SYSINFO and AUX data

PWRDWN

This pin is an active HIGH signal which places the SAA2022 in a “SLEEP” mode. When the SAA2022 is in “SLEEP” mode and the CLK24 is either held HIGH or held LOW, there is no activity in the device, thus resulting in no EMI and a low power dissipation (typically <10% of operational dissipation). This pin should be connected to the DCC power-down signal, which can be driven by the system microcontroller.

To enter the “SLEEP” mode the SAA2022 should reset and hold reset. After a delay of at least 15 μs the PWRDWN pin should be brought HIGH after which the state of the reset pin is “don’t care”. The power dissipation is reduced further when the CLK24 input signal stops.

When recovering from “SLEEP” mode the PWRDWN pin should be driven LOW and the chip reset with a pulse of at least 15 μs duration.

CLK24

This is the 24.576 MHz clock input and should be connected directly to the SAA2002 CLK24 pin.

∙Capstan control for tape deck, programmable by microcontroller.

Operational Modes

The 3 basic modes of operation are:

∙DPAP - Main data (audio) and SYSINFO play, AUX play

∙DRAR - Main data (audio) and SYSINFO record, AUX record

∙DPAR - Main data (audio) and SYSINFO play, AUX record.

Hardware Interfacing

RESET

This is an active HIGH input signal which resets the SAA2022 and brings it into its default mode, DPAP. This should be connected to the system reset, which can be driven by the microcontroller. The duration of the reset pulse should be at least 15 μs. This pin has an internal pull-down resistor of between 20 kΩ and 125 kΩ.

Connections to SAA2032

TCH0 TO TCH7 AND TAUX

These lines are the equalized and clipped (to VDD) tape channel inputs and should be connected to the SAA2032 pins TCH0 to TCH7 and TAUX.

Sub-band I2S-bus Connections

The timing for the SB-I2S-interface is given in Figs 4 to 9.

February 1994

8

February1994		lines show rising edge of SBMCLK																					system DCCcorrectionthe for	error andformattingTape	SemiconductorsPhilips
	SBMCLK
	SBCL
	SBWS
	SBDA
	bit number	0	1	2	3	4	5	6	7	8	9	10	11	12	13	14	15
	byte number					0								1
	SBEF
	byte number				0								1
9
								16	17	18	19	20	21	22	23	24	25	26	27	28	29	30	31
											2									3
										2									3				MEA697 - 1		specification Product
						Fig.4		SB-I2S-interface in playback master mode (1).																SAA2022

February1994	t H-1		systemcorrectionDCCthefor	formattingerrorTapeand	SemiconductorsPhilips
	SBMCLK
	(INPUT)
	t L-1	t dSR
	SBCL
	(OUTPUT)
	t dSR
	SBWS
	(OUTPUT)
	SBEF
	(OUTPUT)
	t suMR	t suMR
10	MCLK
	(OUTPUT)
			t dMR
	SBDA
	(OUTPUT)
	SBEF
	(OUTPUT)
			MEA696
	Fig.5	SB-I2S-interface in playback master mode (2).		SAA2022	specification Product

SBCL																						systemcorrectionDCCthefor	errorformattingTapeand	SemiconductorsPhilips
SBWS
SBDA
bit number	0	1	2	3	4	5	6	7	8	9	10	11	12	13	14	15
byte number					0							1
1994February
SBEF
11
							16	17	18	19	20	21	22	23	24	25	26	27	28	29	30	31
										2									3
																						MEA699 - 1
					Fig.6		SB-I2S-interface in playback slave mode (1).																SAA2022	specification Product

February1994	MCLK		correctionsystemDCCthefor	formattingTapeerrorand	SemiconductorsPhilips
	t hMR	t hMR
	t suMR	t suMR
	SBCL
	(INPUT)
	SBWS
12	(INPUT)
	SBEF
	(OUTPUT)
			t dMR
	SBDA
	(OUTPUT)
			MEA698
	Fig.7	SB-I2S-interface in playback slave mode (2).		SAA2022	specification Product

SBCL																							systemcorrectionDCCthefor	formattingerrorTapeand	SemiconductorsPhilips
SBWS
SBDA
1994February
bit number	0	1	2	3	4	5	6	7	8	9	10	11	12	13	14		15
byte number					0								1
13
						16		17	18	19	20	21	22	23	24	25	26	27	28	29	30	31	MSA536
										2									3
						Fig.8		SB-I2S-interface in record mode (1).																SAA2022	specification Product

February1994	MCLK	correctionsystemDCCthefor	formattingTapeerrorand	SemiconductorsPhilips
	(OUTPUT)
	t suMR
	SBCL
	(INPUT)
	t hMR
14	SBWS
	(INPUT)
	SBDA
	(INPUT)
		MEA700
	Fig.9	SB-I2S-interface in record mode (2).	SAA2022	specification Product

Philips Semiconductors Product specification

	Tape formatting and error		SAA2022
	correction for the DCC system

SBMCLK

This is the sub-band master clock input for the SB-I2S-interface. The frequency of this signal is nominally 6.144 MHz. This pin should be connected to the SBMCLK pin of the SAA2002.

SBDIR

This output pin is the sub-band I2S-bus direction signal, it indicates the direction of transfer on the SB-I2S-bus.

A logic 1 indicates a SAA2022 to SAA2002 transfer (audio play) whilst a logic 0 is output for a SAA2002 to SAA2022 transfer (audio record). This pin connects directly to the SBDIR pin on the SAA2002.

SBCL

This input/output pin is the bit clock line for the SB-I2S-interface to the SAA2002. Is has a nominal frequency of 768 kHz.

SBWS

This input/output pin is the word select line for the SB-I2S-interface to the SAA2002. It has a nominal frequency of 12 kHz.

SBDA

This input/output pin is the serial data line for the SB-I2S-interface to the SAA2002.

SBEF

This active HIGH output pin is the error per byte line for the SB-I2S-interface to the SAA2002.

URDA

This active HIGH output pin indicates that the main data (audio), the SYSINFO and the AUXILIARY data are not usable, regardless of the state of the corresponding reliability flags. The state of this pin is reflected in the URDA bit of STATUS byte 0, which can be read by the microcontroller. This pin should be connected directly to the URDA pin of the SAA2002. URDA is activated as a result of a reset, a mode change from DRAR to DPAP, or if the SAA2022 has had to resynchronize with the incoming data from tape.

The position of the first SB-I2S-bytes in a tape frame is shown in Fig.10.

February 1994

15

Philips Semiconductors Product specification

	Tape formatting and error		SAA2022
	correction for the DCC system

SNUM

LTREF

SBWS

SBDA

SNUM

LTREF

SBWS

SBDA

MODE DPAP OR DPAR

0

1

BYTE number 2

BYTE number BYTE number 1

8191

BYTE number 0

OF PREVIOUS

TAPE FRAME

MODE DRAR

3

0

		BYTE number 2	MEA701 - 2
	BYTE number 8191	BYTE number 1

BYTE number 0

OF PREVIOUS

TAPE FRAME

Fig.10 Position of first SB-I2S-bytes in tape frame.

February 1994

16