Philips saa2012 DATASHEETS

INTEGRATED CIRCUITS

DATA SH EET

SAA2012

Adaptive allocation and scaling for record processing in DCC systems

Product speciﬁcation Supersedes data of February 1993 File under Integrated Circuits, Miscellaneous

Philips Semiconductors

September 1995

Philips Semiconductors Product speciﬁcation

Adaptive allocation and scaling for record processing in DCC systems

FEATURES

• Stereo or 2-channel mono encoding

• Status may be read continuously

• Microcontroller interface

• I2S interfaces

• Allocation algorithm including optional emphasis

correction (for 44.1 kHz)

• Reduced power consumption

• 4 V nominal operating voltage capability.

GENERAL DESCRIPTION

Performing the Adaptive Allocation and Scaling function in the Precision Adaptive Sub-band Coding (PASC) system, the SAA2012 is intended for use in conjunction with the stereo filter and codec (SAA2002).

SAA2012

ORDERING INFORMATION

EXTENDED TYPE

NUMBER

SAA2012GP 44 QFP; note 1 plastic SOT205AG

Note

1. When using reflow soldering it is recommended that the Dry Packing instructions in the “

Pocketbook

” are followed. The pocketbook can be ordered using the code 9398 510 34011.

PINS PIN POSITION MATERIAL CODE

PACKAGE

Quality Reference

September 1995 2

Philips Semiconductors Product speciﬁcation

Adaptive allocation and scaling for

33 32

SAA2012

FDAC

SCL

record processing in DCC systems

BLOCK DIAGRAM

SWS

FS256

FDAF

INTERFACE INTERFACECOMPENSATION DELAY

14,24,40

NODONE

RESOL0

RESOL1

FDIR

FRESET

FSYNC SCALE

TEST3 TEST4

LTDATA LTCNT1 LTCNT0

LTENA

LTCLK CLK24

RESET

PWRDWN

20 21 22

37 36 35 38

15 16

5 1 2

3 4

26 23 30

CONTROL

SAA2012

LT INTERFACE

ALLOCATION AND

SCALING 

CALCULATION

6,25,44

7 8 9

MEA660

LTDATAC

LTCNT1C

LTCNT0C

LTENC

LTCLKC

September 1995 3

Fig.1 Block diagram.

Philips Semiconductors Product speciﬁcation

Adaptive allocation and scaling for record processing in DCC systems

PINNING

SYMBOL PIN DESCRIPTION

LTCNT1 1 mode control 1, microcontroller interface input LTCNT0 2 mode control 0, microcontroller interface input LTENA 3 enable microcontroller interface input LTCLK 4 bit clock microcontroller interface input LTDATA 5 data, microcontroller interface (3-state input/output) V

LTCNT1C 7 control 1, microcomputer interface, SAA2002 side output LTCNT0C 8 control 0, microcomputer interface, SAA2002 side output LTENC 9 enable microcontroller interface, SAA2002 side output LTCLKC 10 bit clock; microcontroller interface, SAA2002 side output LTDATAC 11 data; microcontroller interface, SAA2002 side (3-state input/output) TEST1 12 test 1 output; do not connect TEST2 13 test 2 output; do not connect V

TEST3 15 test 3 mode input; to be connected to V TEST4 16 test 4 mode input; to be connected to V TEST5 17 test 5 input; to be connected to V TEST6 18 test 6 input; to be connected to V TEST7 19 test 7 input; to be connected to V NODONE 20 no done state selection input RESOL0 21 resolution selection 0 input RESOL1 22 resolution selection 1 input RESET 23 active HIGH reset input V

CLK24 26 24.576 MHz processing clock input TEST8 27 test 8 input; to be connected to V TEST9 28 test 9 input; to be connected to V TEST10 29 test 10 input; to be connected to V PWRDWN 30 SLEEP mode input SWS 31 word selection input; ﬁltered - I SCL 32 bit clock input; ﬁltered - I FDAC 33 ﬁltered data - I FDAF 34 ﬁltered data - I FSYNC 35 sub-band synchronization on input; ﬁltered - I FRESET 36 reset signal input from SAA2002 FDIR 37 direction input of the I SCALE 38 scale factor index select (note 1) FS256 39 system clock input; sample frequency × 256 V

6 supply ground (0 V)

14 supply voltage (+5 V)

24 supply voltage (+5 V) 25 supply ground (0 V)

S-interface; SAA2002 side (3-state input/output)

40 supply voltage (+5 V)

S-interface

SAA2012

September 1995 4

Philips Semiconductors Product speciﬁcation

Adaptive allocation and scaling for record processing in DCC systems

SYMBOL PIN DESCRIPTION

n.c. 41 not connected n.c. 42 not connected n.c. 43 not connected V

Note

1. The SCALE input must be set LOW for use with the SAA2002. If operation with the SAA2001/2021 combination is required the SCALE input must be set HIGH.

44 supply ground (0 V)

SAA2012

LTCNT1 LTCNT0

LTENA LTCLK

LTDATA

SS LTCNT1C LTCNT0C

LTENC

LTCLKC

LTDATAC

n.c.

1 2 3 4 5 6 7 8

9 10 11

TEST1

TEST2

n.c. 41

TEST3

FS256

SAA2012

TEST4

TEST5

SCALE

TEST6

FDIR 37

TEST7

FRESET

FSYNC

RESOL0

NODONE

FDAF

RESOL1

33 32 31 30 29 28 27 26 25 24 23

MEA656

FDAC SCL SWS PWRDWN

TEST10 TEST9

TEST8 CLK24 V

RESET

September 1995 5

Fig.2 Pin configuration.

Philips Semiconductors Product speciﬁcation

Adaptive allocation and scaling for record processing in DCC systems

drive

capstan

heads

and

tape

SAA2012

write

TDA1319

TDA1316 or

speed control

codec

SAA2002

stereo filter

I S

(sub-band)

read

digital

SAA2032

SAA2022

adaptive

SAA2012

TDA1318

TDA1317 or

equalizer

RAM

256 kbits

scale factors

allocation and

TAPE DRIVE PROCESSING

MEA695 - 2

MICROCONTROLLER

Fig.3 DCC data flow diagram.

September 1995 6

I S

ADC

SAA7360

RECORDING + PLAY BACK

input

analog

DAC

SAA7323

output

analog

DAIO

TDA1315

digital input

digital output

AUDIO INPUT/OUTPUT PASC PROCESSING

Philips Semiconductors Product speciﬁcation

Adaptive allocation and scaling for record processing in DCC systems

FUNCTIONAL DESCRIPTION

PASC

Precision Adaptive Sub-band Coding achieves highly efficient digital encoding with a bit-rate of 384 kbits/s. It utilizes a system producing sub-band samples from an incoming digital audio signal. This relies upon the audibility of signals above a given level and upon high amplitude signals masking those of lower amplitude. Although each sub-band signal is of approximately 750 Hz bandwidth, it possesses considerable overlap with those adjacent to it.

During the process of encoding, the PASC processor analyses the broadband audio signal at sampling frequency (f sampling frequency (fs/32).

The PASC signal consists of frames conveying the information corresponding to 384 sub-band samples. These also include a synchronization pattern identifying the start of each new frame. The allocation information for the 32 sub-bands is transferred as 4-bit values. If the amplitude of a sub-band signal is below the masking threshold it will be omitted from the PASC signal.

The duration of a PASC frame depends upon sampling frequency and is adjusted to 384 divided by fs.

Adaptive Allocation and Scaling

The PASC system calculates the masking power of the sub-band signals and adds the masking threshold. Sub-band signals with power below this threshold denote information to be discarded. Non-masked signals are coded using floating point notation in which a mantissa corresponds in length to the difference between peak power and masking threshold. The process is repeated for every PASC frame and is known as the Adaptive Allocation of the available capacity.

Encoding mode

Signal FDIR sets the data flow direction on the Filtered-I (FDIR = LOW) the device will accept samples from FDAF. These will be delayed by a number of sample periods depending upon the setting of the SCALE input. In the event of operation with the SAA2002 (SCALE = 0) this delay will be 480 SWS periods. This will ensure alignment of the data with the computed allocations.

After the delay the samples will be presented on FDAC (pin 33). The circuit also performs all the calculations required to build the allocation table which is used in the codec (SAA2002).

) by splitting it into 32 sub-band signals at a

S-interface. In the encoding mode

SAA2012

When used with the SAA2002 the calculated scale factor indices are sent via the LT interface. These operations are performed for every frame of the sub-band codec.

In order to synchronize with the codec and utilize the correct tables for the calculations the SAA2012 frequently requests the status of the codec. It monitors the bit-rate, sample frequency, operation mode and the emphasis information and uses the ‘ready-to-receive’ bit of the codec to determine the moment of the transfer of allocation information.

Decoding Mode

In the decoding mode (FDIR = HIGH) the SAA2012 will take samples from FDAC which will be presented on the FDAF after a delay of 160 SWS periods. The LT interface between microcontroller and codec (SAA2002) will only be affected by the ‘ready-to-receive’ bit from the codec (SAA2002).

Microcontroller Interface Operation

Information on the interface between microcontroller and codec (SAA2002) will flow in a regular sequence synchronized with the codec (SAA2002):

• With every FSYNC the SAA2012 will read the status of the codec (SAA2002).

• Following the calculation of the allocation and scale factors the SAA2012 will send the first allocation information unit (16-bits). It will then continuously read the codec (SAA2012) status to ascertain when it is able to receive further allocation information units. When the transfer of these units is complete the SAA2012 will send settings and (for SCALE = 0) scale factor indices.

• The extended settings will be sent to the codec as soon as possible after reception from the microcontroller.

The microcontroller communicates with the SAA2012 in a similar fashion:

• Status can be read continuously. The SAA2012 will output a copy of the codec (SAA2002) status on the LTDATA line except for the ‘ready-to-receive’ bits which are generated by the SAA2012. These indicate whether the SAA2012 is ready to receive the next settings or extended settings.

• Settings can be sent following every occasion that the ‘ready-to-receive’ bit ‘S’ changes to logic 1.

• Extended settings can be sent following each occasion that the ‘ready-to-receive’ bit ‘E’ changes to logic 1.

September 1995 7

Philips Semiconductors Product speciﬁcation

Adaptive allocation and scaling for record processing in DCC systems

Mode Control

Operation is controlled by the FRESET and FDIR signals. FRESET causes a general reset. The FDIR signal is sampled at the falling edge of the FRESET signal to determine the operation mode:

• FDIR = logic 1 decoding mode, SAA2012 in feed-through mode

• FDIR = logic 0 encoding mode, SAA2012 in calculation mode.

Figure 4 shows the timing diagram for FRESET and FDIR.

Resolution Selection

The (SAA2012) is designed for operation with input devices (ADCs) which may possess a different sample resolution capability, i.e. audio sample inputs into the sub-band filters. RESOL0 (pin 21) and RESOL1 (pin 22) may be utilized to adjust the allocation information calculation to the resolution of the samples.

With the instance of NODONE (pin 20) being HIGH, all available bits in the bit-pool will be allocated. If NODONE is LOW, no bits will be allocated to the sub-bands with energy levels below the theoretical threshold for the selected resolution. For encoding in accordance with the DCC standard NODONE must be HIGH.

SAA2012

Table 1 Resolution selection.

RESOL1 RESOL0 RESOLUTION

0 0 16 bits 0 1 18 bits 1 0 14 bits 1 1 15 bits

Sleep mode switching

When the potential on the RESET pin (pin 23) is held HIGH for at least 5T after which it will operate in its decoding mode.

The sleep mode is activated when the PWRDWN pin (pin 30) is held HIGH. The 3-state buffers will be set to a high impedance while the normal outputs will retain the state attained prior to this mode being entered. This mode can only be used if other associated circuits react accordingly. The sleep mode is de-activated by a reset action.

Operation for the sleep mode switching is shown in Fig.5.

clock periods, the device will be reset

clk24

FRESET

suD

FDIR

trH > 5T t

suD

= 210 ns (for CLK = 24.576 MHz) minimum time; FRESET = HIGH.

clk24

< 0 ns minimum set-up time; FDIR to FRESET = LOW.

Fig.4 Timing of FRESET and FDIR.

September 1995 8

MBC123 - 1

Philips Semiconductors Product speciﬁcation

Adaptive allocation and scaling for record processing in DCC systems

PWRDWN

RESET

sleep mode active

SAA2012

MEA659 - 1

trH > 5T

= 210 ns (for CLK = 24.576 MHz) minimum time; RESET = HIGH.

clk24

Fig.5 Sleep mode switching.

channel

SWS

SCL

FDA

bit :

msb lsb

left 32 bits

7 bits

2102322212

2322212

msb

right

MBC149 - 1

September 1995 9

Fig.6 Format for transferring filtered data.

Philips Semiconductors Product speciﬁcation

Adaptive allocation and scaling for record processing in DCC systems

SAA2012

channel

SWS

FSYNC sub-band

LRLLLLLLRRRRRR

31 0 1 31 0 1

MBC126 - 2

Fig.7 FSYNC relative to SWS.

Filtered-I2S-Interfaces

Interfaces with the sub-band filter and codec (SAA2002) consist of the signals shown in Table 2.

Table 2 The ﬁltered-I

S-interface.

SIGNAL TYPE DESCRIPTION FREQUENCY

SWS input word selection f

SCL input bit clock 64f FDAF bi-directional ﬁltered data to/from the ﬁlter section of SAA2002 − FDAC bi-directional ﬁltered data to/from the codec section of SAA2002 −

FSYNC input ﬁlter synchronization f

FRESET input reset −

FDIR input ﬁltered - I

S-interface direction of data ﬂow −

/32

The format for transferring filtered data is shown in Fig.6. Input frequency (f

) must be provided as system clock. This frequency is used by the interfaces with the SAA2002.

The frequency of the SWS signal (pin 31) is equal to the sample frequency (fs). Bit clock SCL (pin 32) is 64 times fs; thus each SWS period contains 64 data bits, 48 of which are actually used in data transfer. The half period when SWS is logic 0 is used to transfer left-channel information, when SWS is logic 1 transfer of right-channel data is allowed.

The 24-bit samples are transferred with the most significant bit first. This bit is transferred during the bit clock period, one bit time after the change in SWS.

FSYNC signal is provided for the purposes of synchronization and indicates the portion of the SWS period during which the samples of sub-band 0 are transferred.

The relationship between FSYNC and the SWS is logic 0 data transfer period is shown in Fig.7

September 1995 10

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