Philips SAA1305T Technical data

INTEGRATED CIRCUITS

DATA SH EET

SAA1305T

On/off logic IC

Product speciﬁcation Supersedes data of 1998 Sep 04

2004 Jan 15

Philips Semiconductors Product speciﬁcation

On/off logic IC SAA1305T

FEATURES

• 8 accurate Schmitt trigger inputs with clamp circuits

• Very low quiescent current

• Reset generator circuit

• Changed information output

• On/offoutputtocontrolaregulator ICwhichsuppliesthe

microcontroller

• 32.768 kHz RC oscillator and/or a 32.768 kHz crystal oscillator

• No delayed reset needed (start-up behaviour oscillator fixed by internal logic)

• Watchdog timer function

• Blinking LED oscillator with drive circuit for LED

• Watch function.

TheSAA1305Tcanreplaceanexistingon/offlogicbuilt-up with discrete components.

The SAA1305T contains 8 inputs with accurate Schmitt triggers and clamp circuits. The main function of this IC is an intelligent I/O expander with 2 modes of operation:

1. Normal I/O expander: the microcontroller (master) is running and the SAA1305T acts like a slave.

2. Sleepmodeofthetotalapplication:themicrocontroller is stopped and the SAA1305T acts like a master. During an event, the microcontroller is awakened.

GENERAL DESCRIPTION

TheSAA1305Tis an on/off logic IC, intended for use in car radios to interface between a microcontroller and various input signals such as ignition, low supply detection, on/off key and external control signals.

I2C-bus (400 kHz). Extra functions of the SAA1305T are:

• LED blinker circuit

• One-day watch

• Watchdog timer.

QUICK REFERENCE DATA

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

The communication with the IC is performed via the

SCL(max)

supply voltage operating 4.5 5.0 5.5 V quiescent supply current VDD= 5 V; standby mode − 130 200 µA maximum SCL clock frequency −−400 kHz virtual junction temperature −−150 °C

ORDERING INFORMATION

PACKAGE

TYPE NUMBER

NAME DESCRIPTION VERSION

SAA1305T SO24 plastic small outline package; 24 leads; body width 7.5 mm SOT137-1

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Philips Semiconductors Product speciﬁcation

On/off logic IC SAA1305T

BLOCK DIAGRAM

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D0 D1 D2 D3 D4 D5 D6 D7

SDA

SCL

2 3 4

NEW

LATCH

6 7 8

18 20

INTERFACE

LED DRIVER

OLD

LATCH

I2C-BUS

COMPARATOR MASK

SAA1305T

STATUS

SUPPLY

WATCH TIMER ALARM TIMER

OSCILLATOR

RESET

GENERATOR

VL TIMER

WATCHDOG

TIMER

ERROR

COUNTER

CHI

ON/OFF

LED

RES

XTAL2

OSC2

OSC1

XTAL1

TST

MGR200

Fig.1 Block diagram.

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Philips Semiconductors Product speciﬁcation

On/off logic IC SAA1305T

PINNING

SYMBOL PIN DESCRIPTION

D0 1 input D0; generates a reset pulse on pin RP and a LOW-level voltage on pin CHI D1 2 input D1; generates a reset pulse on pin RP and a LOW-level voltage on pin CHI D2 3 input D2; generates a reset pulse on pin RP and a LOW-level voltage on pin CHI D3 4 input D3; generates a reset pulse on pin RP and a LOW-level voltage on pin CHI D4 5 input D4; generates a reset pulse on pin RP and a LOW-level voltage on pin CHI D5 6 input D5; generates a reset pulse on pin RP and a LOW-level voltage on pin CHI D6 7 input D6; generates a reset pulse on pin RP and a LOW-level voltage on pin CHI D7 8 input D7; generates a reset pulse on pin RP and a LOW-level voltage on pin CHI ON/OFF 9 on/offoutput (off is active LOW); for controlling the enable of a separate power supply IC from the

microcontroller RES 10 reset input (active LOW); for power-on or system reset for the IC WD 11 Watchdog timer trigger input signal from the microcontroller TS 12 timer start input (active LOW); to trigger the VL (is an undervoltage) timer (250 ms) TST 13 test purpose input; must be connected to V OSC1 14 RC oscillator output (32.768 kHz) OSC2 15 RC oscillator input (32.768 kHz) XTAL1 16 crystal oscillator output (32.768 kHz) XTAL2 17 crystal oscillator input (32.768 kHz) SDA 18 I2C-bus serial data input/output; interface to the microcontroller V

19 ground supply (0 V) SCL 20 I2C-bus serial clock line input; interface to the microcontroller V

21 supply voltage; 5 V ±10% with a current consumption of maximum 200 µA (without LED current) LED 22 light emitting diode output; to drive a LED up to 20 mA (high side switch to VDD) RP 23 reset pulse output CHI 24 change information output (active LOW); note 1

Note

1. The following results in a LOW-level voltage on pin CHI: a) A change on any of the (non-masked) inputs D0 to D7. b) A device reset. c) An alarm or VL timer event. d) An oscillator fault or a failed I2C-bus read sequence after a change information signal. e) A failed Watchdog timer trigger sequence.

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Philips Semiconductors Product speciﬁcation

On/off logic IC SAA1305T

Reset time

The pulse time on pin RP is selectable via an I2C-bus

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D0 D1 D2 D3 D4 D5 D6 D7

ON/OFF

RES

1 2 3 4 5 6 7 8

9 10 11 12

SAA1305T

MGR201

15 14 13

24 23 22 21 20 19 18 17 16

CHI RP LED

DD SCL V

SS SDA

XTAL2 XTAL1 OSC2 OSC1 TST

Fig.2 Pin configuration.

FUNCTIONAL DESCRIPTION

Figure 1 shows the block diagram for the SAA1305T. Details are explained in the subsequent sections.

Watch and alarm functions

An internal RAM (watch register) counts automatically the seconds for one-day (one-day reset also automatically). The watch register can be set and read from the I2C-bus. An alarm function is possible via a second RAM (alarm register) and is programmable via the I2C-bus. The alarm timer triggers pin CHI and if enabled the reset pulse on pin RP. After a device reset the content of the alarm register is FFFFH (alarm function is disabled) and the content of watch register is 0000H.

LED control

The I2C-bus interface control (see Table 10) for the LED contains:

• Two function control bits

• Two control bits for the blink LED frequency

• Two control bits for the blink LED duration time.

command; see Table 8. The default value after Power-on reset is the longest time (20 ms). Selectable pulse times via the control register are: 1, 5, 10 and 20 ms.

Withtherisingedgeofthereset pulse all inputs, except the Watchdog timer and VL timer, are disabled until the I2C-bus command ENABLE-RESET. Each pulse on pin RP resets the internal I2C-bus interface.

On/off

The output signal on pin ON/OFF remains HIGH after a trigger event. Trigger sources are:

• Alterations on any of the inputs D0 to D7

• An impedance detection

• A device reset

• A VL (is an undervoltage) timer or alarm timer event

• An oscillator fault.

In the event of a five time failed Watchdog timer trigger or missedI2C-busreadsequence(afterachangeinformation indication), an internal logic circuit will reset pin ON/OFF and set the IC in the standby mode. It is also possible to control pin ON/OFF during the run mode via an I2C-bus command (see Table 8, bit 1). In principal two stable IC modes are possible; see Fig.3:

1. Standby mode: an oscillator fault and the following IC function groups can trigger a reset pulse to enter the run mode;

a) Watch (alarm timer). b) Supply (device reset). c) Inputs D0 to D7 (a change on any of these inputs

or an impedance detection).

The Watchdog timer and the VL timer are disabled in the standby mode.

2. Run mode: only the Watchdog timer (WD), an oscillator fault, a missed I2C-bus communication and the reset input (RES) can trigger a reset pulse. It is possible to enter the standby mode via control register bit 0; see Table 8.

The dynamic mode or wait mode is possible but can only be started from the run mode (see Section “VL timer”).

All bits are combined within the LED register.

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Philips Semiconductors Product speciﬁcation

On/off logic IC SAA1305T

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RES = HIGH

RESET

RES = LOW

(1) See Section “Run mode entries”. (2) See Section “Run mode events”. (3) Possible events are: alterations on any of the inputs D0 to D7, an impedance detection, an alarm timer event and an oscillator fault. (4) See Section “Standby mode entries”. (5) Not available. (6) See Section “Wait mode entries”.

entry event

SAA1305T

OPERABLE

I2C-bus error counter = 5

Watchdog timer error counter = 5

RUN

(1)

(2)

VL timer start

VL timer end

input D0 = logic 1

oscillator fault

(3)

; CHI

event

control register bit 0

entry event

WAIT

(6)

(5)

STANDBY

(4)

entry

(5)

event

MGR202

Fig.3 State diagram for IC modes.

RUN MODE ENTRIES

• Reset Watchdog timer error counter

• Enable Watchdog timer

• Enable VL timer function

• Generate reset pulse

• Disable reset generation via inputs D0 to D7 changes

(inclusive impedance detection) and watch compare

WAIT MODE ENTRIES

• Disable Watchdog timer

• Reset I2C-bus error counter

• Reset Watchdog timer error counter

• Start VL timer

• Set pin CHI in 3-state

• Set pin ON/OFF to LOW (OFF is active).

• Reset I2C-bus interface

• Set pin CHI to LOW (LOW = active)

• Set pin ON/OFF to HIGH (ON is active).

STANDBY MODE ENTRIES

• Disable Watchdog timer

• Reset Watchdog timer error counter

RUN MODE EVENTS

• I2C-bus read and write commands

• Watchdog timer reset

• Missed I2C-bus communication after a (CHI) change

information signal

• Oscillator fault.

• Reset I2C-bus error counter

• Disable VL timer function

• Enable reset generation via inputs D0 to D7 changes

(inclusive impedance detection) and watch compare

• Set pin ON/OFF to LOW (OFF is active)

• Set pin CHI in 3-state.

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Philips Semiconductors Product speciﬁcation

On/off logic IC SAA1305T

Serial I/O

The hardware of the I2C-bus interface (slave) operates with a maximum clock frequency of 400 kHz.

Inputs

Pins D0 to D7 are connected to latches (new register). Each latch contains and stores the input change until the read out via the I2C-bus (read out of new register). A second register (old register, latches) contains the input situation before a ‘reset pulse’ signal or HIGH-to-LOW transition of pin CHI. After a level change on any of the inputs D0 to D7 (content of new register into ‘old’ register), pin CHI will indicate this event. Reading the ‘old’ register has no influence on any latch content. Reading the new register will shift the content into the old register. During the I2C-bus read sequence of the new register the latch content will be shifted into the corresponding old latch and afterwards the new latches are enabled until the next change on this input. The functions of the inputs D0 to D7 are shown in Table 1.

Table 1 Input logic levels and functions

INPUT

D7 X − X −− D6 X − X −− D5 X − X −− D4 − XX−− D3 − X −−− D2 − X −−− D1 X −−−X D0 X −−X −

SCHMITT

TRIGGER INPUT

SPECIAL INPUT MASKABLE

Due to the fact, that a ‘reset pulse’ signal or a ‘change information’ signal are also possible via the Watchdog timer, VLtimer, alarm timer, impedance detection, oscillatorfaultoraftera device reset, the information about these different events is also available via corresponding bits within the status register; see Table 5.

A status I2C-bus read sequence resets the status register and pin CHI. Only after a change on any of the inputs D0 to D7, an I2C-bus read sequence of the status register, old register and new register is it necessary to reset pin CHI. The inputs D4 to D7 are maskable via the I2C-bus; see Table 8. All masked inputs (defined via the control register) are blocked to trigger pins CHI and RP. During the disable phase of the masked inputs the corresponding bits within the old and new registers will be continuously refreshed with the actual input level.

VL TIMER

INTERRUPT

IMPEDANCE

DETECTION

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Philips Semiconductors Product speciﬁcation

On/off logic IC SAA1305T

IMPEDANCE DETECTION Input D1 is a normal input with comparable behaviour like

the other seven inputs. The only difference is an additional internal exclusive-NOR (EXNOR) connected between the two comparator outputs for high and low detection; see Fig.4. The EXNOR signal indicates, in combination with a special external circuit on input D1, a voltage of

⁄2VDD on this input.

The simple input description for impedance detection is probably not the real solution, but helps to explain the function. Input D1 can be used as a normal input and for impedance detection as described in Table 2. For normal use the output Q acts like every other input, but for impedance detection the EXNOR output S is also important.Output Sislinkedtothe status register bit 6 and indicates the1⁄2VDD; see Table 5.

10 kΩ

5 V12 V

100 kΩ

input D1

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ignition

key

Between detection and indication via the status register bit 6, a delay time is integrated (programmable via the impedance register bits 1 and 0; see Table 15). When the

⁄2VDD value is detected the EXNOR output will be set to

logic 1 (active) and after the programmed delay time the statusregisterbit 6willbesettologic 1(active).Thisevent will also be indicated via pin CHI and (if enabled) pin RP. The impedance information (bit 6 is active) within the status register is present until the I2C-bus status is read. With the disappearance of the impedance information no further actions will be generated. Every impedance signal change during the delay time will restart the delay time. However an impedance detection is only possible in the event of a stable signal, at least for the programmed delay time. Setting the status register bit 6 with a repetition time which equals the ‘impedance delay time’ as long as input D1 stays in high-impedance state is implemented.

3.5 V

S R

100 kΩ

1.5 V

MGR203

Fig.4 Simple input description for impedance detection.

Table 2 Logic levels for impedance detection

IGNITION KEY O1 O2 Q S

12V 1010 Open-circuit (VI= 2.5 V) 0 0 0 or 1 1 Ground (VI<1.5V) 0100

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Philips Semiconductors Product speciﬁcation

On/off logic IC SAA1305T

Watchdog timer

An internal Watchdog timer is active after each reset pulse output and can be triggered via pin WD. In the event of a not specified pulse, a delayed or missing trigger pulse, a reset on pin RP will be the immediate reaction.

handbook, halfpage

(1) In the event of a not specified, a delayed or missing trigger signal, a reset on pin RP will be the immediate reaction. (2) The maximum time until signal change for first Watchdog timer is 500 ms. (3) The time until next signal change is minimum 200 ms and maximum 300 ms.

(1)

(2)

AftertheHIGH-to-LOWtransitionoftheresetpulseoutput, the first transition change within 500 ms on pin WD will be detected as the first trigger from the microcontroller. The timing diagram for the Watchdog timer trigger signal is shown in Fig.5.

(3)

MGR220

Fig.5 Watchdog timer trigger timing.

Oscillators

Two oscillator types are built-in, a RC oscillator (designed for 32.768 kHz) and a crystal oscillator (32.768 kHz), both with separate pins. For a proper device function an oscillator control circuit is integrated. This circuit supervises the oscillator function and creates a reset and oscillator restart in the event of an oscillator failure.

Intheevent of an oscillator fault, the event will be indicated after a restart via the status register bit 5. During the oscillator failure phase some outputs remain at a defined level as shown in Table 3.

The RC oscillator accuracy is 5%. When operating with the RCoscillator, pin XTAL2 must be

connected to VDDor VSS to minimize the quiescent current. When operating with the crystal oscillator pin OSC2 must be connected to VSSor VDD.

VL timer

A built-in timer, which can be started with a HIGH-to-LOW transition on pin

TS, triggers, after 250 ms, pins RP and CHI and sets pin ON/OFF. The VL timer starts only once after a valid start condition. Default state after a Power-on reset is not active. A VL timer start resets the Watchdog timer. During run time of the V

timer is

ON/OFF = LOW, CHI = 3-state and the Watchdog timer is disabled.

Pin TS is only active during the run mode. During run time of the VL timer the IC remains in the wait mode. Only a HIGH-level signal on input D0 can stop the VLtimer in the same way as after 250 ms. In the event of an oscillator fault the IC also enters the run mode but without an influence on the status register bit 2. During the wait mode an influence of the status register via other sources (e.g. timer and inputs) is possible, but a transition from wait mode to run mode is only possible as described above.

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Philips Semiconductors Product speciﬁcation

On/off logic IC SAA1305T

Power-on or system reset

Theresetinput (pin RES) is of the CMOS input levels type. During a LOW level on pin RES the outputs are as shown in Table 3 for RES = LOW.

Table 3 Logic levels for the reset input and oscillator failure

PIN RES=LOW RES = HIGH OSCILLATOR FAILURE

RP HIGH HIGH (voltage on VDD)

3-state [after a defined time (maximum reset time)] ON/OFF LOW HIGH LOW LED LOW LOW LOW SDA 3-state 3-state (receiving mode if RP = LOW) 3-state CHI 3-state LOW (information for microcontroller) LOW

Table 4 Deﬁned condition after reset for the registers; RES = HIGH

Status register 02 (HEX) New register all input latches are enabled Old register same levels as corresponding inputs during falling edge on pin RES Control register 03 (HEX) LED register 04 (HEX) Alarm register FFFF (HEX); see Table 7 Watch register 0000 (HEX) Impedance register 03 (HEX)

After the system reset (rising edge on pin RES) all internal registers are in a defined condition (see Table 4) and the outputs are as shown in Table 3 for RES = HIGH.

3-state

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