Philips saa1101 DATASHEETS
INTEGRATED CIRCUITS
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SAA1101
Universal sync generator (USG)
Product specification
File under Integrated Circuits, IC02
January 1990
Philips Semiconductors Product specification
Universal sync generator (USG) SAA1101
FEATURES
• Programmable to seven standards
• Additional outputs to simplify signal processing
• Can be synchronized to an external sync. signal
• Option to select the 524/624 line mode instead of the 525/625 line mode
• Lock from subcarrier to line frequency
GENERAL DESCRIPTION
The SAA1101 is a Universal Sync Generator (USG) and is designed for application in video sources such as cameras,
film scanners, video generators and associated apparatus. The circuit can be considered as a successor to the SAA1043
sync generator and the SAA1044 subcarrier coupling IC.
QUICK REFERENCE DATA
SYMBOL PARAMETER MIN. MAX. UNIT
V
I
DD
f
OSC
DD
supply voltage range (pin 28) 4.5 5.5 V
quiescent supply current − 10 µA
clock oscillator frequency − 24 MHz
ORDERING AND PACKAGE INFORMATION
EXTENDED
TYPE NUMBER
PINS PIN POSITION MATERIAL CODE
PACKAGE
SAA1101P 28 DIL plastic SOT117
SAA1101T 28 SO28 plastic SOT136A
Notes
1. SOT117-1; 1996 December 02.
2. SOT136-1; 1996 December 02.
(1)
(2)
January 1990 2
Philips Semiconductors Product specification
Universal sync generator (USG) SAA1101
, full pagewidth
CSCBBKIDHDVDWMP
18171615222120
13232434
LOGIC
COMBINING
CLP12RR
19
VLE11ECS
7
MGH191
SAA1101
PULSE
DIVIDER
VERTICAL
NORM SI
LOGIC
ADDITION/
SUPPRESSION
H
2f
LINE
DIVIDER
RESET
H
40f
SHAPER
VERTICAL
DETECTION
LOCK
VERTICAL
DETECTION
HORIZONTAL
H
f
HRI
ref
H
H
f
DIVIDER
SUBCARRIER
− ∆f
s
f
PHASE
SELECTION
LOCK MODE
DETECTION
81428 910
PH LM1 LM0
Fig.1 Block diagram.
H
CS1 CLOCS0
160f
PRESCALER
5
OSCI
6
OSCO
STANDARD
PROGRAMMED
252627
X
Y
January 1990 3
∆f
DIVIDER
Z
SUBCARRIER
SUBTRACTION
s
f
2
1
FSI
FSO
SS
V
DD
V
Philips Semiconductors Product specification
Universal sync generator (USG) SAA1101
PINNING
SYMBOL PIN DESCRIPTION
page
FSI
FSO
CS1
CS0
OSCI
OSCO
VLE
PH
LM1
LM0
ECS
RR
V
SS
1
2
3
4
5
6
7
SAA1101
8
9
10
11
12
SI
13
MGH190
28
27
26
25
24
23
22
21
20
19
18
17
16
1514
V
DD
Z
Y
X
CLO
NORM
HD
VD
WMP
CLP
CS
CB
BK
ID
Fig.2 Pinning configuration;
SOT117.
FUNCTIONAL DESCRIPTION
Generation of pulses
Generation of standard pulses such
as sync, blanking and burst for TV
systems: PAL B/G, PALN, PALM,
SECAM and NTSC. In addition a
number of non-standard pulses have
been supplied to simplify signal
processing. These signals include horizontal drive, vertical drive, clamp
pulse, identification etc. It is possible
to select the 524/624 line mode
instead of the 525/625 line mode for
all the above TV systems for
applications such as robotics, games
and computers.
FSI 1 subcarrier oscillator input, where f
FSO 2 subcarrier oscillator output
CS1 3 clock frequency selection - CMOS input
CS0 4 clock frequency selection - CMOS input
OSCI 5 clock oscillator input, where f
max
OSCO 6 clock oscillator output
VLE 7 vertical in-lock enable - CMOS input
PH 8 phase detector output - 3-state output
LM1 9 lock mode selection - CMOS input
LM0 10 lock mode selection - CMOS input
ECS 11 external composite sync. signal - CMOS Schmitt-trigger
input
RR 12 frame reset - CMOS Schmitt-trigger input
SI 13 set identification, used to set the correct field sequence in
P AL-mode. The correction (inversion of fH2) is done at the
left-hand slope of the SI-pulse. Minimum pulse width is
800 ns. CMOS Schmitt-trigger input.
V
SS
14 ground
ID 15 identification - push-pull output
BK 16 burst key (PAL/NTSC), chroma-blanking (SECAM) -
push-pull output
CB 17 composite blanking - push-pull output
CS 18 composite sync. - push-pull output
CLP 19 clamp pulse - push-pull output
WMP 20 white measurement pulse-3-state output
VD 21 vertical drive pulse - push-pull output
HD 22 horizontal drive pulse - push-pull output
NORM 23 used with X, Y and Z to select TV system; NORM = 0,
625/525 line mode (standard);
NORM = 1, 624/524 line mode - CMOS input
CLO 24 clock output - push-pull output
X 25 TV system selection input - CMOS input
Y 26 TV system selection input - CMOS input
Z 27 TV system selection input - CMOS input
V
DD
28 voltage supply
= 5 MHz
max
= 24 MHz
January 1990 4
Philips Semiconductors Product specification
Universal sync generator (USG) SAA1101
Lock modes
The USG offers four lock modes:
• Lock from the subcarrier
• Slow sync. lock, external H
• Slow sync. lock, internal H
• Fast sync. lock, internal H
ref
ref
ref
LOCK FROM SUBCARRIER
Lock from subcarrier to the line frequency for the above
mentioned TV systems is given below; the horizontal
frequency (fH) = 15.625 kHz for 625 line systems and
15.734264 kHz for 525 line systems.
SECAM (1 and 2) 282f
PALN 229.2516f
NTSC (1 and 2) 227.5f
PALM 227.25f
PAL B/G 283.7516f
H
H
H
H
H
These relationships are obtained by the use of a phase
locked loop and the internal programmed divider chain,
see Fig.3(a).
subcarrier input is, in this case, used as an external
input for the horizontal reference, see Fig.3(d).
SELECTION OF LOCK MODE
Lock mode is selected using the inputs LM0 and LM1 as
illustrated in the Table below.
LM0 LM1 SELECTION
0 0 lock to subcarrier
0 1 slow sync. lock external H
1 0 slow sync. lock internal H
1 1 fast sync. lock internal H
ref
ref
ref
LOCK TO AN EXTERNAL SIGNAL SOURCE
The following methods can be used to lock to an external
signal source:
1. Sync. lock slow; the line frequency is locked to an
external signal. The line and frame information are
extracted from the external sync. signal and used
separately in the lock system. The line information is
used in a phase-locked loop where external and
internal line frequencies are compared by the same
phase detector as is used for the subcarrier lock. The
external frame information is compared with the
internal frame in a slow lock system; mismatch of
internal and external frames will result in the addition
or suppression of one line depending on the direction
of the fault. The maximum lock time for frame lock is
6.25 s, see Fig.3(b).
2. Sync. lock fast. A fast lock of frames is possible with a
frame reset which is extracted out of the incoming
external sync. signal, see Fig.3(c).
3. Sync. lock with external reference. Lock of an external
sync. signal to the line frequency with an external line
reference to make possible a shifted lock. The
January 1990 5
Philips Semiconductors Product specification
Universal sync generator (USG) SAA1101
The different lock modes are illustrated by the following figures:
handbook, halfpage
SUB-
CARRIER
OSCILLATOR
Fig.3 (a) Lock to subcarrier.
n × f
H
LINE
OSCILLATOR
OSCO OSCI
FSI
FSO
65
1
SAA1101
2
10
logic 0 logic 1
PH
8
9
LM1LM0
MGH193
handbook, halfpage
ECS
n × f
H
LINE
OSCILLATOR
OSCO OSCI
65
11
SAA1101
10
logic 1 logic 1
9
Fig.3 (c) Fast sync lock, internal H
PH
8
LM1LM0
MGH195
ref
handbook, halfpage
OSCO OSCI
ECS
Fig.3 (b) Slow sync lock, internal H
n × f
H
LINE
OSCILLATOR
65
11
SAA1101
10
logic 0 logic 1
9
PH
8
LM1LM0
MGH194
ref
January 1990 6
handbook, halfpage
τ
H
ref
n × f
H
LINE
OSCILLATOR
H
D OSCO OSCI
65
22
FSI
1
ECS
SAA1101
11
10
logic 0 logic 1
9
LM1LM0
PH
8
MGH192
Fig.3 (d) Slow sync lock, external H
ref
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