Philips sa8016 DATASHEETS
INTEGRATED CIRCUITS
SA8016
2.5GHz low voltage fractional-N
synthesizer
Product specification
Supersedes data of 1999 Apr 16
1999 Nov 04
Philips Semiconductors Product specification
TYPE NUMBER
SA80162.5GHz low voltage fractional-N synthesizer
GENERAL DESCRIPTION
The SA8016 BICMOS device integrates programmable dividers,
charge pumps and a phase comparator to implement a
phase-locked loop. The device is designed to operate from 3 NiCd
cells, in pocket phones, with low current and nominal 3 V supplies.
The synthesizer operates at VCO input frequencies up to 2.5 GHz.
The synthesizer has fully programmable main and reference
dividers. All divider ratios are supplied via a 3-wire serial
programming bus.
Separate power and ground pins are provided to the analog and
digital circuits. The ground leads should be externally short-circuited
to prevent large currents flowing across the die and thus causing
damage. V
must be greater than or equal to V
DDCP
DD
.
The charge pump current (gain) is set by an external resistance at
the R
pin. Only passive loop filters could be used; the charge
SET
pump operates within a wide voltage compliance range to provide a
wider tuning range.
FEA TURES
•Low phase noise
•Low power
•Fully programmable main divider
•Internal fractional spurious compensation
•Hardware and software power down
•Split supply for V
APPLICATIONS
DD
and V
DDCP
•350–2500 MHz wireless equipment
•Cellular phones (all standards)
•WLAN
•Portable battery-powered radio equipment.
1
LOCK
2
TEST
3
V
DD
4
GND
5
RFin+
6
RFin–
7
GND
CP
89
PHP
PON
16
15
STROBE
14
DATA
13
CLOCK
12
REFin+
11
REFin–
10
R
V
SR01505
SET
DDCP
Figure 1. TSSOP16 Pin Configuration
V
GND
RFin+
RFin–
DDPre
GND
N/C
DD
LOCK
TEST
V
1
2
3
Pre
TOP VIEW
4
5
6
8 9 10 11 12
CP
GND
PHP
N/C
V
N/C
PON
DDCP
STROBE
2021222324
SET
R
N/C
19
18
17
16
15
14
137
Figure 2. HBCC24 Pin configuration
DATA
CLOCK
REFin+
REFin–
N/C
N/C
SR02174
QUICK REFERENCE DATA
ORDERING INFORMATION
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
V
DD
V
DDCP
I
DDCP+IDD
I
DDCP+IDD
f
VCO
f
REF
f
PC
T
amb
Supply voltage 2.7 — 5.5 V
Analog supply voltage V
DDCP
≥ V
DD
2.7 — 5.5 V
Total supply current — 8.0 9.5 mA
Total supply current in power-down mode — 1 — µA
Input frequency 350 — 2500 MHz
Crystal reference input frequency 5 — 40 MHz
Maximum phase comparator frequency — 4 MHz
Operating ambient temperature –40 — +85 °C
PACKAGE
NAME DESCRIPTION VERSION
SA8016DH TSSOP16 Plastic thin shrink small outline package; 16 leads; body width 4.4 mm SOT403-1
SA8016WC HBCC24 Plastic, heatsink bottom chip carrier; 24 terminals; body 4 × 4 × 0.65 mm (CSP package) SOT564-1
1999 Nov 04 853–2142 22636
2
Philips Semiconductors Product specification
SA80162.5GHz low voltage fractional-N synthesizer
GND
CLOCK
DATA
STROBE
13
14
15
2–BIT SHIFT
REGISTER
ADDRESS DECODER
LOAD SIGNALS
22–BIT SHIFT
REGISTER
CONTROL
LATCH
CURRENT
PUMP
SETTING
PUMP
BIAS
4
10
R
SET
9
V
DDCP
RFin+
RFin–
REF
REF
TEST
5
6
AMP
12
in+
in–
11
2
MAIN DIVIDER
LATCH
REFERENCE
DIVIDER
Figure 3. Block Diagram (TSSOP16)
TSSOP16 PIN DESCRIPTION
SYMBOL PIN DESCRIPTION
LOCK 1 Lock detect output
TEST 2 Test (should be either grounded or
V
DD
GND 4 Digital ground
RFin+ 5 RF input to main divider
RFin– 6 RF input to main divider
GND
CP
PHP 8 Main normal charge pump
V
DDCP
R
SET
REFin– 11 Reference input
REFin+ 12 Reference input
CLOCK 13 Programming bus clock input
DATA 14 Programming bus data input
STROBE 15 Programming bus enable input
PON 16 Power down control
connected to VDD)
3 Digital supply
7 Charge pump ground
9 Charge pump supply voltage
10 External resistor from this pin to ground
sets the charge pump current
LATCH
COMP
8
PHASE
DETECTOR
3
V
DD
PHP
7
GND
1
16
CP
LOCK
PON
SR01506
1999 Nov 04
3
Philips Semiconductors Product specification
SA80162.5GHz low voltage fractional-N synthesizer
HBCC24 PIN DESCRIPTION
SYMBOL PIN DESCRIPTION
V
DDPre
GND 2 Digital ground
GND
Pre
RFin+ 4 RF input to main divider
RFin– 5 RF input to main divider
N/C 6 Not connected
N/C 7 Not connected
GND
CP
PHP 9 Main normal charge pump
N/C 10 Not connected
V
DDCP
R
SET
N/C 13 Not connected
N/C 14 Not connected
REFin– 15 Reference input
REFin+ 16 Reference input
CLOCK 17 Programming bus clock input
DATA 18 Programming bus data input
N/C 19 Not connected
STROBE 20 Programming bus enable input
PON 21 Power down control
LOCK 22 Lock detect output
TEST 23 Test (should be either grounded or
V
DD
NOTE:
1. GND
CP
1 Prescaler supply voltage
3 Prescaler ground
8 Charge pump ground
11 Charge pump supply voltage
12 External resistor from this pin to ground
sets the charge pump current
connected to VDD)
24 Digital supply
is connected to the die-pad.
1999 Nov 04
4
Philips Semiconductors Product specification
SA80162.5GHz low voltage fractional-N synthesizer
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 134).
SYMBOL
V
DD
V
DDCP
∆V
DDCP–VDD
V
n
V
1
∆V
GND
T
stg
T
amb
T
j
Digital supply voltage –0.3 +5.5 V
Analog supply voltage –0.3 +5.5 V
Difference in voltage between V
Voltage at pins 1, 2, 5, 6, 11 to 16 –0.3 V
Voltage at pin 8, 9 –0.3 V
Difference in voltage between GNDCP and GND (these pins should be
connected together)
Storage temperature –55 +125 °C
Operating ambient temperature –40 +85 °C
Maximum junction temperature 150 °C
Handling
Inputs and outputs are protected against electrostatic discharge in
normal handling. However , to be totally safe, it is desirable to take
normal precautions appropriate to handling MOS devices.
PARAMETER MIN. MAX. UNIT
DDCP and
VDD (V
≥ VDD) –0.3 +2.8 V
DDCP
+ 0.3 V
DD
+ 0.3 V
DDCP
–0.3 +0.3 V
THERMAL CHARACTERISTICS
SYMBOL PARAMETER VALUE UNIT
R
th j–a
Thermal resistance from junction to ambient in free air 120 K/W
1999 Nov 04
5
Philips Semiconductors Product specification
SA80162.5GHz low voltage fractional-N synthesizer
CHARACTERISTICS
= V
= +3.0V, T
DD
V
DDCP
SYMBOL
Supply; pins 3, 9
V
DD
V
DDCP
I
DDTotal
I
Standby
Digital supply voltage 2.7 – 5.5 V
Analog supply voltage V
Synthesizer operational total supply current V
Total supply current in power-down mode logic levels 0 or V
RFin main divider input; pins 5, 6
f
VCO
V
RFin(rms)
Z
IRFin
C
IRFin
N
main
f
PCmax
VCO input frequency 350 – 2500 MHz
AC-coupled input signal level Rin (external) = Rs = 50Ω;
Input impedance (real part) f
Typical pin input capacitance f
Main divider ratio 512 – 65535
Maximum loop comparison frequency indicative, not tested – – 4 MHz
Reference divider input; pins 11, 12
f
REFin
Input frequency range from TCXO 5 – 40 MHz
VRFin AC-coupled input signal level single-ended drive;
Z
C
R
REFin
REFin
REF
Input impedance (real part) f
Typical pin input capacitance f
Reference division ratio 4 – 1023
Charge pump current setting resistor input; pin 10
R
SET
V
SET
External resistor from pin to ground 6 7.5 15 kΩ
Regulated voltage at pin R
Charge pump outputs (including fractional compensation pump); pin 8; R
I
CP
I
MATCH
I
ZOUT
I
LPH
V
PH
Charge pump current ratio to I
Sink-to-source current matching VPH=1/2 V
Output current variation versus V
Charge pump off leakage current VPH=1/2 V
Charge pump voltage compliance 0.7 – V
= +25°C; unless otherwise specified.
amb
PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
= V
DDCP
DD
DD
= +3.0 V – 8.0 9.5 mA
DD
2.7 – 5.5 V
– 1 µA
–18 – 0 dBm
single-ended drive;
max. limit is indicative
@ 500 to 2500 MHz
= 2.4 GHz – 210 – Ω
VCO
= 2.4 GHz – 1.0 – pF
VCO
360 – 1300 mV
max. limit is indicative
= 20 MHz – 10 – kΩ
REF
= 20 MHz – 1.0 – pF
REF
=7.5 kΩ – 1.25 – V
SET
=7.5kΩ, FC=80
SET
SET
PH
1
2
Current gain IPH/I
V
in compliance range –10 +10 %
PH
SET
DDCP
CC
–15 +15 %
–10 +10 %
–10 +10 nA
DDCP
PP
–0.8 V
1999 Nov 04
6
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