Philips sa703 DATASHEETS

Philips Semiconductors Product specification

Divide by: 128/129/144 triple modulus low power
ECL prescaler

DESCRIPTION

The SA703 triple modulus (Divide By 128/129/144) low power ECL
prescaler is used in synthesizer systems to achieve low phase lock
time, broad operating range, high reference frequency and small
frequency step sizes. The minimum supply voltage is 2.7V and is
compatible with the UMA1005 synthesizer from Philips and other
logic circuits. The low supply current allows application in battery
operated low-power equipment. Maximum input signal frequency is

1.1GHz for cellular and other land mobile applications. There is no
lower frequency limit due to a fully static design. The circuit is
implemented in ECL technology on the QUBiC process. The circuit
will be available in an 8-pin SO package with 150 mil package width
and in 8-pin dual in-line plastic package.

APPLICATIONS

•Cellular phones

•Cordless phones

•RF LANs

•Test and measurement

•Military radio

PIN CONFIGURATION

•VHF/UHF mobile radio

•VHF/UHF hand-held radio

FEA TURES

•Low voltage operation

•Low current consumption

•Operation up to 1.1GHz

•ESD hardened

N, D Package

1

IN

2

V

CC

3

MC2

45

OUT

Figure 1. Pin Configuration

IN

8

7

GND

6

MC1

OUT

SA703

SR00551

ORDERING INFORMATION

DESCRIPTION TEMPERATURE RANGE ORDER CODE DWG #

8-Pin Plastic Dual In-Line Package (DIP)
8-Pin Plastic Small Outline (SO) package (Surface-mount)

-40 to +85°C

-40 to +85°C

SA703N SOT97-1
SA703D SOT96-1

ABSOLUTE MAXIMUM RATINGS

SYMBOL PARAMETER RATING UNITS

V

CC

V

IN

I

O

T

STG

T

A

θ

JA

Supply voltage -0.3 to +7.0 V
Voltage applied to any other pin -0.3 to (VCC + 0.3) V
Output current 10 mA
Storage temperature range -65 to +125 °C
Operating ambient temperature range -55 to +125 °C
Thermal impedance D package

N package

158
108

°C/W

1993 Jun 17 853-1710 10044

7–17

Philips Semiconductors Product specification

Divide by: 128/129/144 triple modulus low power ECL
prescaler

BLOCK DIAGRAM

OUT

SA703

OUT

Q

D

Q

D

QQ

D

QQ

D

Q

D

LOGIC

MODULUS CONTROL

Q

D

Q

D

Q

D

QQ

D

1993 Jun 17

IN

IN

MC1

MC2

SR00552

Figure 2. Block Diagram

7–18

Philips Semiconductors Product specification

SYMBOL

PARAMETER

TEST CONDITIONS

UNITS

SYMBOL

PARAMETER

TEST CONDITIONS

UNITS

fINI

GH

VOOutput

V

Divide by: 128/129/144 triple modulus low power ECL
prescaler

DC ELECTRICAL CHARACTERISTICS

The following DC specifications are valid for TA = 25°C and VCC = 3.0V; unless otherwise stated. Test circuit Figure 4.

LIMITS

MIN TYP MAX

V

I
V
V

V

V

V

V

AC ELECTRICAL CHARACTERISTICS

These AC specifications are valid for VCC = 3.0V, fIN = 1GHz, input level = 0dBm, TA = 25°C; unless otherwise stated. Test circuit Fig. 4.

V

R

t

NOTES:

1. Maximum limit is not tested, however, it is guaranteed by design and characterization.

2. For f

DESCRIPTION OF OPERATION

The SA703 comprises a frequency divider circuit implemented using
a divide by 4 or 5 synchronous prescaler followed by a 5 stage
synchronous counter, see BLOCK DIAGRAM. The normal
operating mode is for MC1 (Modulus Control) to be set high and
MC2 input to be set low in which case the circuit comprises a divide
by 128. For divide by 129 the MC1 singal is forced low, causing the
prescaler circuit to switch into divide by 5 operation for the last cycle
of the synchronous counter. For divide by 144, MC2 is set high
configuring the prescaler to divide by 4 and the counter to divide by

36. A truth table for the modulus values is given in Table 1.
For minimization of propagation delay effects, the second divider

circuit is synchronous to the divide by 4/5 stage output.
The prescaler input is positive edge sensitive, and the output at the

final count is a falling edge with propagation delay t

Power supply voltage range fIN = 1GHz, input level = 0dBm 2.7 6.0 V

CC

Supply current No load 4.5 mA

CC

Output high level I

OH

Output low level VCC-2.6 V

OL

MC1 input high threshold 2.0 V

IH

MC1 input low threshold –0.3 0.8 V

IL

MC2 input high threshold 2.0 V

IH

MC2 input low threshold –0.3 0.8 V

IL

I

MC1 input high current V

IH

I

MC1 input low current V

IL

I

MC2 input high current V

IH

I

MC2 input low current V

IL

= 1.2mA VCC-1.4 V

OUT

= VCC = 6V 0.1 50 µA

MC1

= 0V, VCC = 6V –100 –30 µA

MC1

= VCC = 6V 0.1 50 µA

MC2

= 0V, VCC = 6V –100 –30 µA

MC2

LIMITS

MIN TYP MAX

Input signal amplitude

IN

nput signal frequency

Differential input resistance DC measurement 5 kΩ

ID

voltage

t

Modulus set-up time

S

t

Modulus hold time

H

Propagation time 10 ns

PD

< 50MHz, minimum input slew rate of 32V/µs is required.

IN

1

1000pF input coupling 0.05 2.0 V

Direct coupled input

2

0 1.1

1000pF input coupling 1.1

VCC = 5.0V 1.6
VCC = 3.0V 1.2

1

1

input. The rising edge of the output occurs at the count 64 with

PD

.

delay t
The MC1 and MC2 inputs are TTL compatible threshold inputs

operating at a reduced input current. CMOS and low voltage
interface capability are allowed.

The prescaler input is differential and ECL compatible. The output is
differential ECL compatible.

Table 1.

Modulus MC1 MC2

128 1 0
129 0 0
144 0 1

relative to the

PD

144 1 1

SA703

CC

CC

5 ns
0 ns

V

V

P-P

z

P-P

1993 Jun 17

7–19