Philips sa703 DATASHEETS

Philips Semiconductors	Product specification

Divide by: 128/129/144 triple modulus low power

SA703

ECL prescaler

DESCRIPTION

The SA703 triple modulus (Divide By 128/129/144) low power ECL prescaler is used in synthesizer systems to achieve low phase lock time, broad operating range, high reference frequency and small frequency step sizes. The minimum supply voltage is 2.7V and is compatible with the UMA1005 synthesizer from Philips and other logic circuits. The low supply current allows application in battery operated low-power equipment. Maximum input signal frequency is 1.1GHz for cellular and other land mobile applications. There is no lower frequency limit due to a fully static design. The circuit is implemented in ECL technology on the QUBiC process. The circuit will be available in an 8-pin SO package with 150 mil package width and in 8-pin dual in-line plastic package.

APPLICATIONS

•Cellular phones

•Cordless phones

•RF LANs

•Test and measurement

•Military radio

PIN CONFIGURATION

N, D Package

IN	1				8	IN
VCC	2				7		GND
MC2	3				6	MC1
OUT	4				5		OUT

SR00551

Figure 1. Pin Configuration

•VHF/UHF mobile radio

•VHF/UHF hand-held radio

FEATURES

•Low voltage operation

•Low current consumption

•Operation up to 1.1GHz

•ESD hardened

ORDERING INFORMATION

	DESCRIPTION		TEMPERATURE RANGE			ORDER CODE		DWG #
8-Pin Plastic Dual In-Line Package (DIP)			-40 to +85°C			SA703N		SOT97-1
8-Pin Plastic Small Outline (SO) package (Surface-mount)			-40 to +85°C			SA703D		SOT96-1
ABSOLUTE MAXIMUM RATINGS
SYMBOL		PARAMETER			RATING			UNITS
VCC	Supply voltage			-0.3 to +7.0				V
VIN	Voltage applied to any other pin			-0.3 to (VCC + 0.3)				V
IO	Output current				10			mA
TSTG	Storage temperature range			-65 to +125				°C
TA	Operating ambient temperature range			-55 to +125				°C
θJA	Thermal impedance	D package			158			°C/W
		N package			108

1993 Jun 17

7±17

853-1710 10044

Philips Semiconductors	Product specification

Divide by: 128/129/144 triple modulus low power ECL

SA703

prescaler

BLOCK DIAGRAM

				OUT	OUT
				Q
				D
				Q
				D
				Q
			CONTROLMODULUS	D
Q	Q			LOGIC
D
				Q
				D
Q	Q
D
				Q
Q
				D
D
				Q	Q
				D
	IN	IN	MC1	MC2	SR00552

Figure 2. Block Diagram

1993 Jun 17

7±18

Philips Semiconductors	Product specification

Divide by: 128/129/144 triple modulus low power ECL

SA703

prescaler

DC ELECTRICAL CHARACTERISTICS

The following DC specifications are valid for TA = 25°C and VCC = 3.0V; unless otherwise stated. Test circuit Figure 4.

	SYMBOL	PARAMETER	TEST CONDITIONS		LIMITS		UNITS
				MIN	TYP	MAX
	VCC	Power supply voltage range	fIN = 1GHz, input level = 0dBm	2.7		6.0	V
	ICC	Supply current	No load		4.5		mA
	VOH	Output high level	IOUT = 1.2mA	VCC-1.4			V
	VOL	Output low level			VCC-2.6		V
	VIH	MC1 input high threshold		2.0		VCC	V
	VIL	MC1 input low threshold		±0.3		0.8	V
	VIH	MC2 input high threshold		2.0		VCC	V
	VIL	MC2 input low threshold		±0.3		0.8	V
	IIH	MC1 input high current	VMC1 = VCC = 6V		0.1	50	μA
	IIL	MC1 input low current	VMC1 = 0V, VCC = 6V	±100	±30		μA
	IIH	MC2 input high current	VMC2 = VCC = 6V		0.1	50	μA
	IIL	MC2 input low current	VMC2 = 0V, VCC = 6V	±100	±30		μA

AC ELECTRICAL CHARACTERISTICS

These AC specifications are valid for VCC = 3.0V, fIN = 1GHz, input level = 0dBm, TA = 25°C; unless otherwise stated. Test circuit Fig. 4.

	SYMBOL	PARAMETER	TEST CONDITIONS		LIMITS		UNITS
				MIN	TYP	MAX
	V	Input signal amplitude1	1000pF input coupling	0.05		2.0	V	P-P
	IN
	fIN	Input signal frequency	Direct coupled input2	0		1.1	GHz
			1000pF input coupling			1.1
	RID	Differential input resistance	DC measurement		5		kΩ
	VO	Output voltage	VCC = 5.0V		1.6		VP-P
			VCC = 3.0V		1.2
	t	Modulus set-up time1				5	ns
	S
	t	Modulus hold time1				0	ns
	H
	tPD	Propagation time			10		ns

NOTES:

1.Maximum limit is not tested, however, it is guaranteed by design and characterization.

2.For fIN < 50MHz, minimum input slew rate of 32V/μs is required.

DESCRIPTION OF OPERATION

The SA703 comprises a frequency divider circuit implemented using a divide by 4 or 5 synchronous prescaler followed by a 5 stage synchronous counter, see BLOCK DIAGRAM. The normal operating mode is for MC1 (Modulus Control) to be set high and MC2 input to be set low in which case the circuit comprises a divide by 128. For divide by 129 the MC1 singal is forced low, causing the prescaler circuit to switch into divide by 5 operation for the last cycle of the synchronous counter. For divide by 144, MC2 is set high configuring the prescaler to divide by 4 and the counter to divide by 36. A truth table for the modulus values is given in Table 1.

For minimization of propagation delay effects, the second divider circuit is synchronous to the divide by 4/5 stage output.

The prescaler input is positive edge sensitive, and the output at the final count is a falling edge with propagation delay tPD relative to the

input. The rising edge of the output occurs at the count 64 with delay tPD.

The MC1 and MC2 inputs are TTL compatible threshold inputs operating at a reduced input current. CMOS and low voltage interface capability are allowed.

The prescaler input is differential and ECL compatible. The output is differential ECL compatible.

Table 1.

Modulus	MC1	MC2
128	1	0
129	0	0
144	0	1
144	1	1

1993 Jun 17

7±19