Philips SA7026DK Datasheet
SA7026
1.3GHz low voltage fractional-N dual
frequency synthesizer
Objective specification
Supersedes data of 1998 Apr 06
1998 Oct 13
INTEGRATED CIRCUITS
Philips Semiconductors Objective specification
SA70261.3GHz low voltage fractional-N dual synthesizer
2
1998 Oct 13
FEATURES
•Low phase noise
•Low power
•Fully programmable main and auxiliary dividers
•NORMAL & INTEGRAL charge pumps outputs
•Fast Locking Adaptive mode design
•Internal fractional spurious compensation
•Hardware and software power down
APPLICATIONS
•500–1300 MHz wireless equipment
•Cellular phones
•Portable battery-powered radio equipment.
General description
The SA7026 BICMOS device integrates programmable dividers,
charge pumps and a phase comparator to implement a
phase-locked loop. The device is designed to operate from 3 NiCd
cells, in pocket phones, with low current and nominal 3 V supplies.
The synthesizer operates at VCO input frequencies up to 1.3 GHz.
The synthesizer has fully programmable main, auxiliary and
reference dividers. All divider ratios are supplied via a 3-wire serial
programming bus.
Separate power and ground pins are provided to the analog and
digital circuits. The ground leads should be externally short-circuited
to prevent large currents flowing across the die and thus causing
damage. V
DDCP
could be greater than or equal to V
DD
.
The charge pump current (gain) is fixed by an external resistance at
pin R
SET (pin ). Only passive loop filters are used; the charge-pump
operates within a wide voltage compliance range to provide a wider
tuning range.
SR01649
1
2
3
4
5
6
7
8
9
11
12
13
14
15
16
17
18
19
20
LOCK
TEST
V
DD
GND
RFin+
RFin–
GND
CP
PHP
PHI
GND
CP
PON
STROBE
DATA
CLOCK
REF
in
+
REF
in
–
RSET
AUXin
V
DDCP
PHA
10
Figure 1. Pin Configuration
QUICK REFERENCE DA TA
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
V
DD
Supply voltage V
DD
2.7 – 5.5 V
V
DDCP
Analog supply voltage V
DDCP
≥ V
DD
2.7 – 5.5 V
I
DDCP+IDD
Supply current Main and Aux. on – 7.5 8.8 mA
I
DDCP+IDD
Total supply current in power-down mode – 1 – µA
f
VCO
Input frequency 500 – 1300 MHz
f
AUX
Input frequency 10 – 550 MHz
f
REF
Crystal reference input frequency 10 – 40 MHz
f
PC
Maximum phase comparator frequency – 4 MHz
T
amb
Operating ambient temperature –40 – +85 °C
ORDERING INFORMATION
PACKAGE
TYPE NUMBER
NAME DESCRIPTION VERSION
SA7026DK TSSOP20 Plastic thin shrink small outline package; 20 leads; body width 4.4 mm SOT360–1
Philips Semiconductors Objective specification
SA70261.3GHz low voltage fractional-N dual synthesizer
1998 Oct 13
3
SR01496
CLOCK
DATA
STROBE
RFin+
RFin–
REF
in+
REF
in–
AUXin
TEST
LOAD SIGNALS
ADDRESS DECODER
2–BIT SHIFT
REGISTER
22–BIT SHIFT
REGISTER
CONTROL
LATCH
LATCH
MAIN DIVIDER
SM
REFERENCE
DIVIDER
2222
LATCH
AMP
AMP
15
16
6
5
19
18
17
12
2
LATCH
AUX DIVIDER
PHASE
DETECTOR
PHASE
DETECTOR
COMP
PUMP
BIAS
PUMP
CURRENT
SETTING
13
V
DDCP
GND
4
SA
103
GND
CP
V
DD
RSET
GND
CP
PHP
PHI
LOCK
PHA
PUMP
BIAS
14
7
8
9
1
11
PON
20
Figure 2. Block Diagram
PINNING
SYMBOL PIN DESCRIPTION
LOCK 1 Lock detect output
TEST 2 Test
V
DD
3 Digital supply
GND 4 Digital ground
RFin+ 5 RF positive input to main divider
RFin– 6 RF negative input to main divider
GND
CP
7 Charge pump ground
PHP 8 Main NORMAL chargepump
PHI 9 Main INTEGRAL chargepump
GND
CP
10 Charge Pump Ground
SYMBOL PIN DESCRIPTION
PHA 11 Auxiliary chargepump output
AUXin 12 Input to auxiliary divider
V
DDCP
13 Charge pump supply voltage
RSET 14 External resistor from this pin to ground
sets the chargepump current
REF
in–
15 Reference input
REF
in+
16 Reference input
CLOCK 17 Programming bus clock input
DATA 18 Programming bus data input
STROBE 19 Programming bus enable input
PON 20 Power down control
Philips Semiconductors Objective specification
SA70261.3GHz low voltage fractional-N dual synthesizer
1998 Oct 13
4
Characteristics
V
DDCP
= V
DD
= +3.0V, T
amb
= +25°C; unless otherwise specified.
SYMBOL
PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
Supply; pins 3, 13
V
DD
Digital supply voltage 2.7 – 5.5 V
V
DDCP
Analog supply voltage V
DDCP
= V
DD
2.7 – 5.5 V
I
DDTotal
Synthesizer operational digital supply current V
DD
= +3.0 V
(with main and aux on)
– 7.5 8.8 mA
I
standby
Total supply current in power-down mode logic levels 0 or VDD – 1 TBD µA
RFin main divider input; pins 5, 6
p
–
f
VCO
VCO in ut frequency
500–1300
MHz
p
p
;
V
RFin(rms)
AC-coupled input signal level
R
s
= 50 Ω;
MAX. limit is
–
18–0
dBm
indicative
Z
IRFin
Input impedance (real part) f
VCO
= 2.0 GHz – TBD – kΩ
C
IRFin
Typical pin input capacitance indicative, not tested – TBD – pF
N
m
Main divider ratio 512 – 65535
f
PCmax
Maximum loop comparison frequency indicative, not tested – – 4 MHz
AUX reference divider input; pins 12
f
AUXin
Input frequency range 10 – 550 MHz
p
p
R
=50Ω; MAX. limit is
–18 – 0 dBm
V
AUXin
AC-coupled input signal level
Rs50Ω MAX. limit is
indicative
80 – 636 mVpp
Z
AUXin
Input impedance (real part) f
VCO
=500 MHz – TBD – kΩ
C
AUXin
Typical pin input capacitance indicative, not tested – TBD – pF
N
AUX
Auxiliary division ratio 128 – 16384
Reference divider input; pins 15, 16
f
REFin
Input frequency range from crystal 10 – 40 MHz
VRFin AC-coupled input signal level RS=50Ω; MAX. limit is 360 – 1300 mVpp
g
S
indicative
Z
REFin
Input impedance (real part) – TBD – kΩ
C
REFin
Typical pin input capacitance indicative, not tested – TBD – pF
R
REF
Reference division ratio SA=SM=”000” 4 – 1023
Charge pump current setting resistor input; pin 14
R
SET
External resistor from pin 3 to ground 6 7.5 24 kΩ
V
SET
Regulated voltage at pin 3 R
SET
=7.5 kΩ – 1.25 – V
Charge pump outputs (including fractional compensation pump); pins 8, 9, 11; R
SET
=7.5 kΩ, FC=80
Icp Chargepump current ratio to Iset CURRENT GAIN
I
PH/ISET
–15 +15 %
I
MATCH
Sink-to-source current matching Vph=1/2 V
DDCP
–10 +10 %
I
ZOUT
Output current variation versus V
ph
2
V
ph
in compliance
range
–10 +10 %
I
LPH
Charge pump off leakage current Vcp=1/2 V
CC
–10 +10 nA
V
ph
Charge pump voltage compliance 0.7 – V
DDCP
–0.8 V
Philips Semiconductors Objective specification
SA70261.3GHz low voltage fractional-N dual synthesizer
1998 Oct 13
5
SYMBOL UNITMAX.TYP.MIN.CONDITIONSPARAMETER
Phase noise
C/N Synthesizer’s contribution to close-in-phase noise of
1300 MHz RF signal at 1 kHz offset.
fref=19.44MHz;
fcomp=240kHz
indicative, not tested
– –77 – dBc
Hz
Interface logic input signal levels; pins 3, 15, 16, 18, 19, 20
V
IH
HIGH level input voltage 0.7*V
DD
– VDD+0.3 V
V
IL
LOW level input voltage –0.3 – 0.3*V
DD
V
I
bias
Input bias current logic 1 or logic 0 –5 – +5 µA
Lock detect output signal (in push/pull mode); pin 1
V
OL
LOW level output voltage I
sink
= 2mA – – 0.4 V
V
OH
HIGH level output voltage I
source
= –2mA VDD–0.4 – – V
NOTES:
1. I
SET =
V
SET
R
SET
bias current for charge pumps.
2. The relative output current variation is defined thus:
I
OUT
I
OUT
2
.
(I2–I1)
I(I
2
I1)I
; with V1 0.7V, V2 V
DDCP
–0.8V (See Figure 3.)
I
2
I
1
I
2
I
1
V
1
V
2
CURRENT
VOLTAGE
SR00602
Figure 3. Relative Output Current Variation
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