Philips SA7025DK Datasheet

INTEGRATED CIRCUITS

SA7025

Low-voltage 1GHz fractional-N synthesizer

Product specification

1996 Aug 6

IC17 Data Handbook

m n r

Philips Semiconductors	Product specification
1GHz low-voltage Fractional-N synthesizer	SA7025

DESCRIPTION

The SA7025 is a monolithic low power, high performance dual frequency synthesizer fabricated in QUBiC BiCMOS technology.

Featuring Fractional-N division with selectable modulo 5 or 8 implemented in the Main synthesizer to allow the phase detector comparison frequency to be five or eight times the channel spacing. This feature reduces the overall division ratio yielding a lower noise floor and faster channel switching. The phase detectors and charge pumps are designed to achieve phase detector comparison frequencies up to 5MHz. A triple modulus prescaler (divide by

64/65/72) is integrated on chip with a maximum input frequency of

1.04GHz. Programming and channel selection are realized by a high speed 3-wire serial interface.

FEATURES

•Operation up to 1.04GHz

•Fast locking by ªFractional-Nº divider

•Auxiliary synthesizer

•Digital phase comparator with proportional and integral charge pump output

•High speed serial input

•Low power consumption

•Programmable charge pump currents

•Supply voltage range 2.7 to 5.5V

•Excellent input sensitivity: VRF_IN = ±20dBm

PIN CONFIGURATION

DK Package

CLOCK								VDD
			1				20
DATA								TEST
			2				19
								LOCK
STROBE			3				18
	VSS
			4				17	RF
RFIN
			5				16	RN
RFIN			6				15	VDDA
VCCP			7				14	PHP
								PHI
REFIN			8				13
	RA		9				12	VSSA
AUXIN								PHA
			10				11

SR00600

Figure 1. Pin Configuration

APPLICATIONS

•NADC (North American Digital Cellular)

•PDC (Personal Digital Cellular)

•Cellular radio

•Spread-spectrum receivers

ORDERING INFORMATION

DESCRIPTION	TEMPERATURE RANGE	ORDER CODE	DWG #
20-Pin Plastic Shrink Small Outline Package (SSOP)	±40 to +85°C	SA7025DK	SOT266-1

ABSOLUTE MAXIMUM RATINGS

SYMBOL	PARAMETER	RATING	UNITS
V	Supply voltage, VDD, VDDA, VCCP	-0.3 to +6.0	V
VIN	Voltage applied to any other pin	-0.3 to (VDD + 0.3)	V
TSTG	Storage temperature range	-65 to +150	°C
TA	Operating ambient temperature range	-40 to +85	°C

NOTE: Thermal impedance (θJA) = 117°C/W. This device is ESD sensitive.

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853-1786 17157

Philips Semiconductors	Product specification
1GHz low-voltage Fractional-N synthesizer	SA7025

PIN DESCRIPTIONS

Symbol			Pin	Description
CLOCK			1	Serial clock input
DATA			2	Serial data input
STROBE			3	Serial strobe input
	VSS		4	Digital ground
	RFIN		5	Prescaler positive input
			6	Prescaler negative input
	RFIN
VCCP			7	Prescaler positive supply voltage. This pin supplies power to the prescaler and RF input buffer
REFIN			8	Reference divider input
	RA		9	Auxiliary current setting; resistor to VSSA
AUXIN			10	Auxiliary divider input
	PHA		11	Auxiliary phase detector output
VSSA			12	Analog ground
	PHI		13	Integral phase detector output
	PHP		14	Proportional phase detector output
VDDA			15	Analog supply voltage. This pin supplies power to the charge pumps, Auxiliary prescaler, Auxiliary and Reference
				buffers.
	RN		16	Main current setting; resistor to VSSA
	RF		17	Fractional compensation current setting; resistor to VSSA
LOCK			18	Lock detector output
TEST			19	Test pin; connect to VDD
	VDD		20	Digital supply voltage. This pin supplies power to the CMOS digital part of the device

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Philips Semiconductors	Product specification
1GHz low-voltage Fractional-N synthesizer	SA7025

BLOCK DIAGRAM

CLOCK		SERIAL INPUT + PROGRAM LATCHES								VDD
DATA
STROBE
VSS	FB			NM2					FB
		PR	NM1	NM3
	EM				FMOD		NF	3
	2	2	12	8
RFIN							FRACTIONAL		PRESCALER
	64/65/72								MODULUS
			MAIN DIVIDERS			ACCUMULATOR
RFIN	PRESCALER								CONTROL
										RF
							FRD	CN		RN
TEST			EM					8
									NORMAL
				MAIN			2		OUTPUT
				PHASE					CHARGE
				DETECTOR					PUMP
								CL		PHP
			SM					2
			2	MAIN					SPEED-UP
									OUTPUT
	NR			REFERENCE
				SELECT					CHARGE
VCCP									PUMP
	EM+EA
	12							CK
	REFERENCE DIVIDER			2	2	2		4
REFIN									INTEGRAL
									OUTPUT	PHI
									CHARGE
			SA						PUMP
			2	AUXILIARY						RA
				REFERENCE
				SELECT
									AUXILIARY
			EA						OUTPUT
				AUXILIARY			2		CHARGE	PHA
									PUMP
	PA	NA		PHASE
	EA			DETECTOR
		12								LOCK
AUXIN	1/4	AUXILIARY DIVIDER
	PRESCALER
					VDDA				VSSA
										SR00601

Figure 2. Block Diagram

1996 Aug 6

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Philips Semiconductors

Product specification

1GHz low-voltage Fractional-N synthesizer

SA7025

DC ELECTRICAL CHARACTERISTICS

VDD = VDDA = VCCP = 3V; TA = 25°C, unless otherwise specified.

SYMBOL

PARAMETER

TEST CONDITIONS

LIMITS

UNITS

MIN

TYP

MAX

VSUPPLY

Recommended operating conditions

VCCP = VDD, VDDA ≥ VDD

2.7

5.5

V

ISTANDBY

Total standby supply currents

EM = EA = 0, IRN = IRF = IRA = 0

50

500

μA

Operational

supply currents: I = IDD + ICCP + IDDA; IRN = 25μA, IRA = 25μA, (see Note 5)

IAUX

Operational supply currents

EM = 0, EA = 1

3.5

mA

IMAIN

Operational supply currents

EM = 1, EA = 0

5.5

mA

ITOTAL

Operational supply currents

EM = EA = 1

7.5

mA

Digital inputs CLK, DATA, STROBE

VIH

High level input voltage range

0.7xVDD

VDD

V

VIL

Low level input voltage range

0

0.3xVDD

V

Digital outputs LOCK

VOL

Output voltage LOW

IO = 2mA

0.4

V

VOH

Output voltage HIGH

IO = ±2mA

VDD±0.4

V

Charge pumps: VDDA = 3V / IRX = 25μA or VDDA = 5V / IRX = 62.5μA, VPHX in range, unless otherwise specified. (See Note 16)

|IRX|

Setting current range for any setting re-

2.7V < VDDA < 5.5V

25

μA

sistor

4.5V < VDDA < 5.5V

62.5

VPHOUT

Output voltage range

0.7

VDDA±0.8

V

Charge pump PHA

I

= ±62.5μA; V

PHA

= V

DDA

/213

400

500

600

|IPHA|

Output current PHA

RA

μA

IRA = ±25μA; VPHA = VDDA/2

160

200

240

IPHP_A

Relative output current variation PHA

I

RA

= ±62.5μA2, 13

2

6

%

| IPHP_A|

IPHA_M

Output current matching PHA pump

VDDA = 3V, IRA = 25μA

±50

μA

VDDA = 5V, IRA = 62.5μA

±65

Charge pump

PHP, normal mode1, 4, 6 VRF = VDDA

I

= ±62.5μA; V

PHP

= V

DDA

/213

440

550

660

|IPHP_N|

Output current PHP

RN

μA

IRN = ±25μA; VPHP = VDDA/2

175

220

265

IPHP_N

Relative output current variation PHP

I

= ±62.5μA2, 13

2

6

%

IPHP_N

RN

IPHP_N_M

Output current matching PHP

VDDA = 3V, IRA = 25μA

±50

μA

normal mode

VDDA = 5V, IRA = 62.5

μ

A

±

65

Charge pump

PHP, speed-up mode 1, 4, 7

VRF = VDDA

I

= ±62.5μA; V

PHP

= V

DDA

/213

2.20

2.75

3.30

|IPHP_S|

Output current PHP

RN

mA

IRN = ±25μA; VPHP = VDDA/2

0.85

1.1

1.35

IPHP_S

Relative output current variation PHP

I

= ±62.5μA2, 13

2

6

%

IPHP_S

RN

IPHP_S_M

Output current matching PHP

VDDA = 3V, IRA = 25μA

±250

μA

speed-up mode

VDDA = 5V, IRA = 62.5

μ

A

±

300

Charge pump

PHI, speed-up mode 1, 4, 8

VRF = VDDA

I

= ±62.5μA; V

PHI

= V

DDA

/213

4.4

5.5

6.6

|IPHI|

Output current PHI

RN

mA

IRN = ±25μA; VPHI = VDDA/2

1.75

2.2

2.65

IPHI

Relative output current variation PHI

I

= ±62.5μA2, 13

2

8

%

IPHI

RN

IPHI_M

Output current matching PHI pump

VDDA = 3V, IRA = 25μA

±500

μA

VDDA = 5V, IRA = 62.5μA

±600

Fractional

compensation PHP, normal mode 1, 9 VRN

= VDDA, VPHP = VDDA/2

Fractional compensation output current

I

= ±62.5μA;F

= 1 to 713

±625

±400

±250

IPHP_F_N

RF

RD

nA

PHP vs FRD3

I = ±25μA;F

= 1 to 7

±250

±180

±100

RF

RD

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Philips Semiconductors	Product specification
1GHz low-voltage Fractional-N synthesizer	SA7025

DC ELECTRICAL CHARACTERISTICS (Continued)

SYMBOL

PARAMETER

TEST CONDITIONS

LIMITS

UNITS

MIN

TYP

MAX

Fractional

compensation PHP, speed up mode 1, 10

VPHP = VDDA, VRN = VDDA

Fractional compensation output current

I

RF

= ±62.5μA;F

= 1 to 713

±3.35

±2.0

±1.1

IPHP_F_S

RD

μA

PHP vs FRD3

I

= ±25μA;F

RD

= 1 to 7

±1.35

±1.0

±0.5

RF

Pump leakage

±20

20

nA

Fractional

compensation PHI, speed up mode 1, 11 VPHP = VDDA/2, VRN = VDDA

Fractional compensation output current

I

RF

= ±62.5μA;F

= 1 to 713

±5.4

±4.0

±2.6

IPHI_F

RD

μA

PHI vs FRD3

I

= ±25μA;F

RD

= 1 to 7

±2.15

±1.6

±1.05

RF

Charge pump leakage currents, charge pump not active

IPHP_L

Output leakage current PHP; normal

VPHP = 0.7 to VDDA ± 0.8

0.1

10

nA

mode1

IPHI_L

Output leakage current PHI; normal

VPHI = 0.7 to VDDA ± 0.8

0.1

10

nA

mode1

IPHA_L

Output leakage current PHA

VPHA = 0.7 to VDDA ± 0.8

0.1

10

nA

AC ELECTRICAL CHARACTERISTICS

VDD = VDDA = VCCP = 3V; TA = 25°C; fRF_IN = 1GHz, input level = ±20dBm; unless otherwise specified. Test Circuit, Figure 4. The parameters listed below are tested using automatic test equipment to assure consistent electrical characteristics. The limits do not represent the ultimate performance limits of the device. Use of an optimized RF layout will improve many of the listed parameters.

SYMBOL	PARAMETER				TEST CONDITIONS		LIMITS		UNITS
						MIN	TYP	MAX
Main divider
fRF_IN	Input signal frequency				Direct coupled input14			1.04	GHz
					1000pF input coupling			1.04
VRF_IN	Input sensitivity				1040MHz	±20		0	dBm
Reference divider (VDD = VDDA = 3V or VDD = 3V / VDDA = 5V)
fREF_IN	Input signal frequency				2.7 < VDD and VDDA < 5.5V			25	MHz
					2.7 < VDD and VDDA < 4.5V			30
VREF_IN	Input signal range, AC coupled				2.7 < VDD and VDDA < 5.5V	500			mVP-P
					2.7 < VDD and VDDA < 4.5V	300
Z	Reference divider input impedance15						100		kΩ
REF_IN							3		pF
Auxiliary divider
	Input signal frequency					0		50
fAUX_IN	PA = ª0º, prescaler enabled				4.5V ≤ VDDA ≤ 5.5V	0		150	MHz
	Input signal frequency					0		30
	PA = ª1º, prescaler disabled				4.5V ≤ VDDA ≤ 5.5V	0		40
VAUX_IN	Input signal range, AC coupled					200			mVP-P
ZAUX_IN	Auxiliary divider input impedance						100		kΩ
							3		pF
Serial interface15
fCLOCK	Clock frequency							10	MHz
tSU	Set-up time: DATA to CLOCK,					30			ns
	CLOCK to STROBE
tH	Hold time; CLOCK to DATA					30			ns
tW	Pulse width; CLOCK					30			ns
	Pulse width; STROBE				B, C, D, E words	30
In-Loop Performance17 V		= 5V, V	DD	= 2.7V
	DDA
RMM	Main loop residual FM				FVCO = 1030MHz		300	600	Hz

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Philips Semiconductors	Product specification
1GHz low-voltage Fractional-N synthesizer	SA7025

AC ELECTRICAL CHARACTERISTICS (continued)

SYMBOL

PARAMETER

TEST CONDITIONS

LIMITS

UNITS

MIN

TYP

MAX

A word, PR = `01'

1

(NM2 65) t

W

tSW

Pulse width; STROBE

fVCO

ns

A word, PR = `10'

1

[(NM2 65) (NM3 1) 72] tW

fVCO

NOTES:

1.When a serial input ªAº word is programmed, the main charge pumps on PHP and PHI are in the ªspeed up modeº as long as STROBE= H.

When this is not the case, the main charge pumps are in the ªnormal modeº.

2.The relative output current variation is defined thus:

	IOUT	2	(I2	I1)	; with V	1	= 0.7V, V = V	DDA	± 0.8V (see Figure 3).
	IOUT		|(I2	I1)|			2

3.FRD is the value of the 3 bit fractional accumulator.

4.Monotonicity is guaranteed with CN = 0 to 255.

5.Power supply current measured with VDD = VCCP = 3V, VDDA = 5V, fRF IN = 915.99MHz, XTAL at 21.36MHz, AUX at 85.92MHz (PA = `0'),

Main comp frequency = 240kHz, Auxiliary comp frequency = 120kHz, CN = 160, CL = 0, CK = 0. Internal registers NM1 = 52, NM2 = 0,

NM3 = 4, PR = `10', SM = `00', SA = `01', NA = 179, NF = 5, FMOD = 8, NR = 89, PA = 0, IRN = IRA = IRF = 25μA, lock condition, normal mode. Operational supply current = IDDA + IDD + ICCP.

6.Specification condition: CN = 255

7.Specification conditions:

1)CN = 255; CL = 1, or

2)CN = 75; CL = 3

8.Typical output current | IPHI | = ±IRN x CN x 2(CL+1) x CK/32:

1)CN = 160; CL = 3; CK = 1, or

2)CN = 160; CL = 2; CK = 2, or

3)CN = 160; CL = 1; CK = 4, or

4)CN = 160; CL = 0; CK = 8

9.Any RFD, CL = 1 for speed-up pump. The integral pump is intended for switching only and the fractional compensation is not guaranteed.

10.Specification conditions: FRD = 1 to 7; CL = 1.

11.Specification conditions:

1)FRD = 1 to 7; CL = 1; CK = 2, or

2)FRD = 1 to 7; CL = 2; CK = 1.

12.The matching is defined by the sum of the P and the N pump for a given output voltage.

13.Limited analog supply voltage range 4.5 to 5.5V.

14.For fIN < 50MHz, low frequency operation requires DC-coupling and a minimum input slew rate of 32V/μs.

15.Guaranteed by design.

16.Close in noise for the charge pumps is tested on a sample basis in a typical application in order to eliminate parts outside the normal distribution.

17.FXTAL = 14.4MHz, VXTAL = 500mVP-P, comparison frequency = 200kHz, Loop bandwidth = 5kHz, Audio filter = 300Hz to 15kHz.

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