Philips psmn009-100w Datasheet

Philips Semiconductors Product specification

N-channel TrenchMOS transistor PSMN009-100W

FEATURES SYMBOL QUICK REFERENCE DATA

• ’Trench’ technology

• Very low on-state resistance V

d

= 100 V

DSS

• Fast switching

• Low thermal resistance I

g

s

R

DS(ON)

D

= 100 A

≤ 9 mΩ

GENERAL DESCRIPTION PINNING SOT429 (TO247)

SiliconMAXproductsusethelatest PIN DESCRIPTION

Philips Trench technology to
achieve the lowest possible 1 gate
on-state resistance in each
package at each voltage rating. 2 drain

Applications:- 3 source

• d.c. to d.c. converters

2

• switched mode power supplies tab drain

1

The PSMN009-100Wis suppliedin
the SOT429 (TO247) conventional
leaded package.

LIMITING VALUES

Limiting values in accordance with the Absolute Maximum System (IEC 134)

3

SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT

V

DSS

V

DGR

V

GS

I

D

Drain-source voltage Tj = 25 ˚C to 175˚C - 100 V
Drain-gate voltage Tj = 25 ˚C to 175˚C; RGS = 20 kΩ - 100 V
Gate-source voltage - ± 20 V
Continuous drain current Tmb = 25 ˚C - 100

1

Tmb = 100 ˚C - 79 A

I

DM

P

D

Tj, T

Pulsed drain current Tmb = 25 ˚C - 300 A
Total power dissipation Tmb = 25 ˚C - 300 W
Operating junction and - 55 175 ˚C

stg

storage temperature

1 Maximum continuous current limited by package.

A

October 1999 1 Rev 1.100

Philips Semiconductors Product specification

N-channel TrenchMOS transistor PSMN009-100W

AVALANCHE ENERGY LIMITING VALUES

Limiting values in accordance with the Absolute Maximum System (IEC 134)

SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT

E

AS

I

AS

THERMAL RESISTANCES

SYMBOL PARAMETER CONDITIONS TYP. MAX. UNIT

R

th j-mb

R

th j-a

Non-repetitive avalanche Unclamped inductive load, IAS = 100 A; - 650 mJ
energy tp = 100 µs; Tj prior to avalanche = 25˚C;

VDD ≤ 50 V; RGS = 50 Ω; VGS = 5 V; refer to

fig:15
Non-repetitive avalanche - 100 A
current

Thermal resistance junction - 0.5 K/W
to mounting base
Thermal resistance junction in free air 45 - K/W
to ambient

ELECTRICAL CHARACTERISTICS

Tj= 25˚C unless otherwise specified

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

V

(BR)DSS

V

GS(TO)

R

DS(ON)

I

GSS

I

DSS

Q

g(tot)

Q

gs

Q

gd

t

d on

t

r

t

d off

t

f

L

d

L

d

L

s

C

iss

C

oss

C

rss

Drain-source breakdown VGS = 0 V; ID = 0.25 mA; 100 - - V
voltage Tj = -55˚C 89 - - V
Gate threshold voltage VDS = VGS; ID = 1 mA 2.0 3.0 4.0 V

Tj = 175˚C 1.0 - - V

Tj = -55˚C - - 6 V
Drain-source on-state VGS = 10 V; ID = 25 A - 6.7 9 mΩ
resistance Tj = 175˚C - 15 25 mΩ
Gate source leakage current VGS = ±10 V; VDS = 0 V - 2 100 nA
Zero gate voltage drain VDS = 100 V; VGS = 0 V; - 0.05 10 µA
current Tj = 175˚C - - 500 µA

Total gate charge ID = 100 A; V

= 80 V; VGS = 10 V - 214 - nC

DD

Gate-source charge - 45 - nC
Gate-drain (Miller) charge - 91 - nC

Turn-on delay time VDD = 50 V; RD = 2 Ω; - 40 - ns
Turn-on rise time VGS = 10 V; RG = 5.6 Ω - 100 - ns
Turn-off delay time Resistive load - 260 - ns
Turn-off fall time - 100 - ns

Internal drain inductance Measured from tab to centre of die - 3.5 - nH
Internal drain inductance Measured from drain lead to centre of die - 4.5 - nH
Internal source inductance Measured from source lead to source - 7.5 - nH

bond pad

Input capacitance VGS = 0 V; VDS = 25 V; f = 1 MHz - 9000 - pF
Output capacitance - 1000 - pF
Feedback capacitance - 650 - pF

October 1999 2 Rev 1.100

Philips Semiconductors Product specification

N-channel TrenchMOS transistor PSMN009-100W

REVERSE DIODE LIMITING VALUES AND CHARACTERISTICS

Tj = 25˚C unless otherwise specified

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

I

S

I

SM

V

SD

t

rr

Q

rr

Continuous source current - - 100 A
(body diode)
Pulsed source current (body - - 300 A
diode)
Diode forward voltage IF = 25 A; VGS = 0 V - 0.82 1.2 V

IF = 75 A; VGS = 0 V - 0.95 - V

Reverse recovery time IF = 20 A; -dIF/dt = 100 A/µs; - 100 - ns
Reverse recovery charge VGS = 0 V; VR = 30 V - 0.5 - µC

October 1999 3 Rev 1.100

Philips Semiconductors Product specification

N-channel TrenchMOS transistor PSMN009-100W

Normalised Power Derating, PD (%)

100

90
80
70
60
50
40
30
20
10

0

0 25 50 75 100 125 150 175

Mounting Base temperature, Tmb (C)

Fig.1. Normalised power dissipation.

PD% = 100⋅PD/P

Normalised Current Derating, ID (%)

100

90
80
70
60
50
40
30
20
10

0

0 25 50 75 100 125 150 175

Mounting Base temperature, Tmb (C)

D 25 ˚C

= f(Tmb)

Fig.2. Normalised continuous drain current.

ID% = 100⋅ID/I

D 25 ˚C

= f(Tmb)

Transient thermal impedance, Zth j-mb (K/W)

1

D = 0.5

0.2

0.1

0.1

0.05

0.02

0.01

single pulse

0.001
1E-06 1E-05 1E-04 1E-03 1E-02 1E-01 1E+00

Pulse width, tp (s)

P

D

D = tp/T

tp

T

Fig.4. Transient thermal impedance.

Z

= f(t); parameter D = tp/T

th j-mb

Drain Current, ID (A)

100

90
80
70
60
50
40
30
20
10

0

8 V

0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2

Drain-Source Voltage, VDS (V)

6 V

Tj = 25 CVGS = 10 V

4 V

5 V

4.8 V

4.6 V

4.4 V

4.2 V

Fig.5. Typical output characteristics, Tj = 25 ˚C

ID = f(VDS); parameter V

GS

.

Peak Pulsed Drain Current, IDM (A)

1000

RDS(on) = VDS/ ID

tp = 10 us

100

10

1

1 10 100 1000

D.C.

Drain-Source Voltage, VDS (V)

100 us

1 ms

10 ms
100 ms

Fig.3. Safe operating area. Tmb = 25 ˚C

ID & IDM = f(VDS); IDM single pulse; parameter t

p

Drain-Source On Resistance, RDS(on) (Ohms)

0.05

0.045

0.035

0.025

0.015

0.005

4.4 V

4.2 V

0.04

0.03

0.02

0.01

0

0 102030405060708090100

4.8 V

4.6 V

Drain Current, ID (A)

5 V

8 V

Tj = 25 C

6V

VGS = 10V

Fig.6. Typical on-state resistance, Tj = 25 ˚C

R

= f(VGS)

DS(ON)

.

October 1999 4 Rev 1.100

Philips Semiconductors Product specification

N-channel TrenchMOS transistor PSMN009-100W

Drain current, ID (A)

100

VDS > ID X RDS(ON)

90
80
70
60
50
40
30
20
10

0

0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 6

Gate-source voltage, VGS (V)

175 C

Tj = 25 C

Fig.7. Typical transfer characteristics.

ID = f(VGS); parameter T

Transconductance, gfs (S)

130

VDS > ID X RDS(ON)

120
110
100

90
80
70
60
50
40
30
20
10

0

0 102030405060708090100

Tj = 25 C

Drain current, ID (A)

j

175 C

Fig.8. Typical transconductance, Tj = 25 ˚C

gfs = f(ID)

Threshold Voltage, VGS(TO) (V)

4.5
4

3.5
3

2.5
2

1.5
1

0.5
0

-60 -40 -20 0 20 40 60 80 100 120 140 160 180
Junction Temperature, Tj (C)

maximum

typical

minimum

Fig.10. Gate threshold voltage.

V

= f(Tj); conditions: ID = 1 mA; VDS = V

GS(TO)

Drain current, ID (A)

1.0E-01

1.0E-02

1.0E-03

1.0E-04

1.0E-05

1.0E-06
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5

.

Fig.11. Sub-threshold drain current.

minimum

typical

Gate-source voltage, VGS (V)

ID = f(V

; Tj = 25 ˚C

GS)

maximum

GS

Normalised On-state Resistance

2.9

2.7

2.5

2.3

2.1

1.9

1.7

1.5

1.3

1.1

0.9

0.7

0.5

-60 -40 -20 0 20 40 60 80 100 120 140 160 180
Junction temperature, Tj (C)

Fig.9. Normalised drain-source on-state resistance.

R

DS(ON)/RDS(ON)25 ˚C

= f(Tj)

Capacitances, Ciss, Coss, Crss (pF)

100000

10000

1000

100

0.1 1 10 100

Fig.12. Typical capacitances, C

Drain-Source Voltage, VDS (V)

iss

, C

C = f(VDS); conditions: VGS = 0 V; f = 1 MHz

oss

Ciss

Coss

Crss

, C

rss

.

October 1999 5 Rev 1.100

Philips Semiconductors Product specification

N-channel TrenchMOS transistor PSMN009-100W

Gate-source voltage, V

15

ID = 100A

14
13

Tj = 25 C

12
11
10

9
8
7
6
5
4
3
2
1
0

0 20 40 60 80 100 120 140 160 180 200 220 240

(V)

GS

VDD = 20 V

Gate charge, Q

G

VDD = 80 V

(nC)

Fig.13. Typical turn-on gate-charge characteristics

V

= f(QG)

GS

Source-Drain Diode Current, IF (A)

100

VGS = 0 V

90
80
70
60
50
40
30
20
10

0

0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 1.1 1.2 1.3 1.4 1.5

175 C

Tj = 25 C

Source-Drain Voltage, VSDS (V)

Maximum Avalanche Current, I

1000

100

10

1

0.001 0.01 0.1 1 10

Tj prior to avalanche = 150 C

Avalanche time, t

(A)

AS

25 C

(ms)

AV

Fig.15. Maximum permissible non-repetitive

avalanche current (IAS) versus avalanche time (tAV);

unclamped inductive load

Fig.14. Typical reverse diode current.

IF = f(V

); conditions: V

SDS

= 0 V; parameter T

GS

j

October 1999 6 Rev 1.100

Philips Semiconductors Product specification

N-channel TrenchMOS transistor PSMN009-100W

MECHANICAL DATA

Plastic single-ended through-hole package; heatsink mounted; 1 mounting hole; 3-lead TO-247 SOT429

α

E
P

R

(1)

L

1

b

2

123

b

DIMENSIONS (mm are the original dimensions)

A

A

UNIT

mm

Note

1. Tinning of terminals are uncontrolled within zone L1.

1

1.9

5.3

1.7

4.7

OUTLINE

VERSION

SOT429 TO-247

b

1

1.2

2.2

0.9

1.8

IEC JEDEC EIAJ

b

2

3.2

2.8

c

0.9

0.621201615

b
1

ee

DbE

REFERENCES

q

S

D

Y

L

w

M

0 10 20 mm

scale

L

16154.0

(1)

1

3.6

e

5.45

A

A

1

Q

3.7

2.6

3.3

5.3

2.4

c

7.5

3.5

7.1

3.3

EUROPEAN

PROJECTION

β

wSRqQPLY

15.7

0.4

15.3

ISSUE DATE

α

6°
4°

98-04-07
99-08-04

17°
13°

β

Fig.16. SOT429; pin 2 connected to mounting base

Notes

1. Observe the general handling precautions for electrostatic-discharge sensitive devices (ESDs) to prevent
damage to MOS gate oxide.

2. Refer to mounting instructions for SOT429 envelope.

3. Epoxy meets UL94 V0 at 1/8".

October 1999 7 Rev 1.100

Philips Semiconductors Product specification

N-channel TrenchMOS transistor PSMN009-100W

DEFINITIONS

Data sheet status

Objective specification This data sheet contains target or goal specifications for product development.
Preliminary specification This data sheet contains preliminary data; supplementary data may be published later.
Product specification This data sheet contains final product specifications.

Limiting values

Limiting values are given in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one
or more of the limiting values may cause permanent damage to the device. These are stress ratings only and
operation of the device at these or at any other conditions above those given in the Characteristics sections of
this specification is not implied. Exposure to limiting values for extended periods may affect device reliability.

Application information

Where application information is given, it is advisory and does not form part of the specification.

 Philips Electronics N.V. 1999

All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the
copyright owner.

The information presented in this document does not form part of any quotation or contract, it is believed to be
accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any
consequence of its use. Publication thereof does not convey nor imply any license under patent or other
industrial or intellectual property rights.

LIFE SUPPORT APPLICATIONS

These products are not designed for use in life support appliances, devices or systems where malfunction of these
products can be reasonably expected to result in personal injury. Philips customers using or selling these products
for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting
from such improper use or sale.

October 1999 8 Rev 1.100