Philips PHX3055L Datasheet
Philips Semiconductors Preliminary specification
PowerMOS transistor PHX3055L
Logic level FET
GENERAL DESCRIPTION QUICK REFERENCE DATA
N-channel enhancement mode logic SYMBOL PARAMETER MAX. UNIT
level field-effectpowertransistorina
plastic full-pack envelope. The V
device features high avalanche I
energy capability, stable blocking P
voltage, fast switching and high R
thermalcyclingperformancewithlow
DS
D
tot
DS(ON)
thermal resistance. Intended for use
in Switched Mode Power Supplies
(SMPS), motor control circuits and
general purpose switching
applications.
PINNING - SOT186A PIN CONFIGURATION SYMBOL
Drain-source voltage 60 V
Drain current (DC) 9.4 A
Total power dissipation 28 W
Drain-source on-state resistance 0.18 Ω
PIN DESCRIPTION
case
d
1 gate
2 drain
3 source
case isolated
123
g
s
LIMITING VALUES
Limiting values in accordance with the Absolute Maximum System (IEC 134)
SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT
I
D
I
DM
P
D
∆PD/∆ThsLinear derating factor Ths > 25 ˚C - 0.22 W/K
V
GS
V
GSM
E
AS
I
AS
Tj, T
Continuous drain current Ths = 25 ˚C; VGS = 10 V - 9.4 A
Ths = 100 ˚C; VGS = 10 V - 5.9 A
Pulsed drain current Ths = 25 ˚C - 26 A
Total dissipation Ths = 25 ˚C - 28 W
Gate-source voltage - ± 15 V
Non-repetitive gate source tp≤50µs-± 20 V
voltage
Single pulse avalanche VDD ≤ 50 V; starting Tj = 25˚C; RGS = 50 Ω; - 25 mJ
energy VGS = 10 V
Peak avalanche current VDD ≤ 50 V; starting Tj = 25˚C; RGS = 50 Ω;- 6 A
VGS = 10 V
Operating junction and - 55 150 ˚C
stg
storage temperature range
ISOLATION LIMITING VALUE & CHARACTERISTIC
Ths = 25 ˚C unless otherwise specified
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
V
isol
C
isol
October 1997 1 Rev 1.000
R.M.S. isolation voltage from all f = 50-60 Hz; sinusoidal - 2500 V
three terminals to external waveform;
heatsink R.H. ≤ 65% ; clean and dustfree
Capacitance from T2 to external f = 1 MHz - 10 - pF
heatsink
Philips Semiconductors Preliminary specification
PowerMOS transistor PHX3055L
Logic level FET
THERMAL RESISTANCES
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
R
th j-hs
R
th j-a
ELECTRICAL CHARACTERISTICS
Tj = 25 ˚C unless otherwise specified
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
V
(BR)DSS
∆V
(BR)DSS
∆T
j
R
DS(ON)
V
GS(TO)
g
fs
I
DSS
I
GSS
Q
g(tot)
Q
gs
Q
gd
t
d(on)
t
r
t
d(off)
t
f
L
d
L
s
C
iss
C
oss
C
rss
Thermal resistance junction to - - 4.5 K/W
heat sink.
Thermal resistance junction to - 55 - K/W
ambient
Drain-source breakdown VGS = 0 V; ID = 0.25 mA 60 - - V
voltage
/ Drain-source breakdown VDS = VGS; ID = 0.25 mA - 0.06 - V/K
voltage temperature coefficient
Drain-source on resistance VGS = 10 V; ID = 6 A - 0.13 0.18 Ω
Gate threshold voltage VDS = VGS; ID = 0.25 mA 1.0 1.5 2.0 V
Forward transconductance VDS = 50 V; ID = 6 A 3.5 5.5 - S
Drain-source leakage current VDS = 60 V; VGS = 0 V - 0.1 25 µA
VDS = 48 V; VGS = 0 V; Tj = 150 ˚C - 1 250 µA
Gate-source leakage current VGS = ±30 V; VDS = 0 V - 10 100 nA
Total gate charge ID = 10 A; V
Gate-source charge - 1.9 3 nC
= 48 V; VGS = 10 V - 7.5 10 nC
DD
Gate-drain (Miller) charge - 5.5 7 nC
Turn-on delay time VDD = 30 V; ID = 10 A; - 12 - ns
Turn-on rise time RG = 24 Ω; RD = 2.7 Ω - 105 - ns
Turn-off delay time - 26 - ns
Turn-off fall time - 35 - ns
Internal drain inductance Measured from drain lead 6 mm - 4.5 - nH
from package to centre of die
Internal source inductance Measured from source lead 6 mm - 7.5 - nH
from package to source bond pad
Input capacitance VGS = 0 V; VDS = 25 V; f = 1 MHz - 290 - pF
Output capacitance - 103 - pF
Feedback capacitance - 40 - pF
SOURCE-DRAIN DIODE RATINGS AND CHARACTERISTICS
Ths = 25 ˚C unless otherwise specified
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
I
S
I
SM
V
SD
t
rr
Q
rr
October 1997 2 Rev 1.000
Continuous source current - - 9.4 A
(body diode)
Pulsed source current (body - - 48 A
diode)
Diode forward voltage IS = 10 A; VGS = 0 V - - 1.5 V
Reverse recovery time IS = 10 A; VGS = 0 V; - 40 - ns
dI/dt = 100 A/µs
Reverse recovery charge - 0.1 - µC
Philips Semiconductors Preliminary specification
PowerMOS transistor PHX3055L
Logic level FET
PD%
120
110
100
90
80
70
60
50
40
30
20
10
0
0 20 40 60 80 100 120 140
Normalised Power Derating
with heatsink compound
Ths / C
Fig.1. Normalised power dissipation.
PD% = 100⋅PD/P
ID%
120
110
100
90
80
70
60
50
40
30
20
10
0
0 20 40 60 80 100 120 140
with heatsink compound
Ths / C
= f(Ths)
D 25 ˚C
Normalised Current Derating
Fig.2. Normalised continuous drain current.
ID% = 100⋅ID/I
= f(Ths); conditions: VGS ≥ 10 V
D 25 ˚C
Transient Thermal Impedance (K/W)
0.5
0.2
0.1
p
t
P
0
1us 10us 100us 1ms 10ms 0.1s 1s 10s
D
T
tp, pulse width (s)
D =
PHX3055E
p
t
T
t
0.1
0.01
0.001
10
Zth(j-hs)
1
0.05
0.02
Fig.4. Transient thermal impedance.
Z
= f(t); parameter D = tp/T
th j-hs
ID, Drain current (Amps)
15
10 V
10
5
0
0 5 10 15 20 25 30
VDS, Drain-Source voltage (Volts)
Tj = 25 C
PHP3055E
VGS = 4.5 V
Fig.5. Typical output characteristics
ID = f(VDS); parameter V
GS
7 V
6.5 V
6 V
5.5 V
5 V
.
ID, Drain current (Amps)
100
tp = 10 us
RDS(ON) = VDS/ID
10
1
0.1
1 10 100 1000
DC
VDS, Drain-source voltage (Volts)
100 us
1 ms
10 ms
100 ms
Fig.3. Safe operating area. Ths = 25 ˚C
ID & IDM = f(VDS); IDM single pulse; parameter t
p
RDS(on), Drain-Source on resistance (Ohms)
0.4
0.3
0.2
0.1
Tj = 25 C
0
0 5 10 15 20
6 V
5.5 V
ID, Drain current (Amps)
6.5 V
PHP3055E
7 V
VGS = 15 V
Fig.6. Typical on-state resistance
R
= f(ID); parameter V
DS(ON)
GS
10 V
.
October 1997 3 Rev 1.000
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