Philips php45n03lt Datasheet

Philips Semiconductors Product specification

TrenchMOS transistor PHP45N03LT
Logic level FET

FEATURES SYMBOL QUICK REFERENCE DATA

• ’Trench’ technology V

d

= 30 V

DSS

• Very low on-state resistance

• Fast switching I

= 45 A

D

• Stable off-state characteristics

• High thermal cycling performance R

g

≤ 24 mΩ (VGS = 5 V)

DS(ON)

• Low thermal resistance

s

R

≤ 21 mΩ (VGS = 10 V)

DS(ON)

GENERAL DESCRIPTION PINNING SOT78 (TO220AB)

N-channel enhancement mode PIN DESCRIPTION
logic level field-effect power
transistor in a plastic envelope 1 gate
using ’trench’ technology. The
device has very low on-state 2 drain
resistance. It is intended for use in
dc to dc converters and general 3 source
purpose switching applications.

tab drain
ThePHP45N03LTissuppliedin the
SOT78 (TO220AB) conventional
leaded package.

tab

123

LIMITING VALUES

Limiting values in accordance with the Absolute Maximum System (IEC 134)

SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT

V

DS

V

DGR

Drain-source voltage - - 30 V

Drain-gate voltage RGS = 20 kΩ -30V
±VGSGate-source voltage - - 15 V
I

D

I

D

I

DM

P

tot

T

, T

stg

j

Drain current (DC) Tmb = 25 ˚C - 45 A

Drain current (DC) Tmb = 100 ˚C - 36 A

Drain current (pulse peak value) Tmb = 25 ˚C - 180 A

Total power dissipation Tmb = 25 ˚C - 86 W

Storage & operating temperature - - 55 175 ˚C

THERMAL RESISTANCES

SYMBOL PARAMETER CONDITIONS TYP. MAX. UNIT

R
R

th j-mb

th j-a

Thermal resistance junction to - - 1.75 K/W

mounting base

Thermal resistance junction to in free air 60 - K/W

ambient

November 1997 1 Rev 1.200

Philips Semiconductors Product specification

TrenchMOS transistor PHP45N03LT

Logic level FET

STATIC CHARACTERISTICS

Tj= 25˚C unless otherwise specified

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

V

(BR)DSS

V

GS(TO)

I

DSS

I

GSS

R

DS(ON)

DYNAMIC CHARACTERISTICS

Tj = 25˚C unless otherwise specified

Drain-source breakdown VGS = 0 V; ID = 0.25 mA; 30 - - V
voltage Tj = -55˚C 27 - - V
Gate threshold voltage VDS = VGS; ID = 1 mA 1 1.5 2 V

Tj = 175˚C 0.5 - - V

Tj = -55˚C - - 2.3

Zero gate voltage drain current VDS = 30 V; VGS = 0 V; - 0.05 10 µA

Tj = 175˚C - - 500 µA
Gate source leakage current VGS = ±5 V; VDS = 0 V - 10 100 nA
Drain-source on-state VGS = 5 V; ID = 25 A - 20 24 mΩ
resistance VGS = 10 V; ID = 25 A - 16 21 mΩ

VGS = 5 V; ID = 25 A; Tj = 175˚C - - 45 mΩ

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

g
Q

Q
Q

C
C
C

t
t
t
t

L

fs

g(tot)
gs
gd

iss
oss
rss

d on
r
d off
f

d

Forward transconductance VDS = 25 V; ID = 25 A 8 16 - S
Total gate charge ID = 40 A; V

= 24 V; VGS = 5 V - 23 - nC

DD

Gate-source charge - 3 - nC
Gate-drain (Miller) charge - 12 - nC

Input capacitance VGS = 0 V; VDS = 25 V; f = 1 MHz - 2000 2500 pF
Output capacitance - 380 450 pF
Feedback capacitance - 250 300 pF

Turn-on delay time VDD = 15 V; ID = 25 A; - 30 45 ns
Turn-on rise time VGS = 5 V; RG = 5 Ω - 80 130 ns
Turn-off delay time Resistive load - 95 135 ns
Turn-off fall time - 40 55 ns

Internal drain inductance Measured from contact screw on - 3.5 - nH

tab to centre of die

L

d

Internal drain inductance Measured from drain lead 6 mm - 4.5 - nH

from package to centre of die

L

s

Internal source inductance Measured from source lead 6 mm - 7.5 - nH

from package to source bond pad

REVERSE DIODE LIMITING VALUES AND CHARACTERISTICS

Tj = 25˚C unless otherwise specified

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

I

DR

I

DRM

V

t

rr

Q

SD

rr

Continuous reverse drain - - 45 A
current
Pulsed reverse drain current - - 180 A
Diode forward voltage IF = 25 A; VGS = 0 V - 0.95 1.2 V

IF = 40 A; VGS = 0 V - 1.0 -

Reverse recovery time IF = 40 A; -dIF/dt = 100 A/µs; - 52 - ns
Reverse recovery charge VGS = -10 V; VR = 25 V - 0.08 - µC

November 1997 2 Rev 1.200

Philips Semiconductors Product specification

TrenchMOS transistor PHP45N03LT

Logic level FET

AVALANCHE LIMITING VALUE

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

W

DSS

Drain-source non-repetitive ID = 25 A; VDD ≤ 25 V; - - 60 mJ
unclamped inductive turn-off VGS = 10 V; RGS = 50 Ω; Tmb = 25 ˚C
energy

November 1997 3 Rev 1.200

Philips Semiconductors Product specification

TrenchMOS transistor PHP45N03LT
Logic level FET

PD%

120
110
100

90
80
70
60
50
40
30
20
10

0

0 20 40 60 80 100 120 140 160 180

Normalised Power Derating

Tmb / C

Fig.1. Normalised power dissipation.

PD% = 100⋅PD/P

ID%

120
110
100

90
80
70
60
50
40
30
20
10

0

0 20 40 60 80 100 120 140 160 180

Tmb / C

= f(Tmb)

D 25 ˚C

Normalised Current Derating

Fig.2. Normalised continuous drain current.

ID% = 100⋅ID/I

= f(Tmb); conditions: VGS ≥ 5 V

D 25 ˚C

Zth j-mb / (K/W)

10

D =

1

0.5

0.2

0.1

0.1

0.05

0.02

0.01

0

1E-07 1E-05 1E-03 1E-01 1E+01

t / s

p

t

P

D

7528-30

p

t

D =

T

T

t

Fig.4. Transient thermal impedance.

Z

= f(t); parameter D = tp/T

th j-mb

ID / A

80

6

60

40

20

0

0246810

510

VGS / V =

VDS / V

Fig.5. Typical output characteristics, Tj = 25 ˚C

ID = f(VDS); parameter V

9528-30

4.5

4

3.5

3

2.5

.

GS

ID / A

1000

100

RDS(ON) = VDS / ID

10

1

1 10 100

DC

VDS / V

7528-30

tp = 10 us

100 us

1 ms
10 ms

Fig.3. Safe operating area. Tmb = 25 ˚C

ID & IDM = f(VDS); IDM single pulse; parameter t

RDS(ON) / mOhm

40

30

20

10

0

0 20406080

VGS / V =

ID / A

Fig.6. Typical on-state resistance, Tj = 25 ˚C

R

p

= f(ID); parameter V

DS(ON)

9528-30

4.54

5

6

10

.

GS

November 1997 4 Rev 1.200

Philips Semiconductors Product specification

TrenchMOS transistor PHP45N03LT
Logic level FET

ID / A

60

50

Tj / C = 25 175

40

30

20

10

0

0123456

VGS / V

9528-30

Fig.7. Typical transfer characteristics.

ID = f(VGS) ; conditions: VDS = 25 V; parameter T

25

20

15

10

gfs / S

Tj / C = 25

175

9528-30

j

VGS(TO) / V

2.5
max.

2

typ.

1.5

min.

1

0.5

0

-100 -50 0 50 100 150 200
Tj / C

BUK959-60

Fig.10. Gate threshold voltage.

V

= f(Tj); conditions: ID = 1 mA; VDS = V

GS(TO)

1E-01

1E-02

1E-03

1E-04

2% typ

Sub-Threshold Conduction

98%

GS

5

0

0 102030405060

Fig.8. Typical transconductance, Tj = 25 ˚C

ID / A

.

gfs = f(ID); conditions: VDS = 25 V

a

2

1.5

1

0.5

0

-100 0 100 200
Tj / C

30V TrenchMOS

15050-50

Fig.9. Normalised drain-source on-state resistance.

a = R

DS(ON)/RDS(ON)25 ˚C

= f(Tj); ID = 25 A; VGS = 5 V

1E-05

1E-05

0 0.5 1 1.5 2 2.5 3

Fig.11. Sub-threshold drain current.

ID = f(V

C / pF

10000

1000

100

0.1 1 10 100

Fig.12. Typical capacitances, C

; conditions: Tj = 25 ˚C; VDS = V

GS)

VDS / V

, C

iss

C = f(VDS); conditions: VGS = 0 V; f = 1 MHz

9528-30

, C

oss

GS

Ciss

Coss
Crss

rss

.

November 1997 5 Rev 1.200

Philips Semiconductors Product specification

TrenchMOS transistor PHP45N03LT
Logic level FET

VGS / V

5

4

3

2

1

0

0 5 10 15 20 25

VDS / V = 6 24

QG / nC

9528-30

Fig.13. Typical turn-on gate-charge characteristics.

V

= f(QG); conditions: ID = 40 A; parameter V

GS

IF / A

60

50

40

30

20

10

0

0 0.5 1 1.5 2

Tj / C = 175 25

VSDS / V

DS

9528-30

Fig.14. Typical reverse diode current.

IF = f(V

); conditions: V

SDS

= 0 V; parameter T

GS

j

WDSS%

120
110
100

90
80
70
60
50
40
30
20
10

0

20 40 60 80 100 120 140 160 180

Tmb / C

Fig.15. Normalised avalanche energy rating.

W

% = f(Tmb); conditions: ID = 25 A

DSS

+

L

VDS

VGS

0

RGS

T.U.T.

Fig.16. Avalanche energy test circuit.

W

= 0.5 ⋅ LI

DSS

2

D

⋅ BV

DSS

/(BV

DSS−VDD

-

R 01

shunt

)

VDD

-ID/100

VDD

+

RD

VDS

VGS

0

RG

T.U.T.

-

Fig.17. Switching test circuit.

November 1997 6 Rev 1.200

Philips Semiconductors Product specification

TrenchMOS transistor PHP45N03LT

Logic level FET

MECHANICAL DATA

Dimensions in mm
Net Mass: 2 g

10,3
max

1,3

3,7

4,5
max

3,0 max

not tinned

1,3

max

(2x)

123

2,54 2,54

2,8

3,0

13,5

min

0,9 max (3x)

5,9

min

15,8

max

0,6

2,4

Fig.18. SOT78 (TO220AB); pin 2 connected to mounting base.

Notes

1. Observe the general handling precautions for electrostatic-discharge sensitive devices (ESDs) to prevent
damage to MOS gate oxide.

2. Refer to mounting instructions for SOT78 (TO220) envelopes.

3. Epoxy meets UL94 V0 at 1/8".

November 1997 7 Rev 1.200

Philips Semiconductors Product specification

TrenchMOS transistor PHP45N03LT

Logic level FET

DEFINITIONS

Data sheet status

Objective specification This data sheet contains target or goal specifications for product development.
Preliminary specification This data sheet contains preliminary data; supplementary data may be published later.
Product specification This data sheet contains final product specifications.

Limiting values

Limiting values are given in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one
or more of the limiting values may cause permanent damage to the device. These are stress ratings only and
operation of the device at these or at any other conditions above those given in the Characteristics sections of
this specification is not implied. Exposure to limiting values for extended periods may affect device reliability.

Application information

Where application information is given, it is advisory and does not form part of the specification.

 Philips Electronics N.V. 1997

All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the
copyright owner.

The information presented in this document does not form part of any quotation or contract, it is believed to be
accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any
consequence of its use. Publication thereof does not convey nor imply any license under patent or other
industrial or intellectual property rights.

LIFE SUPPORT APPLICATIONS

These products are not designed for use in life support appliances, devices or systems where malfunction of these
products can be reasonably expected to result in personal injury. Philips customers using or selling these products
for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting
from such improper use or sale.

November 1997 8 Rev 1.200