Philips phkd13n03lt Datasheet

Page 1

1. Product profile

1.1 General description

Dual logic level N-channel enhancement mode Field-Effect Transistor (FET) in a plastic package using TrenchMOS technology. This product is designed and qualified for use in computing, communications, consumer and industrial applications only.

1.2 Features and benefits

PHKD13N03LT

Dual N-channel TrenchMOS logic level FET

Rev. 03 — 27 April 2010 Product data sheet

 Low conduction losses due to low

on-state resistance

 Simple gate drive required due to low

 Suitable for high frequency

applications due to fast switching characteristics

gate charge

1.3 Applications

 DC-to-DC convertors  Lithium-ion battery applications

 Notebook computers  Portable equipment

1.4 Quick reference data

Table 1. Quick reference data

Symbol Parameter Conditions Min Typ Max Unit

tot

Static characteristics

DSon

Dynamic characteristics

drain-source voltage Tj≥ 25 °C; Tj≤ 150°C --30V drain current Tsp=25°C; VGS=10V;

see Figure 1; see Figure 3

total power dissipation

drain-source on-state resistance

gate-drain charge VGS=5V; ID=5A;

Tsp=25°C; see Figure 2 --3.57W

VGS=10V; ID=8A; T

=25°C; see Figure 9;

see Figure 10

=15V; Tj=25°C;

see Figure 11

[1]

--10.4A

- 1720mΩ

-3.9-nC

[1] Single device conducting.

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NXP Semiconductors

2. Pinning information

PHKD13N03LT

Dual N-channel TrenchMOS logic level FET

Table 2. Pinning information

Pin Symbol Description Simplified outline Graphic symbol

1S1source1 2 G1 gate1

3S2source2 4 G2 gate2 5D2drain2 6D2drain2 7D1drain1

SOT96-1 (SO8)

G1S1

G2S2

mbk72

8D1drain

3. Ordering information

Table 3. Ordering information

Type number Package

PHKD13N03LT SO8 plastic small outline package; 8 leads; body width 3.9 mm SOT96-1

Name Description Version

4. Limiting values

Table 4. Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134).

Symbol Parameter Conditions Min Typ Max Unit

DGR

tot

stg

Source-drain diode

[1] Single device conducting.

drain-source voltage Tj≥ 25 °C; Tj≤ 150°C --30V drain-gate voltage Tj≥ 25 °C; Tj≤ 150 °C; RGS=20kΩ --30V gate-source voltage -20 - 20 V drain current Tsp= 100 °C; VGS=10V; see Figure 1

=25°C; VGS=10V; see Figure 1;

[1] [1]

--6.6A

- - 10.4 A

see Figure 3

peak drain current Tsp=25°C; tp≤ 10 µs; pulsed;

[1]

--42A

see Figure 3 total power dissipation Tsp=25°C; see Figure 2 --3.57W storage temperature -55 - 150 °C junction temperature -55 - 150 °C

source current Tsp=25°C peak source current Tsp=25°C; tp≤ 10 µs; pulsed

[1] [1]

--3.2A

--42A

Product data sheet Rev. 03 — 27 April 2010 2 of 13

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NXP Semiconductors

PHKD13N03LT

Dual N-channel TrenchMOS logic level FET

120

der

(%)

0 20015050 100

03aa25

Tsp (°C)

Fig 1. Normalized continuous drain current as a

function of solder point temperature

120

der

(%)

0 20015050 100

03aa17

Tsp (°C)

Fig 2. Normalized total power dissipation as a

function of solder point temperature

003aaa368

(A)

-1

Limit R

DSon

= V

/ I

tp = 10 μs

1 ms

1 10 10

10 ms

100 ms

VDS (V)

Fig 3. Safe operating area; continuous and peak drain currents as a function of drain -sou rce voltage

Product data sheet Rev. 03 — 27 April 2010 3 of 13

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NXP Semiconductors

5. Thermal characteristics

PHKD13N03LT

Dual N-channel TrenchMOS logic level FET

Table 5. Thermal characteristics

Symbol Parameter Conditions Min Typ Max Unit

th(j-sp)

thermal resistance from

see Figure 4 --35K/W

junction to solder point

th(j-a)

Z (K/W)

th(j-s p)

thermal resistance from junction to ambient

= 0.5

0.2

0.1

0.05

0.02

single pulse

-1

-4

-3

minimum footprint; mounted on a printed-circuit board

-2

-1

-70-K/W

003aaa415

1 10

δ =

(s)

Fig 4. Transient thermal impedance from junction to solder point as a function of pulse duration

Product data sheet Rev. 03 — 27 April 2010 4 of 13

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NXP Semiconductors

6. Characteristics

PHKD13N03LT

Dual N-channel TrenchMOS logic level FET

Table 6. Characteristics

Symbol Parameter Conditions Min Typ Max Unit

Static characteristics

(BR)DSS

GS(th)

drain-source breakdown voltage

gate-source threshold voltage

ID=250µA; VGS=0V; Tj= -55 °C 27 - - V

=250µA; VGS=0V; Tj=25°C 30--V

ID=250µA; VDS=VGS; Tj=-55°C;

--2.2V

see Figure 8

=250µA; VDS=VGS; Tj= 150 °C;

0.5--V

see Figure 8

=250µA; VDS=VGS; Tj=25°C;

11.52V

see Figure 8

DSS

GSS

DSon

drain leakage current VDS=24V; VGS=0V; Tj=25°C --1µA

=24V; VGS=0V; Tj= 100 °C - - 5 µA

gate leakage current VGS=20V; VDS=0V; Tj= 25 °C - - 100 nA

=-20V; VDS=0V; Tj= 25 °C - - 100 nA

drain-source on-state resistance

VGS=10V; ID=8A; Tj= 150 °C;

--34mΩ

see Figure 9; see Figure 10

=4.5V; ID=7A; Tj= 25 °C; see Figure 9 - 2126mΩ

=10V; ID=8A; Tj=25°C; see Figure 9;

- 1720mΩ

see Figure 10

Dynamic characteristi cs

Q Q Q C C C

G(tot) GS

GD iss oss rss

total gate charge ID=5A; VDS=15V; VGS=5V; Tj=25°C; gate-source charge - 2.7 - nC

see Figure 11

- 10.7 - nC

gate-drain charge - 3.9 - nC input capacitance VDS=15V; VGS= 0 V; f = 1 MHz; Tj=25°C; output capacitance - 200 - pF

see Figure 12

reverse transfer

- 752 - pF

- 130 - pF

capacitance

d(on)

d(off)

turn-on delay time VDS=15V; RL=10Ω; VGS=10V;

=6Ω; Tj=25°C; ID=1.5A

rise time - 7 - ns

G(ext)

turn-off delay time - 23 - ns fall time - 11 - ns

-6-ns

Source-drain diode

source-drain voltage IS=7A; VGS=0V; Tj= 25 °C; see Figure 13 - 0.86 1.1 V reverse recovery time IS=7A; dIS/dt = -100 A/µs; VGS=0V;

=30V; Tj=25°C

recovered charge - 5 - nC

-25-ns

Product data sheet Rev. 03 — 27 April 2010 5 of 13

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NXP Semiconductors

PHKD13N03LT

Dual N-channel TrenchMOS logic level FET

003aaa325

2.8 V

2.7 V

2.6 V

2.5 V

2.4 V

2.3 V

VDS (V)

(A)

10 V 5 V 3 V

010.80.4 0.60.2

VGS (V) =

Fig 5. Output characteristics: drain current as a

function of drain-source voltage; typical values

003aaa426

(A)

−1

−2

VDS > ID × R

(A)

0321

DSon

Tj = 150 °C 25 °C

003aaa326

VGS (V)

Fig 6. Transfer characteristics: drain current as a

function of gate-source voltage; typical value s

03aa33

2.5

GS(th)

(V)

max

−3

−4

−5

−6

0321

min typ max

VGS (V)

Fig 7. Sub-threshold drain current as a function of

gate-source voltage

1.5

0.5

-60 0 60 120 180

typ

min

(°C)

Fig 8. Gate-source threshold voltage as a function of

junction temperature

Product data sheet Rev. 03 — 27 April 2010 6 of 13

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NXP Semiconductors

PHKD13N03LT

Dual N-channel TrenchMOS logic level FET

003aaa327

3 V

4 V

5 V

10 V

ID (A)

DSon

(mΩ)

0108462

2.5 V 2.6 V 2.8 V

VGS (V) =

Fig 9. Drain-source on-state resistance as a function

of drain current; typical values

(V)

003aaa330

03aa27

(°C)

1.5

0.5

−60 0 60 120 180

Fig 10. Normalized drain-source on-state resistance

factor as a function of junction temperature

003aaa328

(pF)

015105

QG (nC)

Fig 11. Gate-source voltage as a function of gate

charge; typical values

−1

VDS (V)

iss

oss

rss

102101

Fig 12. Input, output and reverse transfer capacitances

as a function of drain-source voltage; typical values

Product data sheet Rev. 03 — 27 April 2010 7 of 13

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NXP Semiconductors

PHKD13N03LT

Dual N-channel TrenchMOS logic level FET

(A)

0.2 10.80.4 0.6

150 °C

003aaa329

Tj = 25 °C

VSD (V)

Fig 13. Source current as a function of source-drain voltage; typical values

Product data sheet Rev. 03 — 27 April 2010 8 of 13

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NXP Semiconductors

-1

7. Package outline

PHKD13N03LT

Dual N-channel TrenchMOS logic level FET

O8: plastic small outline package; 8 leads; body width 3.9 mm

pin 1 index

w M

detail X

v M

(A )

SOT96

0 2.5 5 mm

scale

DIMENSIONS (inch dimensions are derived from the original mm dimensions)

OUTLINE

VERSION

SOT96-1

A1A2A3b

max.

0.25

1.75

0.10

0.010

0.069

0.004

1.45

1.25

0.057

0.049

IEC JEDEC JEITA

076E03 MS-012

0.25

0.01

0.49

0.36

0.019

0.014

0.25

0.19

0.0100

0.0075

UNIT

inches

Notes

1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.

2. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included.

(1)E(2)

5.0

4.8

0.20

0.19

REFERENCES

eHELLpQZywv θ

4.0

3.8

0.16

0.15

1.27

0.05

6.2

5.8

0.244

0.228

1.05

1.0

0.4

0.039

0.016

0.7

0.6

0.028

0.024

0.25 0.10.25

0.010.010.041 0.004

EUROPEAN

PROJECTION

(1)

0.7

0.3

0.028

0.012

ISSUE DATE

99-12-27 03-02-18

Fig 14. Package outline SOT96-1 (SO8)

Product data sheet Rev. 03 — 27 April 2010 9 of 13

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NXP Semiconductors

8. Revision history

PHKD13N03LT

Dual N-channel TrenchMOS logic level FET

Table 7. Revision history

Document ID Release date Data sheet status Change notice Supersedes

PHKD13N03LT_3 20100427 Product data sheet - PHKD13N03LT_2 Modifications: PHKD13N03LT_2 20090306 Product data sheet - PHKD13N03LT-01 PHKD13N03LT-01

(9397 750 11612)

• Various changes to content.

20030623 Product data - -

Product data sheet Rev. 03 — 27 April 2010 10 of 13

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NXP Semiconductors

PHKD13N03LT

Dual N-channel TrenchMOS logic level FET

9. Legal information

9.1 Data sheet status

Document status

Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification.

[1] Please consult the most recently issued document before initiating or completing a design. [2] The term 'short data sheet' is explained in section "Definitions". [3] The product status of device(s) des cribed in this document may have changed since this document was published and may differ in case of multiple devices. The latest product

status information is available on the Internet at URL http://www.nxp.com.

[1][2]

Product status

[3]

Definition

9.2 Definitions

Draft — The document is a draft version only. The content is still under

internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information.

Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied u pon to co nt ain det ailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail.

Product specification — The information and data provided in a Product data sheet shall define the specification of the product as agreed between NXP Semiconductors and its customer, unless NXP Semiconductors and customer have explicitly agreed otherwise in writing. In no event however, shall an agreement be valid in which the NXP Semiconductors product is deemed to offer functions and qualities beyond those described in the Product data sheet.

9.3 Disclaimers

Limited warranty and liability — Information in this document is believed to

be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information.

In no event shall NXP Semiconductors be lia ble for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory.

Notwithstanding any damages that customer might incur for any reason whatsoever, NXP Semi conductors’ aggregat e and cumulative liabil ity towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of NXP Semiconductors.

Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof.

Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonabl y be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk.

Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification.

NXP Semiconductors does not accept any liability related to any default , damage, costs or problem which is based on a weakness or default in the customer application/use or the application/use of customer’s third party customer(s) (hereinafter both referred t o as “Application”). It is customer’s sole responsibility to check whether the NXP Semiconductors product is suitable and fit for the Application planned. Customer has to do all necessary testing for the Application in order to avoid a default of the Application and the product. NXP Semiconductors does not accept any liability in this respect.

Quick reference data — The Quick reference data is an extract of the product data given in the Limiting values and Characteri stics sections of this document, and as such is not complete, exhaustive or legally binding. Limiting values — Stress above one or more limiting values (as de fined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device.

Terms and conditions of commercial sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. NXP Semiconductors hereby expressly objects to applying the customer’s general terms and conditions with regard to the purchase of NXP Semiconductors products by customer.

No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell product s that is ope n for accept ance or the gr ant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights.

Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from national authorities.

, unless otherwise

Product data sheet Rev. 03 — 27 April 2010 11 of 13

Page 12

NXP Semiconductors

PHKD13N03LT

Dual N-channel TrenchMOS logic level FET

Non-automotive qualified products — Unless this data sheet expressly

states that this specific NXP Semiconductors product is automotive qualified, the product is not suitable for automotive use. It i s neither qua lif ied nor test ed in accordance with automotive testing or application requirements. NXP Semiconductors accepts no liability for inclusion and/or use of non-automotive qualified products in automotive equ ipment or applications.

In the event that customer uses the product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without NXP Semiconductors’ warranty of the product for such automotive applications, use and specifications, and (b) whenever customer uses the product for automotive applications beyond NXP Semiconductors’ specifications such use shall be solely at customer’s own risk, and (c) customer fully indemnifies NXP Semiconductors for any liability, damages or failed produ ct claims resulting from customer design and use of the product for automotive applications beyond NXP Semiconductors’ standard warranty and NXP Semiconductors’ product specifications.

9.4 Trademarks

Notice: All referenced brands, prod uct names, service names and trad emarks are the property of their respective owners.

Adelante, Bitport, Bitsound, CoolFlux, CoReUse, DESFire, EZ-HV, FabKey, GreenChip, HiPerSmart, HITAG, I²C-bus logo, ICODE, I-CODE, ITEC, Labelution, MIFARE, MIFARE Plus, MIFARE Ultralight, MoReUse, QLPAK, Silicon Tuner, SiliconMAX, SmartXA, STARplug, TOPFET, TrenchMOS, TriMedia and UCODE — are trademarks of NXP B.V.

HD Radio and HD Radio logo — are trademarks of iBiquity Digital

Corporation.

10. Contact information

For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected]

Product data sheet Rev. 03 — 27 April 2010 12 of 13

Page 13

NXP Semiconductors

11. Contents

1 Product profile . . . . . . . . . . . . . . . . . . . . . . . . . . .1

1.1 General description . . . . . . . . . . . . . . . . . . . . . .1

1.2 Features and benefits. . . . . . . . . . . . . . . . . . . . .1

1.3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . .1

1.4 Quick reference data . . . . . . . . . . . . . . . . . . . . .1

2 Pinning information. . . . . . . . . . . . . . . . . . . . . . .2

3 Ordering information. . . . . . . . . . . . . . . . . . . . . .2

4 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . .2

5 Thermal characteristics . . . . . . . . . . . . . . . . . . .4

6 Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . .5

7 Package outline . . . . . . . . . . . . . . . . . . . . . . . . . .9

8 Revision history. . . . . . . . . . . . . . . . . . . . . . . . .10

9 Legal information . . . . . . . . . . . . . . . . . . . . . . . .11

9.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . .11

9.2 Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . .11

9.3 Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . .11

9.4 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . .12

10 Contact information. . . . . . . . . . . . . . . . . . . . . .12

PHKD13N03LT

Dual N-channel TrenchMOS logic level FET

Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’.

For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected]

Date of release: 27 April 2010

Document identifier: PHKD13N03LT