Philips PHK28NQ03LT User Guide
M3D315
1. Product profile
1.1 Description
1.2 Features
1.3 Applications
PHK28NQ03LT
TrenchMOS™ logic level FET
Rev. 02 — 10 April 2003 Product data
N-channel enhancement mode field-effect transistor in a plastic package using
TrenchMOS™ technology.
Product availability:
PHK28NQ03LT in SOT96-1 (SO8).
■ Logic level compatible ■ Low gate charge.
■ DC-to-DC converters ■ Switched mode power supplies.
1.4 Quick reference data
■ VDS≤ 30 V ■ ID≤ 23.7 A
■ P
≤ 6.25 W ■ R
tot
DSon
≤ 6.5 mΩ.
2. Pinning information
Table 1: Pinning - SOT96-1 simplified outline and symbol
Pin Description Simplified outline Symbol
1,2,3 source (s)
4 gate (g)
5,6,7,8 drain (d)
8
1
Top view MBK187
SOT96-1 (SO8)
5
4
MBB076
d
g
s
Philips Semiconductors
PHK28NQ03LT
TrenchMOS™ logic level FET
3. Limiting values
Table 2: Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol Parameter Conditions Min Max Unit
V
DS
V
DGR
V
GS
I
D
I
DM
P
tot
T
stg
T
j
Source-drain diode
I
S
I
SM
drain-source voltage (DC) 25 °C ≤ Tj≤ 150 °C - 30 V
drain-gate voltage (DC) 25 °C ≤ Tj≤ 150 °C; RGS=20kΩ -30V
gate-source voltage - 20 V
drain current (DC) Tsp=25°C; VGS=10V;Figure 2 and 3 - 23.7 A
= 100 °C; VGS=10V;Figure 2 -15A
T
sp
peak drain current Tsp=25°C; pulsed; tp≤ 10 µs; Figure 3 -60A
total power dissipation Tsp=25°C; Figure 1 - 6.25 W
storage temperature −55 +150 °C
junction temperature −55 +150 °C
source (diode forward) current (DC) Tsp=25°C - 5.2 A
peak source (diode forward) current Tsp=25°C; pulsed; tp≤ 10 µs - 20.8 A
9397 750 11367
Product data Rev. 02 — 10 April 2003 2 of 12
© Koninklijke Philips Electronics N.V. 2003. All rights reserved.
Philips Semiconductors
PHK28NQ03LT
TrenchMOS™ logic level FET
120
P
der
(%)
80
40
0
0 50 100 150 200
P
tot
P
der
-----------------------
P
tot 25 C°()
100%×= I
03aa17
Tsp (°C)
Fig 1. Normalized total power dissipation as a
function of solder point temperature.
2
10
(A)
limit R
I
D
DSon
= V
DS
/ I
D
120
I
der
(%)
80
40
0
0 50 100 150 200
I
D
der
-------------------
I
D25C
()
100%×=
°
03aa25
Tsp (°C)
Fig 2. Normalized continuous drain current as a
function of solder point temperature.
03ak85
tp = 10 µs
100 µs
10
1
10
DC
-1
-1
10
1 10 10
1 ms
10 ms
100 ms
VDS (V)
2
Tsp=25°C; IDM is single pulse; VGS=10V
Fig 3. Safe operating area; continuous and peak drain currents as a function of drain-source voltage.
9397 750 11367
Product data Rev. 02 — 10 April 2003 3 of 12
© Koninklijke Philips Electronics N.V. 2003. All rights reserved.
Philips Semiconductors
PHK28NQ03LT
TrenchMOS™ logic level FET
4. Thermal characteristics
Table 3: Thermal characteristics
Symbol Parameter Conditions Min Typ Max Unit
R
th(j-sp)
thermal resistance from junction to solder point Figure 4 --20K/W
4.1 Transient thermal impedance
2
10
Z
th(j-sp)
(K/W)
= 0.5
δ
10
0.2
0.1
0.05
1
10
0.02
single pulse
-1
-4
10
-3
10
-2
10
-1
10
P
t
p
T
1 10
tp (s)
Fig 4. Transient thermal impedance from junction to solder point as a function of pulse duration.
03ak84
δ =
t
p
T
t
9397 750 11367
© Koninklijke Philips Electronics N.V. 2003. All rights reserved.
Product data Rev. 02 — 10 April 2003 4 of 12
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