Philips phd97nq03lt Datasheet

1. Product profile

1.1 General description

Logic level N-channel enhancement mode Field-Effect Transistor (FET) in a plastic
package using TrenchMOS technology. This product is designed and qualified for use in
computing, communications, consumer and industrial applications only.

1.2 Features and benefits

PHD97NQ03LT

N-channel TrenchMOS logic level FET

Rev. 01 — 24 March 2009 Product data sheet

 Fast switching
 Lead-free packing
 Logic level threshold

 Low on-state resistance
 Suitable for high frequency

applications due to fast switching
characteristics

1.3 Applications

 Computer motherboard high

frequency DC-to-DC convertors

 Switched-mode power supplies
 Voltage regulators

1.4 Quick reference data

Table 1. Quick reference

Symbol Parameter Conditions Min Typ Max Unit

V

DS

I

D

P

tot

Dynamic characteristics

Q

GD

Static characteristics

R

DSon

drain-source voltage Tj≥ 25 °C; Tj≤ 175 °C - - 25 V
drain current Tmb=25°C; VGS=10V;

see Figure 1

total power
dissipation

gate-drain charge VGS= 4.5 V; ID=25A;

drain-source
on-state resistance

Tmb= 25 °C; see Figure 2 - - 107 W

VDS= 12 V; see Figure 9;
see Figure 10

VGS=10V; ID=25A;

= 25 °C; see Figure 7;

T

j

see Figure 8

; see Figure 3

--75A

-1.9-nC

-5.36.3mΩ

NXP Semiconductors

2. Pinning information

PHD97NQ03LT

N-channel TrenchMOS logic level FET

Table 2. Pinning information

Pin Symbol Description Simplified outline Graphic symbol

1G gate
2D drain
3S source

mb

G

mb D mounting base; connected to

drain

2

3

1

mbb076

SOT428

(SC -63; D PAK)

3. Ordering information

Table 3. Ordering information

Type number Package

PHD97NQ03LT SC-63; DPAK plastic single-ended surface-mounted package (DPAK); 3 leads

Name Description Version

(one lead cropped)

4. Limiting values

D

S

SOT428

Table 4. Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134).

Symbol Parameter Conditions Min Max Unit

V

DS

V

DGR

V

GS

I

D

I

DM

P

tot

T

stg

T

j

Source-drain diode

I

S

I

SM

Avalanche ruggedness

E

DS(AL)S

drain-source voltage Tj≥ 25 °C; Tj≤ 175 °C - 25 V
drain-gate voltage Tj≥ 25 °C; Tj≤ 175 °C; RGS=20kΩ -25V
gate-source voltage -20 20 V
drain current VGS=10V; Tmb= 100 °C; see Figure 1 -69A

=10V; Tmb=25°C; see Figure 1; see Figure 3 -75A

V

GS

peak drain current tp≤ 10 µs; pulsed; Tmb=25°C; see Figure 3 -300A
total power dissipation Tmb=25°C; see Figure 2 -107W
storage temperature -55 175 °C
junction temperature -55 175 °C

source current Tmb=25°C - 75 A
peak source current tp≤ 10 µs; pulsed; Tmb=25°C - 240 A

non-repetitive
drain-source avalanche

VGS=10V; T
unclamped; t

=25°C; ID=35A; V

j(init)

=0.1ms; RGS=50Ω

p

sup

≤ 25 V;

-60mJ

energy

PHD97NQ03LT_1 © NXP B.V. 2009. All rights reserved.

Product data sheet Rev. 01 — 24 March 2009 2 of 12

NXP Semiconductors

PHD97NQ03LT

N-channel TrenchMOS logic level FET

120

I

der

(%)

80

40

0

0 20015050 100

003aab533

Tj (°C)

Fig 1. Normalized continuous drain current as a

function of mounting base temperature

3

10

120

P

der

(%)

80

40

0

0 20015050 100

03aa16

Tmb (°C)

Fig 2. Normalized total power dissipation as a

function of mounting base temperature

003aab556

I

(A)

D

2

10

10

1

−1

10

R

DSon

= VDS / I

D

DC

101

tp = 10 μs

100 μs

1 ms

10 ms

VDS (V)

Fig 3. Safe operating area; continuous and peak drain currents as a function of drain-source voltage

2

10

PHD97NQ03LT_1 © NXP B.V. 2009. All rights reserved.

Product data sheet Rev. 01 — 24 March 2009 3 of 12

NXP Semiconductors

5. Thermal characteristics

PHD97NQ03LT

N-channel TrenchMOS logic level FET

Table 5. Thermal characteristics

Symbol Parameter Conditions Min Typ Max Unit

R

th(j-mb)

thermal resistance from junction to

see Figure 4 --1.4K/W

mounting base

R

th(j-a)

thermal resistance from junction to

minimum footprint [1] -75-K/W

ambient

[1] Mounted on a printed-circuit board; vertical in still air

10

Z

th(j-mb )

(K/W)

1

10

10

δ

= 0.5

0.2

0.1

-1

0.05

0.02

-2

-5

10

single pulse

10

-4

-3

10

-2

10

-1

10

P

1 10

003aab535

t

p

δ =

T

t

p

T

(s)

t

p

t

Fig 4. Transient thermal impedance from junction to mounting base as a function of pulse duration

PHD97NQ03LT_1 © NXP B.V. 2009. All rights reserved.

Product data sheet Rev. 01 — 24 March 2009 4 of 12

NXP Semiconductors

6. Characteristics

PHD97NQ03LT

N-channel TrenchMOS logic level FET

Table 6. Characteristics

Symbol Parameter Conditions Min Typ Max Unit

Static characteristics

V

(BR)DSS

V

GS(th)

drain-source
breakdown voltage

gate-source threshold
voltage

ID=250µA; VGS=0V; Tj=25°C 25 - - V

=250µA; VGS=0V; Tj=-55°C 22 - - V

I

D

ID=1mA; VDS = VGS; Tj=25°C;

1.3 1.7 2.15 V

see Figure 5; see Figure 6

=1mA; VDS = VGS; Tj= 175 °C;

I

D

0.7 - - V

see Figure 5
I

=1mA; VDS = VGS; Tj=-55°C;

D

--2.6V

see Figure 5

I

DSS

I

GSS

R

DSon

drain leakage current VDS=25V; VGS=0V; Tj=25°C --1µA
gate leakage current VGS=16V; VDS=0V; Tj= 25 °C - - 100 nA

=-16V; VDS=0V; Tj= 25 °C - - 100 nA

V

GS

drain-source on-state
resistance

VGS=10V; ID=25A; Tj= 175 °C;
see Figure 7; see Figure 8

=4.5V; ID=25A; Tj=25°C;

V

GS

see Figure 7
V

=10V; ID=25A; Tj=25°C;

GS

; see Figure 8

- 10.1 12 mΩ

-810.6mΩ

-5.36.3mΩ

see Figure 7; see Figure 8

I

DSS

R

G

drain leakage current VDS=25V; VGS=0V; Tj= 175 °C - - 100 µA
gate resistance f = 1 MHz - 1.5 - Ω

Dynamic characteristi cs

Q

Q
Q

G(tot)

GS
GS1

total gate charge ID=25A; VDS=12V; VGS=4.5V;

see Figure 9
I

=0A; VDS=0V; VGS= 4.5 V - 10.2 - nC

D

; see Figure 10

gate-source charge ID=25A; VDS=12V; VGS=4.5V;
pre-threshold

see Figure 9; see Figure 10

-11.7-nC

-6.2-nC

-3.4-nC

gate-source charge

Q

GS2

post-threshold

-2.8-nC

gate-source charge
Q
V

C

GD

GS(pl)

iss

gate-drain charge - 1.9 - nC

gate-source plateau

voltage

input capacitance VDS=12V; VGS= 0 V; f = 1 MHz;

ID=25A; VDS=12V; see Figure 9; see

Figure 10

-3.1-V

- 1570 - pF

Tj=25°C; see Figure 11

=0V; VGS=0V; f=1MHz;

V

DS

- 1800 - pF

Tj=25°C

C

oss

C

rss

output capacitance VDS=12V; VGS= 0 V; f = 1 MHz;

=25°C; see Figure 11

T

reverse transfer

j

- 380 - pF

- 160 - pF

capacitance

PHD97NQ03LT_1 © NXP B.V. 2009. All rights reserved.

Product data sheet Rev. 01 — 24 March 2009 5 of 12

NXP Semiconductors

PHD97NQ03LT

N-channel TrenchMOS logic level FET

Table 6. Characteristics

…continued

Symbol Parameter Conditions Min Typ Max Unit

t

d(on)

t

r

t

d(off)

t

f

turn-on delay time VDS=12V; RL=0.5Ω; VGS=4.5V;

=5.6Ω

R

rise time - 33 - ns

G(ext)

turn-off delay time - 20 - ns

fall time - 12 - ns

-18-ns

Source-drain diode

V

SD

source-drain voltage IS=25A; VGS=0V; Tj=25°C;

- 0.87 1.2 V

see Figure 12

t

rr

Q

r

V

GS(th)

reverse recovery time IS=20A; dIS/dt = -100 A/µs; VGS=0V;

=30V

V

recovered charge - 14 - nC

3

(V)

2

1.5

max

typ

min

DS

003aab272

(A)

−3

10

I

D

−4

10

-38-ns

003aab271

max

typ

min

1

0.5

0

-60 180120060

Tj (°C)

Fig 5. Gate-source threshold voltage as a function of

junction temperature

−5

10

−6

10

0 2.521 1.50.5

V

(V)

GS

Fig 6. Sub-threshold drain current as a function of

gate-source voltage

PHD97NQ03LT_1 © NXP B.V. 2009. All rights reserved.

Product data sheet Rev. 01 — 24 March 2009 6 of 12

NXP Semiconductors

8

PHD97NQ03LT

N-channel TrenchMOS logic level FET

2

a

1.6

1.2

0.8

0.4

0

−60 180120060

003aab467

Tj (°C)

Fig 7. Normalized drain-source on-state resistance

factor as a function of junction temperature

003aab539

V

(V)

GS

10

8

ID = 25 A

= 25 °C

T

j

25

R

DSon

(mΩ)

20

15

10

5

0

0 20406080

VGS (V) =

3.3

003aab537

3.7

4.1

4.5

10

I

(A)

D

5
6

Fig 8. Drain-source on-state resistance as a function

of drain current; typical values

V

DS

I

D

6

4

2

0

0102030

12 V

VDS = 19 V

Q

(nC)

G

Fig 9. Gate-source voltage as a function of gate

charge; typical values

V

GS(pl)

V

GS(th)

V

GS

Q

GS1QGS2

Q

G(tot)

Q

GD

003aaa50

Q

GS

Fig 10. Gate charge waveform definitions

PHD97NQ03LT_1 © NXP B.V. 2009. All rights reserved.

Product data sheet Rev. 01 — 24 March 2009 7 of 12

NXP Semiconductors

PHD97NQ03LT

N-channel TrenchMOS logic level FET

10

C

(pF)

10

10

4

3

2

-1

10

1 10 10

003aab542

C

iss

C

oss

C

rss

VDS (V)

2

Fig 11. Input, output and reverse transfer capacitances

as a function of drain-source voltage; typical
values

80

I

S

(A)

60

40

20

0

0 0.4 0.8 1.2

175 °C

003aab541

Tj = 25 °C

(V)

V

SD

Fig 12. Source current as a function of source-drain

voltage; typical values

PHD97NQ03LT_1 © NXP B.V. 2009. All rights reserved.

Product data sheet Rev. 01 — 24 March 2009 8 of 12

NXP Semiconductors

7. Package outline

Plastic single-ended surface-mounted package (DPAK); 3 leads (one lead cropped)

y

PHD97NQ03LT

N-channel TrenchMOS logic level FET

SOT428

E

b

2

L

2

b

1

2

13

b

e

e

1

A

D

1

H

L

M

wA

D

mounting
base

L

1

A

A

1

c

E

1

D

2

0 5 10 mm

scale

DIMENSIONS (mm are the original dimensions)

0.2

y

max

0.2

UNIT

mm

OUTLINE
VERSION

SOT428 SC-63

A

Ab

1

0.93

2.38

0.46

2.22

b

bcD

1.1

0.89

0.9

0.71

IEC JEDEC JEITA

2

1

5.46

0.56

5.00

0.20

TO-252

1

6.22

5.98

REFERENCES

D

min

4.0

2

E

1

Ee

min

6.73

4.45

6.47

e

2.285 4.57

L

1

Lw

H

1

D

10.4

2.95

9.6

2.55

EUROPEAN

PROJECTION

min

0.5

L

2

0.9

0.5

ISSUE DATE

06-02-14

06-03-16

Fig 13. Package outline SOT428 (DPAK)

PHD97NQ03LT_1 © NXP B.V. 2009. All rights reserved.

Product data sheet Rev. 01 — 24 March 2009 9 of 12

NXP Semiconductors

8. Revision history

PHD97NQ03LT

N-channel TrenchMOS logic level FET

Table 7. Revision history

Document ID Release date Data sheet status Change notice Supersedes

PHD97NQ03LT_1 20090324 Product data sheet - -

PHD97NQ03LT_1 © NXP B.V. 2009. All rights reserved.

Product data sheet Rev. 01 — 24 March 2009 10 of 12

NXP Semiconductors

PHD97NQ03LT

N-channel TrenchMOS logic level FET

9. Legal information

9.1 Data sheet status

Document status

Objective [short] data sheet Development This document contains data from the objective specification for product development.
Preliminary [short] data sheet Qualification This document contains data from the preliminary specification.
Product [short] data sheet Production This document contains the product specification.

[1] Please consult the most recently issued document before initiating or completing a design.
[2] The term 'short data sheet' is explained in section "Definitions".
[3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product

status information is available on the Internet at URL http://www.nxp.com

[1][2]

Product status

[3]

Definition

.

9.2 Definitions

Draft — The document is a draft version only. The content is still under

internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.

Short data sheet — A short data sheet is an extract from a full dat a sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied u pon to co nt ain det ailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.

9.3 Disclaimers

General — Information in this document is believed to be accurate and

reliable. However, NXP Semiconduct ors does not give any repr esentatio ns or
warranties, expressed or implied, as to the accuracy or completeness of such
information and shall have no liability for the consequences of use of such
information.

Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.

Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in medical, military, aircraft,
space or life support equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors accepts no liability for inclusion and/or use of
NXP Semiconductors products in such equipment or applications and
therefore such inclusion and/or use is at the customer’s own risk.

Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.

Quick reference data — The Quick reference data is an extract of the
product data given in the Limiting values and Characteri stics sections of this
document, and as such is not complete, exhaustive or legally binding.

Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) may cause permanent
damage to the device. Limiting values are stress ratings only and operation of
the device at these or any other conditions above those given in the
Characteristics sections of this document is not implied. Exposure to limiting
values for extended periods may affect device reliability.

Terms and conditions of sale — NXP Semiconductors products are sold
subject to the general terms and conditions of commercial sale, as published
at http://www.nxp.com/profile/terms
intellectual property rights infringement and limitation of liability, unless
explicitly otherwise agreed to in writing by NXP Semiconductors. In case of
any inconsistency or conflict between information in this document and such
terms and conditions, the latter will prevail.

No offer to sell or license — Nothing in this document may be interpreted or
construed as an offer to sell product s that is ope n for accept ance or the gr ant,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.

Export control — This document as well as the item(s) described herein may
be subject to export control regulations. Export might require a prior
authorization from national authorities.

, including those pertaining to warranty,

9.4 Trademarks

Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.

TrenchMOS — is a trademark of NXP B.V.

10. Contact information

For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [email protected]

PHD97NQ03LT_1 © NXP B.V. 2009. All rights reserved.

Product data sheet Rev. 01 — 24 March 2009 11 of 12

NXP Semiconductors

11. Contents

1 Product profile . . . . . . . . . . . . . . . . . . . . . . . . . . .1

1.1 General description . . . . . . . . . . . . . . . . . . . . . .1

1.2 Features and benefits. . . . . . . . . . . . . . . . . . . . .1

1.3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . .1

1.4 Quick reference data . . . . . . . . . . . . . . . . . . . . .1

2 Pinning information. . . . . . . . . . . . . . . . . . . . . . .2

3 Ordering information. . . . . . . . . . . . . . . . . . . . . .2

4 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . .2

5 Thermal characteristics . . . . . . . . . . . . . . . . . . .4

6 Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . .5

7 Package outline . . . . . . . . . . . . . . . . . . . . . . . . . .9

8 Revision history. . . . . . . . . . . . . . . . . . . . . . . . .10

9 Legal information. . . . . . . . . . . . . . . . . . . . . . . .11

9.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . .11

9.2 Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . .11

9.3 Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . .11

9.4 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . .11

10 Contact information. . . . . . . . . . . . . . . . . . . . . . 11

PHD97NQ03LT

N-channel TrenchMOS logic level FET

Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.

© NXP B.V. 2009. All rights reserved.

For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [email protected]

Date of release: 24 March 2009

Document identifier: PHD97NQ03LT_1