Philips ph2520u Datasheet

Page 1

1. Product profile

1.1 General description

Ultra low level N-channel enhancement mode Field-Effect Transistor (FET) in a plastic package using TrenchMOS technology. This product is designed and qualified for use in computing, communications, consumer and industrial applications only.

1.2 Features and benefits

PH2520U

N-channel TrenchMOS ultra low level FET

Rev. 03 — 2 March 2009 Product data sheet

 Higher operating power due to low

thermal resistance

 Low conduction losses due to low

on-state resistance

 Interfaces directly with low voltage

gate drivers

1.3 Applications

 DC-to-DC convertors  Notebook computers

 Portable equipment  Switched-mode power supplies

1.4 Quick reference data

Table 1. Quick reference

Symbol Parameter Conditions Min Typ Max Unit

tot

Dynamic characteristics

Static characteristics

DSon

drain-source voltage Tj≥ 25 °C; Tj≤ 150 °C - - 20 V drain current Tmb=25°C; VGS=4.5V;

see Figure 1

total power dissipation

gate-drain charge VGS= 4.5 V; ID=50A;

drain-source on-state resistance

Tmb= 25 °C; see Figure 2 - - 62.5 W

VDS=10V; Tj=25°C; see Figure 11; see Figure 12

VGS= 4.5 V; ID=25A;

= 25 °C; see Figure 9;

see Figure 10

; see Figure 3

- - 100 A

-18-nC

-2.12.7mΩ

Page 2

NXP Semiconductors

2. Pinning information

PH2520U

N-channel TrenchMOS ultra low level FET

Table 2. Pinning information

Pin Symbol Description Simplified outline Graphic symbol

1S source 2S source 3S source

4G gate

mb D mounting base; connected to

drain

1234

bb076

SOT669

(LFPAK)

3. Ordering information

Table 3. Ordering information

Type number Package

PH2520U LFPAK plastic single-ended surface-mounted package (LFPAK); 4 leads SOT669

Name Description Version

4. Limiting values

Table 4. Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134).

Symbol Parameter Conditions Min Max Unit

DGR

tot

stg

Source-drain diode

Avalanche ruggedness

DS(AL)S

drain-source voltage Tj≥ 25 °C; Tj≤ 150 °C - 20 V drain-gate voltage Tj≥ 25 °C; Tj≤ 150 °C; RGS=20kΩ -20V gate-source voltage -10 10 V drain current VGS=4.5V; Tmb= 100 °C; see Figure 1 -73A

peak drain current tp≤ 10 µs; pulsed; Tmb=25°C; see Figure 3 -300A total power dissipation Tmb=25°C; see Figure 2 -62.5W storage temperature -55 150 °C junction temperature -55 150 °C

source current Tmb=25°C - 52 A peak source current tp≤ 10 µs; pulsed; Tmb=25°C - 150 A

non-repetitive drain-source avalanche energy

=4.5V; Tmb=25°C; see Figure 1;

-100A

see Figure 3

VGS=10V; Tj=25°C; ID=70.7A; RGS=50Ω; V

≤ 20 V; tp= 0.1 ms; unclamped

sup

-250mJ

Product data sheet Rev. 03 — 2 March 2009 2 of 12

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NXP Semiconductors

PH2520U

N-channel TrenchMOS ultra low level FET

120

der

(%)

0 50 100 150 200

003aab131

(°C)

Fig 1. Normalized continuous drain current as a

function of mounting base temperature

(A)

Limit R

DSon

= VDS/I

120

der

(%)

0 20015050 100

03aa15

Tmb (°C)

Fig 2. Normalized total power dissipation as a

function of mounting base temperature

003aaa345

tp = 100 μs

1 ms

10 ms

100 ms 1 s

-1

1 10 10

VDS (V)

Fig 3. Safe operating area; continuous and peak drain currents as a function of drain-source voltage

Product data sheet Rev. 03 — 2 March 2009 3 of 12

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NXP Semiconductors

5. Thermal characteristics

PH2520U

N-channel TrenchMOS ultra low level FET

Table 5. Thermal characteristics

Symbol Parameter Conditions Min Typ Max Unit

th(j-mb)

thermal resistance from

see Figure 4 --2K/W junction to mounting base

th(j-mb )

(K/W)

= 0.5

0.2

0.1

0.05

0.02

-1

-4

single pulse

-3

-2

-1

1 10 10

003aaa346

δ =

tp (s)

Fig 4. Transient thermal impedance from junction to mounting base as a function of pulse duration

Product data sheet Rev. 03 — 2 March 2009 4 of 12

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NXP Semiconductors

6. Characteristics

PH2520U

N-channel TrenchMOS ultra low level FET

Table 6. Characteristics

Symbol Parameter Conditions Min Typ Max Unit

Static characteristics

(BR)DSS

GS(th)

DSS

GSS

DSon

drain-source breakdown voltage

gate-source threshold voltage

drain leakage current VDS=20V; VGS=0V; Tj= 25 °C - 0.06 1 µA

gate leakage current VGS=10V; VDS=0V; Tj= 25 °C - 20 100 nA

drain-source on-state resistance

ID=250µA; VGS=0V; Tj=-55°C 18 - - V

=250µA; VGS=0V; Tj=25°C 20 - - V

ID=1mA; VDS = VGS; Tj=-55°C;

--1.2V

see Figure 7; see Figure 8

=1mA; VDS = VGS; Tj= 150 °C;

see Figure 7

=1mA; VDS = VGS; Tj=25°C;

see Figure 7

=20V; VGS=0V; Tj= 150 °C - - 500 µA

=-10V; VDS=0V; Tj= 25 °C - 20 100 nA

; see Figure 8

VGS=2.5V; ID=25A; Tj=25°C;

0.25 - - V

0.45 0.7 0.95 V

-2.83.9mΩ

see Figure 9; see Figure 10

=4.5V; ID=25A; Tj=150°C;

see Figure 9

=4.5V; ID=25A; Tj=25°C;

; see Figure 10

-3.34.3mΩ

-2.12.7mΩ

see Figure 9; see Figure 10

internal gate resistance

f=1MHz; Tj= 25 °C - 1.65 - Ω (AC)

Dynamic characteristi cs

Q Q Q V

C C C

G(tot) GS GD

GS(pl)

iss oss rss

total gate charge ID=50A; VDS=10V; VGS=4.5V;

=25°C; see Figure 11;

gate-source charge - 17 - nC

see Figure 12

-78-nC

gate-drain charge - 18 - nC gate-source plateau

voltage input capacitance VDS=10V; VGS= 0 V; f = 1 MHz; output capacitance - 1190 - pF reverse transfer

ID=50A; VDS=10V; Tj=25°C;

see Figure 11; see Figure 12

Tj=25°C; see Figure 13

-2.2-V

- 5850 - pF

- 831 - pF

capacitance

d(on)

d(off)

turn-on delay time VDS=10V; RL=1Ω; VGS=4.5V;

=4.7Ω; Tj=25°C

rise time - 240 - ns

G(ext)

turn-off delay time - 318 - ns fall time - 234 - ns

-34-ns

Source-drain diode

source-drain voltage IS=25A; VGS=0V; Tj=25°C;

- 0.85 1.2 V

see Figure 14

reverse recovery time IS=20A; dIS/dt = -100 A/µs; VGS=0V;

-65-ns

VDS=20V; Tj=25°C

Product data sheet Rev. 03 — 2 March 2009 5 of 12

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NXP Semiconductors

PH2520U

N-channel TrenchMOS ultra low level FET

4.5

2.5

(A)

1.8

0 0.2 0.4 0.6

1.6

003aaa347

1.4

1.3

VGS (V) = 1.2

(V)

Fig 5. Output characteristics: drain current as a

function of drain-source voltage; typical values

03aj65

1.2

GS(th)

(V)

0.9

max

(A)

Tj = 150 °C

25 °C

0 0.5 1 1 .5 2

003aaa348

(V)

Fig 6. Transfer characteristics: drain current as a

function of gate-source voltage; typical values

03aj64

(A)

−3

−4

0.6

0.3

−60 180120060

typ

min

Tj (°C)

Fig 7. Gate-source threshold voltage as a function of

junction temperature

−5

−6

0 0.2 0.4 0.6 0.8 1

min typ max

(V)

Fig 8. Sub-threshold drain current as a function of

gate-source voltage

Product data sheet Rev. 03 — 2 March 2009 6 of 12

Page 7

NXP Semiconductors

003aaa508

PH2520U

N-channel TrenchMOS ultra low level FET

(mΩ)

VGS (V) =

DSon

0 1020304050

1.41.3

003aaa349

1.6

1.8

2.5

4.5

(A)

Fig 9. Drain-source on-state resistance as a function

of drain current; typical values

(V)

003aaa352

03af18

(°C)

1.5

0.5

-60 0 60 120 180

Fig 10. Normalized drain-so urce on-state resistance

factor as a function of junction temperature

0 25 50 75 100

(nC)

Fig 11. G ate-source voltage as a function of gate

charge; typical values

GS(pl)

GS(th)

GS1QGS2

G(tot)

Fig 12. Gate charge waveform definitions

Product data sheet Rev. 03 — 2 March 2009 7 of 12

Page 8

NXP Semiconductors

PH2520U

N-channel TrenchMOS ultra low level FET

(pF)

-1

1 10 10

003aaa350

iss

oss

rss

VDS (V)

Fig 13. Input, output and reverse transfer capacitances

as a function of drain-source voltage; typical values

(A)

0.2 0.4 0.6 0.8 1

150 °C

003aaa351

Tj = 25 °C

(V)

Fig 14. Source current as a function of source-drain

voltage; typical values

Product data sheet Rev. 03 — 2 March 2009 8 of 12

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NXP Semiconductors

7. Package outline

PH2520U

N-channel TrenchMOS ultra low level FET

lastic single-ended surface-mounted package (LFPAK); 4 leads

234

1/2 e

mounting

base

SOT66

0 2.5 5 mm

scale

DIMENSIONS (mm are the original dimensions)

UNIT

Note

1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.

OUTLINE VERSION

0.15

1.20

0.00

1.01

SOT669 MO-235

1.10

0.95

bcA e

0.25 4.20 1.27 0.25 0.1

IEC JEDEC JEITA

0.50

0.35

4.41

3.62

2.2

2.0

0.9

0.25

0.7

0.19

REFERENCES

0.30

0.24

(1)

4.10

3.80

max

detail X

(1)

5.0

4.8

(1)

3.3

3.1

6.2

0.85

5.8

0.40

EUROPEAN

PROJECTION

1.3

0.8

1.3

0.8

(A )

ISSUE DATE

04-10-13 06-03-16

8° 0°

Fig 15. Package outline SOT669 (LFPAK)

Product data sheet Rev. 03 — 2 March 2009 9 of 12

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NXP Semiconductors

8. Revision history

PH2520U

N-channel TrenchMOS ultra low level FET

Table 7. Revision history

Document ID Release date Data sheet status Change notice Supersedes

PH2520U_3 20090302 Product data sheet - PH2520U_2 Modifications:

• The format of this data sheet has been redesigned to comply with the new identity

guidelines of NXP Semiconductors.

• Legal texts have been adapted to the new company name where appropriate.

PH2520U_2 20051115 Product data sheet - PH2520U-01 PH2520U-01

(9397 750 11406)

20030502 Product data - -

Product data sheet Rev. 03 — 2 March 2009 10 of 12

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NXP Semiconductors

PH2520U

N-channel TrenchMOS ultra low level FET

9. Legal information

9.1 Data sheet status

Document status

Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification.

[1] Please consult the most recently issued document before initiating or completing a design. [2] The term 'short data sheet' is explained in section "Definitions". [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product

status information is available on the Internet at URL http://www.nxp.com

[1][2]

Product status

[3]

Definition

9.2 Definitions

Draft — The document is a draft version only. The content is still under

internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information.

Short data sheet — A short data sheet is an extract from a full dat a sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied u pon to co nt ain det ailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail.

9.3 Disclaimers

General — Information in this document is believed to be accurate and

reliable. However, NXP Semiconduct ors does not give any repr esentatio ns or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information.

Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof.

Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk.

Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification.

Quick reference data — The Quick reference data is an extract of the product data given in the Limiting values and Characteri stics sections of this document, and as such is not complete, exhaustive or legally binding.

Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability.

Terms and conditions of sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail.

No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell product s that is ope n for accept ance or the gr ant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights.

, including those pertaining to warranty,

9.4 Trademarks

Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners.

TrenchMOS — is a trademark of NXP B.V.

10. Contact information

For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected]

Product data sheet Rev. 03 — 2 March 2009 11 of 12

Page 12

NXP Semiconductors

11. Contents

1 Product profile . . . . . . . . . . . . . . . . . . . . . . . . . . .1

1.1 General description . . . . . . . . . . . . . . . . . . . . . .1

1.2 Features and benefits. . . . . . . . . . . . . . . . . . . . .1

1.3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . .1

1.4 Quick reference data . . . . . . . . . . . . . . . . . . . . .1

2 Pinning information. . . . . . . . . . . . . . . . . . . . . . .2

3 Ordering information. . . . . . . . . . . . . . . . . . . . . .2

4 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . .2

5 Thermal characteristics . . . . . . . . . . . . . . . . . . .4

6 Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . 5

7 Package outline . . . . . . . . . . . . . . . . . . . . . . . . . .9

8 Revision history. . . . . . . . . . . . . . . . . . . . . . . . .10

9 Legal information. . . . . . . . . . . . . . . . . . . . . . . . 11

9.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . .11

9.2 Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . .11

9.3 Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . .11

9.4 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . .11

10 Contact information. . . . . . . . . . . . . . . . . . . . . . 11

PH2520U

N-channel TrenchMOS ultra low level FET

Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’.

For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected]

Date of release: 2 March 2009

Document identifier: PH2520U_3