Philips pdiusbd12 DATASHEETS
INTEGRATED CIRCUITS
PDIUSBD12
USB interface device with parallel bus
Product specification
Supersedes data of 1998 Sep 24
1999 Jan 08
Philips Semiconductors Product specification
PDIUSBD12USB interface device with parallel bus
FEA TURES
•Complies with the Universal Serial Bus specification Rev. 1.1
•High performance USB interface device with integrated SIE,
FIFO memory, transceiver and voltage regulator
•Compliant with most Device Class specifications
•High-speed (2 Mbytes/s) parallel interface to any external
microcontroller/microprocessor
•Fully autonomous DMA operation
•Integrated 320 bytes of multi-configuration FIFO memory
•Double buffering scheme for main endpoint increases throughput
and eases real time data transfer
•1MByte/s data transfer rate achievable in Bulk mode, 1Mbit/s data
transfer rate achievable in Isochronous mode
•Bus-powered capability with very good EMI performance
•Controllable LazyClock output during suspend
•Software controllable connection to the USB bus (SoftConnect)
•Good USB connection indicator that blinks with traffic
(GoodLink)
•Programmable clock frequency output
•Complies with the ACPI, OnNOW, and USB power management
requirements
•Internal power-on reset and low voltage reset circuit
•Available in SO28 and TSSOP28 pin packages
•Full industrial grade operation from –40 to +85°C
•Higher than 8kV in-circuit ESD protection lowers cost of extra
components
•Full-scan design with high fault coverage (>99%) ensures high
quality
•Operation with dual voltages:
3.3 ± 0.3V or extended 5V supply range of 3.6 – 5.5V
•Multiple interrupt modes to facilitate both bulk and isochronous
transfers
DESCRIPTION
The PDIUSBD12 is a cost and feature-optimized USB device. It is
normally used in microcontroller-based systems and communicates
with the system microcontroller over the high speed
general-purpose parallel interface. It also supports local DMA
transfer.
This modular approach to implementing a USB interface allows the
designer to choose the optimum system microcontroller from the
available wide variety. This flexibility cuts down the development
time, risks, and costs by allowing the use of the existing architecture
and minimize firmware investments. This results in the fastest way
to develop the most cost-effective USB peripheral solution.
The PDIUSBD12 fully conforms to the USB specification Rev. 1.1.
It is also designed to be compliant with most device class
specifications: Imaging Class, Mass Storage Devices,
Communication Devices, Printing Devices, and Human Interface
Devices. As such, the PDIUSBD12 is ideally suited for many
peripherals like Printer, Scanner, External Mass Storage (Zip Drive),
Digital Still Camera, etc. It offers an immediate cost reduction for
applications that currently use SCSI implementations.
The PDIUSBD12 low suspend power consumption along with the
LazyClock output allows for easy implementation of equipment that
is compliant to the ACPI, OnNOW, and USB power management
requirements. The low operating power allows the implementation of
bus-powered peripherals.
In addition, it also incorporates features like SoftConnect,
GoodLink, programmable clock output, low frequency crystal
oscillator, and integration of termination resistors. All of these
features contribute to significant cost savings in the system
implementation and at the same time ease the implementation of
advanced USB functionality into the peripherals.
ORDERING INFORMATION
PACKAGES TEMPERATURE RANGE OUTSIDE NORTH AMERICA NORTH AMERICA PKG. DWG. #
28-pin plastic SO –40°C to +85°C PDIUSBD12 D PDIUSBD12 D SOT136-1
28-pin plastic TSSOP –40°C to +85°C PDIUSBD12 PW PDUSBD12PW DH SOT361-1
1999 Jan 08 853–21 10 20620
2
Philips Semiconductors Product specification
PDIUSBD12USB interface device with parallel bus
BLOCK DIAGRAM
6 MHz
PLL
BIT CLOCK RECOVERY
PHILIPS
SIE
3.3V
1.5k
D+
SoftConnect
VOLTAGE REGULATOR
UPSTREAM
PORT
D+
ANALOG
TX/R
X
D–
NOTE:
* This is a conceptual block diagram and does not include each individual signal.
Analog Transceiver
The integrated transceiver interfaces directly to the USB cables
through termination resistors.
Voltage Regulator
A 3.3V regulator is integrated on-chip to supply the analog
transceiver. This voltage is also provided as an output to connect to
the external 1.5 kΩ pull-up resistor. Alternatively, the PDIUSBD12
provides SoftConnect technology with integrated 1.5 kΩ pull-up
resistor.
PLL
A 6 MHz to 48 MHz clock multiplier PLL (Phase-Locked Loop) is
integrated on-chip. This allows for the use of low-cost 6 MHz crystal.
EMI is also minimized due to the lower frequency crystal. No
external components are needed for the operation of the PLL.
SoftConnect
The connection to the USB is accomplished by bringing D+ (for
high-speed USB device) high through a 1.5 kΩ pull-up resistor. In
the PDIUSBD12, the 1.5 kΩ pull-up resistor is integrated on-chip
and is not connected to V
established through a command sent by the external/system
microcontroller. This allows the system microcontroller to complete
its initialization sequence before deciding to establish connection to
the USB. Re-initialization of the USB bus connection can also be
performed without requiring to pull out the cable.
The PDIUSBD12 will check for USB VBUS availability before the
connection can be established. VBUS sensing is provided through
EOT_N pin. See the pin description for details. Sharing of VBUS
sensing and EOT_N can be easily accomplished by using VBUS
voltage as the pull up voltage for the normally open-drain output of
the DMA controller pin.
Bit Clock Recovery
The bit clock recovery circuit recovers the clock from the incoming
USB data stream using 4X over-sampling principle. It is able to track
jitter and frequency drift specified by the USB specification.
Philips Serial Interface Engine (PSIE)
The Philips SIE implements the full USB protocol layer. It is
completely hardwired for speed and needs no firmware intervention.
The functions of this block include: synchronization pattern
It should be noted that the tolerance of the internal resistors is
higher (25%) than that specified by the USB specification (5%).
However, the overall V
can still be met with good margin. The decision to make sure of this
feature lies with the users.
SoftConnect is a patent pending technology from Philips
Semiconductors.
recognition, parallel/serial conversion, bit stuffing/de-stuffing, CRC
checking/generation, PID verification/generation, address
recognition, and handshake evaluation/generation.
INTEGRATED
RAM
MEMORY
MANAGEMENT
UNIT
PARALLEL
AND DMA
INTERFACE
SV00859
by default. The connection is
CC
voltage specification for the connection
SE
1999 Jan 08
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Philips Semiconductors Product specification
PDIUSBD12USB interface device with parallel bus
GoodLink
Good USB connection indication is provided through GoodLink
technology . During enumeration, the LED indicator will blink ON
momentarily corresponding to the enumeration traffic. When the
PDIUSBD12 is successfully enumerated and configured, the LED
indicator will be permanently ON. Subsequent successful (with
acknowledgement) transfer to and from the PDIUSBD12 will blink
OFF the LED. During suspend, the LED will be OFF.
This feature provides a user-friendly indicator on the status of the
USB device, the connected hub and the USB traffic. It is a useful
field diagnostics tool to isolate faulty equipment. This feature helps
lower field support and hotline costs.
Memory Management Unit (MMU) and Integrated RAM
The MMU and the integrated RAM buffer the difference in speed
between USB, running in bursts of 12 Mbits/s and the parallel
interface to the microcontroller. This allows the microcontroller to
read and write USB packets at its own speed.
PDIUSBD12 80C51
INT_N
Parallel and DMA Interface
A generic parallel interface is defined for ease-of-use, speed, and
allows direct interfacing to major microcontrollers. To a
microcontroller, the PDIUSBD12 appears as a memory device with
8-bit data bus and 1 address bit (occupying 2 locations). The
PDIUSBD12 supports both multiplexed and non-multiplexed
address and data bus. The PDIUSBD12 also supports DMA (Direct
Memory Access) transfer which allows the main endpoint (endpoint
2) to directly transfer to and from the local shared memory. Both
single cycle and burst mode DMA transfers are supported.
Example of parallel interface to a dedicated 80C51
In this example, the ALE is permanently tied LOW to signify a
separate address and data bus configuration. The A0 pin of the
PDIUSBD12 connects to any of the 80C51 I/O port. This port
controls command or data phase to the PDIUSBD12. The
multiplexed address and data bus of the 80C51 can now be
connected directly to the data bus of the PDIUSBD12. The address
phase will simply be ignored by the PDIUSBD12. The crystal input
of the 80C51 can be supplied by the CLKOUT output of the
PDIUSBD12.
–INTO/P3.2
DATA [7:0]
WR_N
RD_N
CLKOUT
CS_N
ALE
A0
ANY I/O PORT (e.g. P3.3)
P [0.7:0.0]/AD [7:0]
–WR/P3.6
–RD/P3.7
XTAL1
SV00870
1999 Jan 08
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Philips Semiconductors Product specification
PDIUSBD12USB interface device with parallel bus
DMA TRANSFER
Direct Memory Address (DMA) allows an efficient transfer of a block
of data between the host and the local shared memory. Using a
DMA controller, data transfer between the PDIUSBD12 main
endpoint (endpoint 2) and the local shared memory can happen
autonomously without local CPU intervention.
Preceding any DMA transfer, the local CPU receives from the host
the necessary setup information and programs the DMA controller
accordingly. Typically, the DMA controller is setup for demand
transfer mode and the byte count register and the address counter
are programmed with the right values. In this mode, transfers occur
only when the PDIUSBD12 requests them and terminated when the
byte count register reaches zero. After the DMA controller has been
programmed, the DMA enable bit of the PDIUSBD12 is set by the
local CPU to initiate the transfer.
The PDIUSBD12 can be programmed for single cycle DMA or burst
mode DMA. In single cycle DMA, the DMREQ is deactivated for
every single acknowledgement by the DMACK_N before being
asserted again. In burst mode DMA, the DMREQ is held active for
the number of bursts programmed in the device before returning
inactive. This process continues until the PDIUSBD12 receives a
DMA termination notice through EOT_N. This will generate an
interrupt to notify the local CPU that DMA operation is completed.
For DMA read operation, the DMREQ will only be activated
whenever the buffer is full signifying that the host has successfully
transferred a packet to the PDIUSBD12. With the double buffering
scheme, the host can start filling up the second buffer while the first
buffer is being read out. This parallel processing increases effective
throughput. For the case when the host does not fill up the buffer
completely (less than 64 bytes or 128 bytes for single direction ISO
configuration), the DMREQ will be deactivated at the last byte of the
buffer regardless of the current DMA burst count. It will be asserted
again on the next packet with a refreshed DMA burst count.
Similarly , for DMA write operation, the DMREQ remains active
whenever the buffer is not full. When the buffer is filled up, the
packet is sent over to the host on the next IN token and DMREQ will
be reactivated if the transfer was successful. Also, the double
buffering scheme here will improve throughput. For non-isochronous
transfer (bulk and interrupt), the buffer needs to be completely filled
up by the DMA write operation before the data is sent to the host.
The only exception is at the end of DMA transfer when the reception
of EOT_N will stop DMA write operation and the buffer content will
be sent to the host on the next IN token.
For isochronous transfer, the local CPU and DMA controller has to
guarantee that they are able to sink or source the maximum packet
size in one USB frame (1 ms).
The assertion of DMACK_N will automatically selects the main
endpoint (endpoint 2) regardless of the current selected endpoint.
The DMA operation of the PDIUSBD12 can be interleaved with
normal I/O access to other endpoints.
DMA operation can be terminated by resetting the DMA enable
register bit or the assertion of EOT_N together with DMACK_N and
either RD_N or WR_N.
PDIUSBD12 supports DMA transfer in a single address mode and it
can also work in dual address mode of the DMA controller. In the
single address mode, DMA transfer is done via the DREQ,
DMACK_N, EOT_N, WR_N and RD_N control lines. In the dual
address mode, DMREQ, DMACK_N and EOT_N are NOT used,
instead CS_N, WR_N and RD_N control signals are used. The I/O
mode Transfer Protocol of PDIUSBD12 needs to be followed. The
source of the DMAC is accessed during the read cycle, and the
destination accessed during the write cycle. Transfer needs to be
done in two separate bus cycles, storing the data temporarily in the
DMAC.
ENDPOINT DESCRIPTION
The PDIUSBD12 endpoints are generic enough to be used by
various device classes ranging from Imaging, Printer, Mass Storage
and Communication device classes. The PDIUSBD12 endpoints can
be configured for 4 modes depending on the “Set Mode” command.
The 4 modes are:
Mode 0 (Non-ISO Mode): no Isochronous transfer
Mode 1 (ISO-OUT Mode): Isochronous output only transfer
Mode 2 (ISO-IN Mode): Isochronous input only transfer
Mode 3 (ISO-IO Mode): Isochronous input and output transfer
1999 Jan 08
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Philips Semiconductors Product specification
0
Default
1
2
0
Default
1
0
Default
1
0
Default
1
2
PDIUSBD12USB interface device with parallel bus
MODE 0 (NON-ISO MODE):
ENDPOINT
NUMBER
MODE 1 (ISO-OUT MODE):
ENDPOINT
NUMBER
2 4 Isochronous Out Isochronous OUT 128
ENDPOINT
INDEX
0 Control Out
1 Control In
2 Generic Out Generic OUT 16
3 Generic In Generic IN 16
4 Generic Out Generic OUT 64
5 Generic In Generic IN 64
ENDPOINT
INDEX
0 Control Out
1 Control In
2 Generic Out Generic OUT 16
3 Generic In Generic IN 16
TRANSFER TYPE ENDPOINT TYPE DIRECTION
OUT 16
IN 16
TRANSFER TYPE ENDPOINT TYPE DIRECTION
OUT 16
IN 16
MAX. PACKET SIZE
(BYTES)
4
4
MAX. PACKET SIZE
(BYTES)
4
MODE 2 (ISO-IN MODE):
ENDPOINT
NUMBER
2 5 Isochronous In Isochronous IN 128
ENDPOINT
INDEX
0 Control Out
1 Control In
2 Generic Out Generic OUT 16
3 Generic In Generic IN 16
TRANSFER TYPE ENDPOINT TYPE DIRECTION
OUT 16
IN 16
MAX. PACKET SIZE
(BYTES)
MODE 3 (ISO-IO MODE):
ENDPOINT
NUMBER
NOTES:
1. Generic endpoint can be used either as Bulk or Interrupt endpoint
2. The main endpoint (endpoint number 2) is double-buffered to ease synchronization with the real time applications and to increase
throughput.
3. DMA access is for the main endpoint (endpoint number 2) only.
4. Denotes double buffering. The size shown is for a single buffer.
ENDPOINT
INDEX
0 Control Out
1 Control In
2 Generic Out Generic OUT 16
3 Generic In Generic IN 16
4 Isochronous Out Isochronous OUT 64
5 Isochronous In Isochronous IN 64
TRANSFER TYPE ENDPOINT TYPE DIRECTION
OUT 16
IN 16
MAX. PACKET SIZE
(BYTES)
4
4
4
MAIN ENDPOINT
The main endpoint (endpoint number 2) is special in a few ways. It is the primary endpoint for sinking or sourcing relatively large data. As such,
it implements a host of features to ease the task of transferring large data:
1. Double buffering. This allows parallel operation between USB access and local CPU access thus increasing throughput. Buffer switching is
handled automatically. This results in transparent buffer operation.
2. Supports for DMA (Direct Memory Access) operation. This can be interleaved with normal I/O operation to other endpoints.
3. Automatic pointer handling during DMA operation. No local CPU intervention is necessary when ‘crossing’ the buffer boundary.
4. Configurable for either isochronous transfer or non-isochronous (bulk and interrupt) transfer.
1999 Jan 08
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Philips Semiconductors Product specification
PDIUSBD12USB interface device with parallel bus
PINNING
Pin configuration
A0
28DATA<0>
V
27
26
D+
25
D–
24
V
23
XTAL2
22
XTAL1
21
GL_N
20
RESET_N
19
EOT_N
18
DMACK_N
DMREQSUSPEND
SV01019
OUT3.3
DD
DATA<1>
DATA<2>
DATA<3>
GND
DATA<4>
DATA<5>
DATA<6>
DATA<7>
ALE
CS_N
1
2
3
4
5
6
7
8
9
10
11
12 17
13 16 WR_NCLKOUT
14 15 RD_NINT_N
Pin Description
PIN SYMBOL TYPE DESCRIPTION
1 DATA <0> IO2 Bit 0 of bi-directional data.
2 DATA <1> IO2 Bit 1 of bi-directional data.
3 DATA <2> IO2 Bit 2 of bi-directional data.
4 DATA <3> IO2 Bit 3 of bi-directional data.
5 GND P Ground.
6 DATA <4> IO2 Bit 4 of bi-directional data.
7 DATA <5> IO2 Bit 5 of bi-directional data.
8 DATA <6> IO2 Bit 6 of bi-directional data.
9 DATA <7> IO2 Bit 7 of bi-directional data.
10 ALE I
11 CS_N I Chip Select (Active Low).
12 SUSPEND I,OD4 Device is in Suspend state.
13 CLKOUT O2 Programmable Output Clock
14 INT_N OD4 Interrupt (Active Low).
NOTE:
1. O2 : Output with 2 mA drive
OD4 : Output Open Drain with 4 mA drive
OD8 : Output Open Drain with 8 mA drive
IO2 : Input and Output with 2 mA drive
O4 : Output with 4mA drive
Slew-rate controlled.
Slew-rate controlled.
Slew-rate controlled.
Slew-rate controlled.
Slew-rate controlled.
Slew-rate controlled.
Slew-rate controlled.
Slew-rate controlled.
Address Latch Enable. The falling
edge is used to close the latch of the
address information in a multiplexed
address/ data bus. Permanently tied
low for separate address/ data bus
configuration.
(slew-rate controlled).
SYMBOL TYPE DESCRIPTION
PIN
15 RD_N I Read Strobe (Active Low).
16 WR_N I Write Strobe (Active Low).
17 DMREQ O4 DMA Request.
18 DMACK_N I DMA Acknowledge (Active Low).
End of DMA Transfer (Active Low).
Double up as Vbus sensing. EOT_N
19 EOT_N I
is only valid when asserted together
with DMACK_N and either RD_N or
WR_N.
20 RESET_N I Reset (Active Low and asynchronous).
Built-in Power-On-Reset circuit
present on chip, so pin can be tied
HIGH to V
CC
.
21 GL_N OD8 GoodLink LED indicator (Active Low)
22 XTAL1 I Crystal Connection 1 (6 MHz)
23 XTAL2 O Crystal Connection 2 (6 MHz). If
external clock signal, instead of
crystal, is connected to XTAL1, then
XTAL2 should be floated.
24 V
CC
P Voltage supply (4.0 – 5.5V).
To operate the IC at 3.3V, supply
3.3V to both V
CC
and V
OUT3.3
pins.
25 D– A USB D– data line
26 D+ A USB D+ data line
27 V
OUT3.3
P 3.3V regulated output. T o operate
the IC at 3.3V , supply a 3.3V to both
V
CC
and V
OUT3.3
pins
Address bit. A0=1 selects command
instruction; A0=0 selects the data
28 A0 I
phase. This bit is a don’t care in a
multiplexed address and data bus
configuration and should be tied high.
1999 Jan 08
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