Philips PDI1394P21 Datasheet
INTEGRATED CIRCUITS
PDI1394P21
3-port physical layer interface
Objective specification 1999 Jul 09
Philips Semiconductors Objective specification
PDI1394P213-port physical layer interface
1.0 FEATURES
•Fully supports provisions of IEEE 1394–1995 Standard for high
performance serial bus and the P1394a supplement (Version 2.0)
•Full P1394a support includes:
– Connection debounce
– Arbitrated short reset
– Multispeed concatenation
– Arbitration acceleration
– Fly-by concatenation
– Port disable/suspend/resume
•Provides three 1394a fully-compliant cable ports at
100/200/400 Megabits per second (Mbits/s)
•Fully compliant with Open HCI requirements
•Cable ports monitor line conditions for active connection to remote
node.
•Power down features to conserve energy in battery-powered
applications include:
– Automatic device power down during suspend
– Device power down terminal
– Link interface disable via LPS
– Inactive ports powered-down
•Logic performs system initialization and arbitration functions
•Encode and decode functions included for data-strobe bit level
encoding
•Incoming data resynchronized to local clock
•Single 3.3 volt supply operation
•Minimum V
of 2.7 V for end-of-wire power-consuming devices
DD
•While unpowered and connected to the bus, will not drive TPBIAS
on a connected port, even if receiving incoming bias voltage on
that port
•Supports extended bias-handshake time for enhanced
interoperability with camcorders
•Interface to link-layer controller supports low-cost bus-holder
1
isolation and optional Annex J electrical isolation
•Data interface to link-layer controller through 2/4/8 parallel lines at
49.152 MHz
•Low-cost 24.576 MHz crystal provides transmit, receive data at
100/200/400 Mbits/s, and link-layer controller clock at 49.152 MHz
•Does not require external filter capacitors for PLL
•Interoperable with link-layer controllers using 3.3 V and 5 V
supplies
•Interoperable with other Physical Layers (PHYs) using 3.3 V and
5 V supplies
•Node power class information signaling for system power
management
•Cable power presence monitoring
•Separate cable bias (TPBIAS) for each port
•Register bits give software control of contender bit, power class
bits, link active bit, and 1394a features
•Fully interoperable with FireWire implementation of IEEE Std 1394
•Function and pin compatible with the Texas Instruments 400 Mbps
Phy TSB41LV03
2.0 DESCRIPTION
The PDI1394P21 provides the digital and analog transceiver functions
needed to implement a three port node in a cable-based IEEE
1394–1995 and/or 1394a network. Each cable port incorporates two
differential line transceivers. The transceivers include circuitry to
monitor the line conditions as needed for determining connection
status, for initialization and arbitration, and for packet reception and
transmission. The PDI1394P21 is designed to interface with a Link
Layer Controller (LLC), such as the PDI1394L11 or PDI1394L21.
3.0 ORDERING INFORMATION
PACKAGE TEMPERATURE RANGE OUTSIDE NORTH AMERICA NORTH AMERICA PKG. DWG. #
80-pin plastic LQFP 0°C to +70°C PDI1394P21 BE PDI1394P21 BE SOT315-1
1. Implements technology covered by one or more patents of Apple Computer, Incorporated and SGS Thompson, Limited.
1999 Jul 09
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Philips Semiconductors Objective specification
PDI1394P213-port physical layer interface
4.0 PIN CONFIGURATION
XI
LREQ
SYSCLK
DGND
CTL0
CTL1
DVDD
NC
D5
D6
DGND
CNA
PD
LPS
DGND
/RESET
DVDD
DGND
1
2
3
4
5
6
7
D0
8
D1
9
10
D2
11
D3
12
D4
13
14
15
D7
16
17
18
19
20
DGND
XO
78 77 76 75 74 73 72 71 7080 79 69 68 67 66 65
23 24 25 26 27 28 29
PC1
PC0
C/LKON
PC2
PLLGND
PLLGND
/ISO
CPS
PLLVDD
NC
NC
PDI1394P21
30 3121 22
DVDD
DVDD
DGND
DVDD
DGND
DVDD
32 33 34 35 36
NC
TEST1
TEST0
R1
AVDD
R0
AVDD
AGND
AGND
AGND
AVDD
AVDD
64 63 62 61
37 38 39 40
AGND
AGND
AGND
AGND
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
AGND
SV001742
AGND
TPBIAS2
TPA2+
TPA2–
TPB2+
TPB2–
AVDD
TPBIAS1
TPA1+
TPA1–
TPB1+
TPB1–
AVDD
AVDD
TPBIAS0
TPA0+
TPA0–
TPB0+
TPB0–
AGND
5.0 PIN DESCRIPTION
Name Pin Type Pin Numbers I/O Description
AGND Supply 36, 37, 38, 39, 40,
41, 60, 61, 64, 65
AVDD Supply 34, 35, 47, 48, 54,
62, 63
CNA CMOS 17 O Cable Not Active output. This terminal is asserted high when there are
CPS CMOS 27 I Cable Power Status input. This terminal is normally connected to cable
CTL0,
CMOS 5V tol 4, 5 I/O Control I/Os. These bi-directional signals control communication
CTL1
1999 Jul 09
— Analog circuit ground terminals. These terminals should be tied together
to the low impedance circuit board ground plane.
— Analog circuit power terminals. A combination of high frequency
decoupling capacitors near each terminal are suggested, such as
paralleled 0.1 µF and 0.001 µF. Lower frequency 10 µF filtering
capacitors are also recommended. These supply terminals are
separated from PLL VDD and DVDD internal to the device to provide
noise isolation. They should be tied at a low impedance point on the
circuit board.
no ports receiving incoming bias voltage.
power through a 370–410 kΩ resistor. This circuit drives an internal
comparator that is used to detect the presence of cable power.
between the PDI1394P21 and the LLC. Bus holders are built into
these terminals.
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Philips Semiconductors Objective specification
PDI1394P213-port physical layer interface
Name DescriptionI/OPin NumbersPin Type
C/LKON CMOS 5V tol 22 I/O Bus Manager Contender programming input and link-on output. On
DGND Supply 3, 16, 20, 21, 28,
D0–D7 CMOS 5V tol 7, 8, 10, 11, 12, 13,
DVDD Supply 6, 29, 30, 68, 69, 79 — Digital circuit power terminals. A combination of high frequency
/ISO CMOS 26 I Link interface isolation control input. This terminal controls the operation
LPS CMOS 5V tol 19 I Link Power Status input. This terminal is used to monitor the power
LREQ CMOS 5V tol 1 I LLC Request input. The LLC uses this input to initiate a service request
NC No Connect 9, 31, 71, 72 — These pins are not internally connected, and consequently are “don’t
PC0, PC1,
PC2
PD CMOS 5V tol 18 I Power Down input. A logic high on this terminal turns off all internal
PLLGND Supply 74, 75 — PLL circuit ground terminals. These terminals should be tied together to
PLLVDD Supply 73 — PLL circuit power terminals. A combination of high frequency decoupling
CMOS 5V tol 23, 24, 25 I Power Class programming inputs. On hardware reset, these inputs set
70, 80
14, 15
— Digital circuit ground terminals. These terminals should be tied together
I/O Data I/Os. These are bi-directional data signals between the
hardware reset, this terminal is used to set the default value of the
contender status indicated during self-ID. Programming is done by tying
the terminal through a 10kΩ resistor to a high (contender) or low (not
contender). The resistor allows the link-on output to override the input.
Following hardware reset, this terminal is the link-on output, which is
used to notify the LLC to power-up and become active. The link-on
output is a square-wave signal with a period of approximately 163 ns (8
SYSCLK cycles) when active. The link-on output is deasserted low when
the LPS input terminal is active.
to the low impedance circuit board ground plane.
PDI1394P21 and the LLC. Bus holders are built into these terminals.
decoupling capacitors near each terminal are suggested, such as
paralleled 0.1 µF and 0.001 µF. Lower frequency 10 µF filtering
capacitors are also recommended. These supply terminals are
separated from PLL VDD and AVDD internal to the device to provide
noise isolation. They should be tied at a low impedance point on the
circuit board.
of output differentiation logic on the CTL and D terminals. If an optional
isolation barrier of the type described in Annex J of IEEE Std 1394–1395
is implemented between the PDI1394P21 and LLC, the /ISO terminal
should be tied low to enable the differentiation logic. If no isolation barrier
is implemented (direct connection), or bus holder isolation is
implemented, the /ISO terminal should be tied high to disable the
differentiation logic.
status of the LLC, and is connected to either the VDD supplying the link
layer controller through a 1kΩ resistor, or to a pulsed output which is
active when the LLC is powered. The pulsed output is useful when using
an isolation barrier. If this input is low for more than 25 ms, the LLC is
considered powered down. If this input is high for more than 20 ns, the
LLC is considered powered up. If the LLC is powered-down, the
PHY–LLC interface is disabled, and the PDI1394P21 performs only the
basic repeater functions required for network initialization and operation.
Bus holder is built into this terminal.
to the PDI1394P21. Bus holder is built into this terminal.
cares”. Other vendor’s pin compatible chips may require connections
and external circuitry on these pins.
the default value of the power class indicated during self-ID.
Programming is done by tying the terminals high or low. Refer to
Table 18 for encoding.
circuitry except the cable-active monitor circuits which control the CNA
output. Bus holder is built into this terminal. For more information, refer to
Section 17.3
the low impedance circuit board ground plane.
capacitors near each terminal are suggested, such as paralleled 0.1 µF
and 0.001 µF. Lower frequency 10 µF filtering capacitors are also
recommended. These supply terminals are separated from DVDD and
AVDD internal to the device to provide noise isolation. They should be
tied at a low impedance point on the circuit board.
1999 Jul 09
4
Philips Semiconductors Objective specification
gg
gg
PDI1394P213-port physical layer interface
Name DescriptionI/OPin NumbersPin Type
/RESET CMOS 5V tol 78 I Logic reset input. Asserting this terminal low resets the internal logic. An
R0, R1 Bias 66, 67 — Current setting resistor terminals. These terminals are connected to
SYSCLK CMOS 2 O System clock output. Provides a 49.152 MHz clock signal, synchronized
TEST0 CMOS 33 I Test control input. This input is used in manufacturing tests of the
TEST1 CMOS 32 I Test control input. This input is used in manufacturing tests of the
TPA0+,
TPA1+,
TPA2+
TPA0–,
TPA1–,
TPA2–
TPB0+,
TPB1+,
TPB2+
TPB0–,
TPB1–,
TPB2–
TPBIAS0,
TPBIAS1,
TPBIAS2
XO, XI Crystal 77, 76 — Crystal oscillator inputs. These terminals connect to a 24.576 MHz
Cable 45, 52, 58 I/O
Cable 44, 51, 57 I/O
Cable 43, 50, 56 I/O
Cable 42, 49, 55 I/O
Cable 46, 53, 59 I/O Twisted-pair bias output. This provides the 1.86V nominal bias voltage
internal pull-up resistor to VDD is provided so only an external
delay capacitor in parallel with a resistor is required for proper power-up
operation. For more information, refer to Section 17.3. This input is
otherwise a standard logic input, and can also be driven by an
open-drain type driver.
an external resistance to set the internal operating currents and
cable driver output currents. A resistance of 6.34 kΩ ±1% is required to
meet the IEEE Std 1394–1995 output voltage limits.
with data transfers, to the LLC.
PDI1394P21. For normal use, this terminal should be tied to GND.
PDI1394P21. For normal use, this terminal should be tied to GND.
Twisted-pair cable A differential signal terminals. Board traces from each
pair of positive and negative differential signal terminals should be kept
matched and as short as possible to the external load resistors and to
the cable connector.
Twisted-pair cable B differential signal terminals. Board traces from each
pair of positive and negative differential signal terminals should be kept
matched and as short as possible to the external load resistors and to
the cable connector.
needed for proper operation of the twisted-pair cable drivers and
receivers, and for signaling to the remote nodes that there is an active
cable connection. Each of these terminals must be decoupled with a
0.3 µF–1 µF capacitor to ground.
parallel resonant fundamental mode crystal. The optimum values for the
external shunt capacitors are dependent on the specifications of the
crystal used. Can also be driven by an external clock generator (leave
XO unconnected in this case).
1999 Jul 09
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Philips Semiconductors Objective specification
PDI1394P213-port physical layer interface
6.0 BLOCK DIAGRAM
CPS
LPS
/ISO
C/LKON
SYSCLK
LREQ
CTL0
CTL1
PC0
PC1
PC2
CNA
TPBIAS0
TPBIAS1
TPBIAS2
PD
/RESET
LINK
INTERFACE
D0
D1
D2
D3
D4
D5
D6
D7
R0
R1
I/O
RECEIVED DATA
DECODER/
RETIMER
ARBITRATION
AND CONTROL
STATE MACHINE
LOGIC
BIAS VOLTAGE
AND
CURRENT
GENERATOR
TRANSMIT
DATA
ENCODER
CABLE POWER
DETECTOR
CABLE PORT 0
CABLE PORT 1
CABLE PORT 2
CRYSTAL
OSCILLATOR,
PLL SYSTEM,
AND CLOCK
GENERATOR
CPS
TPA0+
TPA0–
TPB0+
TPB0–
TPA1+
TPA1–
TPB1+
TPB1–
TPA2+
TPA2–
TPB2+
TPB2–
XI
XO
SV01743
7.0 FUNCTIONAL SPECIFICA TION
The PDI1394P21 requires only an external 24.576 MHz crystal as a
reference. An external clock can be provided instead of a crystal. An
internal oscillator drives an internal phase-locked loop (PLL), which
generates the required 393.216 MHz reference signal. This
reference signal is internally divided to provide the clock signals
used to control transmission of the outbound encoded Strobe and
Data information. A 49.152 MHz clock signal, supplied to the
associated LLC for synchronization of the two chips, is used for
resynchronization of the received data. The Power Down (PD)
function, when enabled by asserting the PD terminal high, stops
operation of the PLL and disables all circuits except the cable bias
detectors at the TPB terminals. The port transmitter circuitry and the
receiver circuitry are also disabled when the port is disabled,
suspended, or disconnected.
The PDI1394P21 supports an optional isolation barrier between
itself and its LLC. When the /ISO input terminal is tied high, the
LLC interface outputs behave normally. When the /ISO terminal is
tied low, internal differentiating logic is enabled, and the outputs are
driven such that they can be coupled through a capacitive or
transformer galvanic isolation barrier as described in
1999 Jul 09
IEEE 1394a
section 5.9.4
. To operate with single capacitor (bus holder) isolation,
the /ISO on the PHY terminal must be tied high.
Data bits to be transmitted through the cable ports are received from
the LLC on two, four or eight parallel paths (depending on the
requested transmission speed). They are latched internally in the
PDI1394P21 in synchronization with the 49.152 MHz system clock.
These bits are combined serially, encoded, and transmitted at
98.304/196.608/392.216 Mbits/s (referred to as S100, S200, and
S400 speed, respectively) as the outbound data-strobe information
stream. During transmission, the encoded data information is
transmitted differentially on the TPB cable pair(s), and the encoded
strobe information is transmitted differentially on the TP A cable
pair(s).
During packet reception the TPA and TPB transmitters of the
receiving cable port are disabled, and the receivers for that port are
enabled. The encoded data information is received on the TPA cable
pair, and the encoded strobe information is received on the TPB
cable pair. The received data-strobe information is decoded to
recover the receive clock signal and the serial data bits. The serial
6
Philips Semiconductors Objective specification
PDI1394P213-port physical layer interface
data bits are split into two-, four- or eight-bit parallel streams
(depending upon the indicated receive speed), resynchronized to
the local 49.152 MHz system clock and sent to the associated LLC.
The received data is also transmitted (repeated) on the other active
(connected) cable ports.
Both the TPA and TPB cable interfaces incorporate dif ferential
comparators to monitor the line states during initialization and
arbitration. The outputs of these comparators are used by the
internal logic to determine the arbitration status. The TPA channel
monitors the incoming cable common-mode voltage. The value of
this common-mode voltage is used during arbitration to set the
speed of the next packet transmission (speed signalling). In addition,
the TPB channel monitors the incoming cable common-mode
voltage on the TPB pair for the presence of the remotely supplied
twisted-pair bias voltage (cable bias detection).
The PDI1394P21 provides a 1.86 V nominal bias voltage at the
TPBIAS terminal for port termination. the PHY contains three
independent TPBIAS circuits. This bias voltage, when seen through
a cable by a remote receiver, indicates the presence of an active
connection. This bias voltage source must be stabilized by an
external filter capacitor of 0.3 µF–1 µF.
The line drivers in the PDI1394P21 operate in a high-impedance
current mode, and are designed to work with external 112 Ω
line-termination resistor networks in order to match the 110 Ω cable
impedance. One network is provided at each end of all twisted-pair
cable. Each network is composed of a pair of series-connected 56 Ω
resistors. The midpoint of the pair of resistors that is directly
connected to the twisted-pair A terminals is connected to its
corresponding TPBIAS voltage terminal. The midpoint of the pair of
resistors that is directly connected to the twisted-pair B terminals is
coupled to ground through a parallel R-C network with recommended
values of 5 kΩ and 220 pF. The values of the external line termination
resistors are designed to meet the standard specifications when
connected in parallel with the internal receiver circuits. An external
resistor connected between the R0 and R1 terminals sets the driver
output current, along with other internal operating currents. This
current setting resistor has a value of 6.34 kΩ ±1%.
When the power supply of the PDI1394P21 is removed while the
twisted-pair cables are connected, the PDI1394P21 transmitter and
receiver circuitry presents a high impedance to the cable in order to
not load the TPBIAS voltage on the other end of the cable.
When the PDI1394P21 is used with one or more of the ports not
brought out to a connector, the twisted-pair terminals of the unused
ports must be terminated for reliable operation. For each unused
port, the TPB+ and TPB– terminals can be tied together and then
pulled to ground, or the TPB+ and TPB– terminals can be connected
to the suggested termination network. The TPA+ and TPA– and
TPBIAS terminals of an unused port can be left unconnected.
The TEST0 and TEST1 terminals are used to set up various
manufacturing test conditions. For normal operation, the TEST0 and
TEST1 terminals should be connected to ground.
Four package terminals, used as inputs to set the default value for
four configuration status bits in the self-ID packet, should be
hard-wired high or low as a function of the equipment design. The
PC0–PC2 terminals are used to indicate the default power-class
status for the node (the need for power from the cable or the ability
to supply power to the cable). See Table 18 for power class
encoding. The C/LKON terminal is used as an input to indicate that
the node is a contender for bus manager.
The PHY supports suspend/resume as defined in the IEEE 1394a
specification. The suspend mechanism allows pairs of directly
connected ports to be placed into a low power state while
maintaining a port-to-port connection between 1394 bus segments.
While in a low power state, a port is unable to transmit or receive
data transaction packets. However, a port in a low power state is
capable of detecting connection status changes and detecting
incoming TPBIAS. When all three ports of the PDI1394P21 are
suspended, all circuits except the bias-detection circuits are
powered down, resulting in significant power savings. The TPBIAS
circuit monitors the value of incoming TPA pair common-mode
voltage when local TPBIAS is inactive. Because this circuit has an
internal current source and the connected node has a current sink,
the monitored value indicates the cable connection status. This
monitor is called connect-detect.
Both the cable bias-detect monitor and TPBIAS connect-detect
monitor are used in suspend/resume signaling and cable connection
detection. For additional details of suspend/resume operation, refer
to the 1394a specification. The use of suspend/resume is
recommended for new designs.
The port transmitter and receiver circuitry is disabled during power
down (when the PD input terminal is asserted high), during reset
(when the /RESET input terminal is asserted low), when no active
cable is connected to the port, or when controlled by the internal
arbitration logic. The port twisted-pair bias voltage circuitry is
disabled during power down, during reset, or when the port is
disabled as commanded by the LLC.
The CNA (cable-not-active) terminal provides a high output when all
twisted-pair cable ports are disconnected, and can be used along
with LPS to determine when to power down the PDI1394P21. The
CNA output is not debounced. In Power Down mode, the CNA
detection circuitry remains enabled.
The LPS (link power status) terminal works with the C/LKON
terminal to manage the power usage in the node. The LPS signal
from the LLC indicates to the PHY that the LLC is powered up and
active. During LLC Power Down mode, as indicated by the LPS
input being low for more than 25 µs, the PDI1394P21 deactivates
the PHY -LLC interface to save power. The PDI1394P21 continues
the necessary repeater function required for network operation
during this low power state.
If the PHY receives a link-on packet from another node, the C/LKON
terminal is activated to output a square-wave signal. The LLC
recognizes this signal, reactivates any powered-down portions of the
LLC, and notifies the PHY of its power-on status via the LPS
terminal. The PHY confirms notification by deactivating the
square-wave signal on the C/LKON terminal, then enables the
PHY -link interface.
1999 Jul 09
7
Philips Semiconductors Objective specification
SYMBOL
PARAMETER
CONDITION
UNIT
Electrostatic discharge
SYMBOL
PARAMETER
MIN
TYP
MAX
UNIT
VDDSuppl
oltage
V
gg,
VIDDifferential input voltage amplitude
V
TPB common-mode input voltage
gg
V
TPB common-mode input voltage
S200 speed signal
V
TPB common-mode input voltage
S400 speed signal
PDI1394P213-port physical layer interface
8.0 ABSOLUTE MAXIMUM RATINGS
1
In accordance with the Absolute Maximum Rating System (IEC 134). Voltages are referenced to GND (ground = 0 V).
LIMITS
MIN MAX
V
DC supply voltage –0.5 4.0 V
DD
V
DC input voltage –0.5 VDD+0.5 V
I
VI–5V 5 volt tolerant input voltage range –0.5 5.5 V
V
DC output voltage range at any output –0.5 VDD+0.5 V
O
Human Body Model 2 kV
Machine Model 200 V
T
amb
T
Operating free-air temperature range 0 +70 °C
Storage temperature range –65 +150 °C
stg
NOTE:
1. Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under “Recommended Operating
Conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability .
9.0 RECOMMENDED OPERATING CONDITIONS
pp
y v
V
IOH/I
IC-100
IC-200
IC-100
t
High-level input voltage, pins
IH
CTLn, Dn, C/LKON
Low-level input voltage, pins
IL
CTLn, Dn, C/LKON
Output current, pins CTLn, Dn,
OL
C/LKON and SYSCLK
I
Output current TPBIAS outputs –6 2.5 mA
O
Power–up reset time Set by capacitor between /RESET pin and GND 2 ms
PU
2
2
p
p
p
p
p
Receive input jitter
Receive input skew
f
XTAL
Crystal or external clock frequency
NOTES:
1. For a node that does not source power to the bus (see Section 4.2.2.2 in the IEEE 1394-1995 standard).
2. C/LKON is only an input when /RESET = 0.
Source power node 3.0 3.3 3.6 V
Non-source power node 2.7
1
3.0 3.6 V
/ISO = VDD, VDD = 2.7 V 2.3 5.5 V
/ISO = VDD, VDD >= 3.0 V 2.6 5.5 V
/ISO = V
DD
0.7 V
VOH = VDD –0.5 V, VOL = 0.5 V –12 12 mA
TPA, TPB cable inputs, during data reception 118 260 mV
TPA, TPB cable inputs, during data arbitration 168 265 mV
Speed signalling off
or S100 speed signal
p
p
Source power node 1.165 2.515 V
Non-source power node 1.165 2.015
1
Source power node 0.935 2.515 V
Non-source power node 0.935 2.015
1
Source power node 0.523 2.515 V
Non-source power node 0.523 2.015
1
TPA, TPB cable inputs, S100 operation 1.08 ns
TPA, TPB cable inputs, S200 operation 0.5 ns
TPA, TPB cable inputs, S400 operation 0.315 ns
Between TPA and TPB cable inputs, S00 operation 0.8 ns
Between TPA and TPB cable inputs, S200 operation 0.55 ns
Between TPA and TPB cable inputs, S400 operation 0.5 ns
Crystal connected according to Figure 8 or external
clock input at pin XI
24.5735 24.576 24.5785 MHz
V
V
V
1999 Jul 09
8
Philips Semiconductors Objective specification
SYMBOL
PARAMETER
TEST CONDITION
UNIT
2
SYMBOL
PARAMETER
TEST CONDITION
UNIT
Z
Differential input impedance
Drivers disabled
Z
Common mode input impedance
Drivers disabled
PDI1394P213-port physical layer interface
10.0 CABLE DRIVER
LIMITS
MIN TYP MAX
V
I
O(diff)
I
V
OFF
NOTES:
1. Limits defined as algebraic sum of TPA+ and TPA– driver currents. Limits also apply to TPB+ and TPB– algebraic sum of driver currents.
2. Limits defined as absolute limit of each of TPB+ and TPB– driver currents.
11.0 CABLE RECEIVER
V
V
V
V
V
TH–SP200
V
TH–SP400
Differential output voltage 56 Ω load 172 265 mV
OD
Driver Difference current, TP A+, TPA–, TPB+, TPB–
Drivers enabled,
1
speed signaling OFF
–1.05
1
100 Mbit/s speed signaling enabled –0.81 –0.44 mA
Common mode speed signaling current, TPB+, TPB–
SP
200 Mbit/s speed signaling enabled –4.84 –2.53 mA
400 Mbit/s speed signaling enabled –12.4 –8.10 mA
OFF state differential voltage Drivers disabled 20 mV
LIMITS
MIN TYP MAX
ID
IC
TH-R
TH-CB
TH+
TH–
I
CD
p
p
p
p
Receiver input threshold voltage Drivers disabled –30 30 mV
Cable bias detect threshold, TPBn cable inputs Drivers disabled 0.6 1.0 V
Positive arbitration comparator threshold voltage Drivers disabled 89 168 mV
Negative arbitration comparator threshold voltage Drivers disabled –168 –89 mV
Speed signal threshold
Speed signal threshold
TPBIAS–TPA common mode
voltage, drivers disabled
TPBIAS–TPA common mode
voltage, drivers disabled
Connect detect output at TPBIAS pins Drivers disabled 76 µA
10 14
20 kΩ
49 131 mV
314 396 mV
1
0.88
4 pF
24 pF
mA
kΩ
1999 Jul 09
9
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