INTEGRATED CIRCUITS
PDI1284P11
3.3V Parallel interface transceiver/buffer
Product specification |
1999 Sep 17 |
Supersedes data of 1997 Sep 15 |
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P s
on o s
Philips Semiconductors |
Product specification |
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3.3V Parallel interface transceiver/buffer |
PDI1284P11 |
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FEATURES
•Asynchronous operation
•8-Bit transceivers
•6 additional buffer/driver lines peripheral to cable
•5 additional control lines from cable
•5V tolerant
•ESD protection exceeds 2000V per MIL STD 883 Method 3015 and 200V per Machine Model
•Latch up protection exceeds 500 mA per JEDEC Std 19
•Input Hysteresis
•Low Noise Operation
•IEEE 1284 Compliant Level 1 & 2
•Overvoltage Protection on B/Y side for OFF-state
•A side 3-State option
•B side active or resistive pull up option
•Cable side VCC for 5V or 3V operation
DESCRIPTION
The PDI1284P11 parallel interface chip is designed to provide an asynchronous, 8-bit, bi-directional, parallel interface for personal computers. The part includes all 19 signal lines defined by the IEEE1284 interface specification for Byte, Nibble, EPP, and ECP modes. The part is designed for hosts or peripherals operating at
3.3V to interface 3.3V or 5.0V devices.
The 8 transceiver pairs (A/B 1-8) allow data transmission from the A bus to the B bus, or from the B bus to the A bus, depending on the state of the direction pin DIR.
The B bus and the Y9-Y13 lines have either totem pole or resistor pull up outputs, depending on the state of the high drive enable pin HD. The A bus has only totem pole style outputs. All inputs are TTL compatible with at least 400mV of input hysteresis at VCC = 3.3V.
QUICK REFERENCE DATA
SYMBOL |
PARAMETER |
CONDITIONS |
TYPICAL |
UNIT |
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Tamb = 25°C; GND = 0V |
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RD |
B/Y Side output resistance |
VCC = 3.3V; VO = 1.65V ±0.2V (See Figure 2) |
45 |
Ω |
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RPU |
B/Y side pull up resistance |
VCC = 3.3V; Outputs, resistive pull up |
1.4K |
Ω |
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SR |
B/Y Side slew rate |
RL = 62Ω; CL = 50pF (See Waveform 4) |
0.2 |
V/ns |
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ICC |
Total static current |
VI = VCC/GND; IO = 0 |
5 |
μA |
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VHYS |
Input hysteresis |
VCC= 3.3V |
0.47 |
V |
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tPLH/tPHL |
Propagation delay |
VCC = 3.3V |
12.5/13.9 |
ns |
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A ±B/Y |
to the B/Y side outputs |
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ORDERING INFORMATION
PACKAGES |
TEMPERATURE RANGE |
ORDER CODE |
DRAWING NUMBER |
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48-pin plastic SSOP Type II |
0°C to +70°C |
PDI1284P11 DL |
SOT370-1 |
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48-pin plastic TSSOP Type II |
0°C to +70°C |
PDI1284P11 DGG |
SOT362-1 |
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1999 Sep 17 |
2 |
853±2036 22356 |
Philips Semiconductors |
Product specification |
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3.3V Parallel interface transceiver/buffer |
PDI1284P11 |
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PIN CONFIGURATION |
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PIN DESCRIPTION |
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DIR |
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PIN NUMBER |
SYMBOL |
FUNCTION |
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HD |
1 |
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48 |
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8, 9, 11, 12, 13, |
A1 - A8 |
Data inputs/outputs |
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14, 16, 17 |
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A9 |
2 |
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47 |
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Y9 |
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41, 40, 38, 37, |
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IEEE 1284 Std. |
A10 |
3 |
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46 |
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Y10 |
B1 - B8 |
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Y11 |
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36, 35, 33, 32 |
outputs/inputs |
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A11 |
4 |
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45 |
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2, 3, 4, 5, 6 |
A9 - A13 |
Data inputs |
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A12 |
5 |
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44 |
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Y12 |
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Y13 |
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47, 46, 45, 44, 43 |
Y9 - Y3 |
IEEE 1284 Std. outputs |
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A13 |
6 |
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43 |
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VCCB |
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29, 28, 27, 26 |
C14 - C17 |
Control inputs (cable) |
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VCC |
7 |
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42 |
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20, 21, 22, 23 |
A19 - A17 |
Control outputs |
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A1 |
8 |
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41 |
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B1 |
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(peripheral) |
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A2 |
9 |
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40 |
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B2 |
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1 |
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HD |
B/Y±side high drive |
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GND |
10 |
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39 |
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GND |
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enable/disable |
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A3 |
11 |
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38 |
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B3 |
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48 |
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DIR |
Direction selection |
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A to B / B to A |
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A4 |
12 |
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37 |
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B4 |
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19 |
PLHI |
Peripheral logic high input |
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A5 |
13 |
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36 |
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B5 |
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(peripheral) |
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A6 |
14 |
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35 |
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B6 |
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30 |
PLHO |
Peripheral logic high |
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GND |
15 |
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34 |
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OEA |
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output (cable) |
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A7 |
16 |
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33 |
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B7 |
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25 |
HLHI |
Host logic high input |
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(cable) |
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A8 |
17 |
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32 |
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B8 |
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24 |
HLHO |
Host logic high output |
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VCC |
18 |
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31 |
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VCCB |
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(cable) |
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PLHI |
19 |
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30 |
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PLHO |
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10, 15, 39 |
GND |
Ground (0V) |
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A14 |
20 |
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29 |
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C14 |
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7, 18 |
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VCC |
Positive supply voltage |
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A15 |
21 |
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28 |
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C15 |
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31, 42 |
VCCB |
Cable side power supply |
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A16 |
22 |
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27 |
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C16 |
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voltage 3V/5V |
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A17 |
23 |
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26 |
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C17 |
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34 |
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OEA |
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A side output enable |
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HLHO |
24 |
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25 |
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HLHI |
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SV00496 |
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1999 Sep 17 |
3 |
Philips Semiconductors |
Product specification |
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3.3V Parallel interface transceiver/buffer |
PDI1284P11 |
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LOGIC SYMBOL
HD |
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HD |
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CNTL |
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A9 |
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HD |
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HD
A10
HD
A11
HD
A12
HD
A13
HD
A1
CNTL
HD
A2
CNTL
HD
A3
CNTL
HD
A4
CNTL
HD
A5
CNTL
HD
A6
CNTL
HD
A7
CNTL
HD
A8
CNTL
HD
PLHI
A14
A15
A16
A17
HLHO
PERIPHERAL
SIDE
DIR
OEA
Y9
Y10
Y11
Y12
Y13
B1
B2
B3
B4
B5
B6
B7
B8
PLHO
C14
C15
C16
C17
HLHI
CABLE
SIDE
SV00136
FUNCTION TABLE
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OUTPUT |
DIR |
OEA |
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HD |
INPUTS |
OUTPUTS |
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TYPES |
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X |
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X |
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X |
C14-17 |
A14-17 |
tP |
X |
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X |
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X |
HLHI |
HLHO |
tP |
X |
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X |
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L |
A9-13 |
Y9-13 |
rP |
X |
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X |
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H |
A9-13 |
Y9-13 |
tP |
X |
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X |
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L |
PLHI |
PLHO |
O.C. |
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X |
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X |
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H |
PLHI |
PLHO |
tP |
H |
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X |
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L |
A1-8 |
B1-8 |
rP |
H |
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X |
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H |
A1-8 |
B1-8 |
tP |
L |
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L |
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X |
B1-8 |
A1-8 |
tP |
L |
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H |
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X |
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A1-8 |
Z* |
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L |
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H |
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X |
B1-8 |
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rP* |
A= Side driving internal IC
B= Side driving external cable (bidirectional)
C= Side receiving control signals from internal cable
Y= Side driving external cable (unidirectional)
X= Don't care ± control signals in
Z= High Z or 3-State
O.C.= |
Open collector |
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tP |
= |
Totem pole output |
rP |
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Resistive pull up: 1.4kΩ (nominal) on B/Y/C cable side and |
VCC. However, while a B/Y side output is Low as driven by a
Low signal on the A side, that particular B/Y side resistor is switched out to stop current drain from VCC through it.
*When DIR = L and OEA = H, the output signal is isolated from the input signal. B1 ± 8 signals maintain an rP = 1.4kΩ on the input for this mode.
PINS WITH PULL UP RESISTORS TO LOAD CABLE
PINS |
SYMBOL |
FUNCTION |
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47, 46, 45, 44, 43 |
Y9 |
± Y13 |
Output cable drivers |
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41, 40, 38, 37, 36, |
B1 |
± B8 |
Output cable drivers |
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35, 33, 32 |
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29, 28, 27, 26 |
C14 ± C17 |
External cables control signal |
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input |
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1999 Sep 17 |
4 |
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