INTEGRATED CIRCUITS
PCK2020
CK00 (100/133MHz) spread spectrum
differential system clock generator
Product specification
Supersedes data of 2000 Jul 25
2000 Nov 13
Philips Semiconductors Product specification
CK00 (100/133MHz) spread spectrum
differential system clock generator
FEA TURES
•3.3 V operation
•Four differential CPU clock pairs
•Ten PCI clocks at 3.3 V
•Four 66 MHz clocks at 3.3 V
•Two 48 MHz clocks at 3.3 V
•Two 14.318 MHz reference clocks
•100 or 133 MHz operation
•Power management control pins
•CPU clock skew less than 200 ps cycle-to-cycle
•CPU clock skew less than 150 ps pin-to-pin
•1.5 ns to 3.5 ns delay on PCI pins
•Spread Spectrum capability
DESCRIPTION
The PCK2020 is a clock synthesizer/driver for a Pentium III and
other similar processors.
The PCK2020 has four differential pair CPU current source outputs,
two Mref clock outputs running at 1/2 the CPU clock frequency
depending on the state of SEL133/100 pin and four 3V66 clocks
running at 66 MHz. There are ten PCI clock outputs running at
33 MHz and two 48 MHz clocks. Finally, there are two 3.3 V
reference clocks at 14.318 MHz. All clock outputs meet Intel’s drive
strength, rise/fall times, jitter, accuracy, and skew requirements.
The part possesses a dedicated power-down input pin for power
management control. This input is synchronized on-chip and
ensures glitch-free output transitions.
PIN CONFIGURATION
1
Ref0/MultSel0
Ref1/MultSel1
V
DD
XTAL_IN
XTAL_OUT
PCICLK0
PCICLK1
V
DD
PCICLK2
PCICLK4
PCICLK5
V
DD
PCICLK6
PCICLK7
PCICLK9
V
DD
SEL100/133
48MHz0/SelA
2
3
3.3Ref
4
5
6
V
7
PCI
SS
8
9
10
3.3PCI
11
12 45
13
14
15
16
3.3PCI
17
18 39
19 38
VSSPCI
20
21
22
3.3PCI
23
24
USB
V
SS
25 32
26 31 3V66_248MHz1/SelB
27 30 3V66_3VDD3.3USB
28 29PWRDWN VDD3.3
PCK2020
V
56VSSRef
3.3M
DD
55
3VMref
54
3VMref_b
M
53
V
SS
SPREAD
52
51
CPUCLK0
50
CPUCLK0
V
3.3CPU
49
DD
48
CPUCLK1
47
CPUCLK1
46
VSSCPU
CPUCLK2PCICLK3
44VSSPCI
CPUCLK2
V
3.3CPU
43
DD
42
CPUCLK3
CPUCLK3
41
40
VSSCPU
I_REF
V
3.3Core
DD
37PCICLK8
Core
V
SS
36
V
3.3
DD
35
3V66_0
34
3V66_1
33
V
SS
V
SS
SW00577
ORDERING INFORMA TION
PACKAGES TEMPERATURE RANGE (°C) ORDER CODE DRAWING NUMBER
56-Pin Plastic SSOP 0 to +70 PCK2020 DL SOT371-1
Intel and Pentium are registered trademarks of Intel Corporation.
2000 Nov 13 853-2209 25006
2
Philips Semiconductors Product specification
CK00 (100/133MHz) spread spectrum
differential system clock generator
PIN DESCRIPTION
PIN NUMBER SYMBOL FUNCTION
1 VSSRef
2, 3
4 VDD3.3Ref
5 XTAL_IN Crystal input
6 XTAL_OUT Crystal output
7, 13, 19 VSSPCI
8, 9, 11, 12, 14, 15, 17,
18, 20, 21
10, 16, 22 VDD3.3PCI
23 SEL100/133 Select input pin for enabling 133 MHz or 100 MHz CPU outputs.
24 VSSUSB
25, 26
27 VDD3.3USB
28 PWRDWN Device enters power down mode when held low. Asserts low.
29, 36 VDD3.3
30, 31, 34, 35 3V66[0–3] 3.3 V fixed 66 MHz CPU clock outputs.
32, 33 V
37 VSSCore
38 VDD3.3Core 3.3 V power supply for analog circuits.
39 I_REF
40, 46 VSSCPU
41, 44, 47, 50 CPUCLK[0–3]
42, 45, 48, 51 CPUCLK[0–3]
43, 49 VDD3.3CPU
52 SPREAD
53 VSSM
54 3VMref_b
55 3VMref
56 VDD3.3M 3.3 V power supply
Ref0/MultSel0
Ref1/MultSel1
PCICLK[0–9] 3.3 V PCI clock outputs fixed at 33 MHz.
48 MHz/SelA
48 MHz/SelB
SS
During power up, pins functions as a latched inputs that enables MULTSEL0 and
MULTSEL1 prior to the pins being used for output of 3 V at 14.318 MHz. Part must be
clocked to latch data in.
3.3 V fixed 48 MHz clock outputs. During power up, pins functions as latched inputs
that enables SELA and SELB prior to the pins being used for output of 3 V at 48 MHz.
Part must be clocked to latch data in.
This pin controls the reference current for the host pairs. This pin requires a fixed
precision resistor tied to ground in order to establish the correct current.
Enables spread spectrum mode when held low on differential host outputs,
MREF/MREF_B clocks, 66 MHz clocks, and 33 MHz PCI clocks. Asserts low.
3.3 V clock outputs running at 1/2 CPU clock frequency. 66 MHz or 50 MHz depending
on the state of input pin SEL133/100. (Out of phase with 3VMREF output).
3.3 V clock outputs running at 1/2 CPU clock frequency. 66 MHz or 50 MHz depending
on the state of input pin SEL133/100.
PCK2020
2000 Nov 13
3
Philips Semiconductors Product specification
CK00 (100/133MHz) spread spectrum
differential system clock generator
BLOCK DIAGRAM
XIN
X
14.318
MHZ
XOUT
SPREAD
SEL 133/100
SEL0
SEL1
OSC
X
X
X
DECODE
X
LOGIC
X
USBPLL
SYSPLL
PWRDWN
PWRDWN
PWRDWN
PWRDWN
PWRDWN
REF [0–1](14.318 MHz)
X
X
48 MHz[0–1] 3 V
CPUCLK [0–3]
X
CPUCLK [0–3]
X
3V66 [0–3] (66 MHz)
X
3VMRef
X
PCK2020
PWRDWN
PWRDWN
X
PWRDWN
PWRDWN
PCICLK_F (33 MHz)
X
3VMRef
X
PCICLK_F (33 MHz)
X
SW00727
2000 Nov 13
4
Philips Semiconductors Product specification
CK00 (100/133MHz) spread spectrum
PCK2020
differential system clock generator
FUNCTION TABLES
SEL
100/133
0 0 0 100 MHz 50 MHz 66.7 MHz 33.3 MHz 48 MHz 14.318 MHz
0 0 1 105 MHz
0 1 0 200 MHz 50 MHz 66.7 MHz 33.3 MHz N/A N/A
0 1 1 HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z
1 0 0 133 MHz 66.7 MHz 66.7 MHz 33.3 MHz 48 MHz 14.318 MHz
1 0 1 126.7 MHz
1 1 0 200 MHz 66.7 MHz 66.7 MHz 33.3 MHz 48 MHz 14.318 MHz
1 1 1 TCLK/2 TCLK/4 TCLK/4 TCLK/8 TCLK/2 TCLK
NOTE:
1. These frequencies are for debug and thus can vary a small amount from the values listed at the vendor’s discretion.
SEL
100/133
0 0 0 Active 100 MHz
0 0 1 Active 100 MHz – ~5% over-clock
0 1 0 200 MHz, 50 MHz M
0 1 1 HI-Z all outputs
1 0 0 Active 133 MHz
1 0 1 Active 133.3 MHz minus ~5 under-clock
1 1 0 200 MHz, 66 MHz M
1 1 1 Test mode
SELA SELB HOST M
1
1
SELA SELB HOST
REF
52.5 MHz
63.3 MHz
REF
REF
1
1
3V66 3V33 PCI 48 MHz REF
1
70 MHz
63.3 MHz
35 MHz
1
31.7 MHz
1
1
48 MHz 14.318 MHz
48 MHz 14.318 MHz
POWER DOWN MODE
PWRDWN HOST/HOST_BAR MREF/MREF_B 3V66 PCI 48 MHz REF 14.318/66 MHz Seeds
Asserts low
0 = Active
NOTE:
1. The differential outputs should have a voltage forced across them when power down is asserted.
HOST = 2*I
HOST_BAR
REF
LOW LOW LOW LOW OFF LOW/(if applicable)
SPREAD SPECTRUM FUNCTION TABLE
SPREAD FUNCTION
1
0
HOST/PCI/3V66/M
HOST/PCI/3V66/M
Down spread –0.5%
No spread
REF/MREF_B
REF/MREF_B
48 MHz PLL
REF/MULTSEL0
REF/MULTSEL1
No spread
No spread
2000 Nov 13
5