Philips PCK2010RADL Datasheet

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PCK2010RA

CK98R (100/133MHz) RCC spread

spectrum system clock generator

Product specification

Supersedes data of 2000 Dec 01

ICL03 — PC Motherboard ICs; Logic Products Group

2001 Apr 02

INTEGRATED CIRCUITS

Philips Semiconductors Product specification

PCK2010RA

CK98R (100/133MHz) RCC spread spectrum

system clock generator

2

2001 Apr 02 853–2232 25964

FEA TURES

•Mixed 2.5 V and 3.3 V operation

•Four CPU clocks at 2.5 V

•Eight PCI clocks at 3.3 V, one free-running

(synchronous with CPU clocks)

•Four 3.3 V fixed clocks @ 66 MHz

•Two 2.5 V CPUDIV2 clocks @

1

/

2

CPU clock frequency

•Three 2.5 V IOAPIC clocks @ 16.67 MHz

•One 3.3 V 48 MHz USB clock

•Two 3.3 V reference clocks @ 14.318 MHz

•Reference 14.31818 MHz Xtal oscillator input

•133 MHz or 100 MHz operation, 133.01 MHz in 133 mode

•Power management control input pins

•CPU clock jitter ≤ 250 ps cycle-cycle

•CPU clock skew ≤ 175 ps pin-pin

•0.0 ns – 1.5 ns CPU–3V66 delay

•1.5 ns – 3.5 ns 3V66–PCI delay

•1.5 ns – 4.0 ns CPU–IOAPIC delay

•1.5 ns – 4.0 ns CPU–PCI delay

•Available in 56-pin SSOP package

•±0.6% center spread spectrum capability via select pins

•–0.6% down spread spectrum capability via select pins

DESCRIPTION

The PCK2010RA is a clock generator (frequency synthesizer) chip

for a Pentium II and other similar processors.

The PCK2010RA has four CPU clock outputs at 2.5 V, two

CPUDIV2 clock outputs running at

1

/

2

CPU clock frequency

(66 MHz or 50 MHz depending on the state of SEL133/100) and four

3V66 clocks running at 66MHz. There are eight PCI clock outputs

running at 33 MHz. One of the PCI clock outputs is free-running.

Additionally, the part has three 2.5 V IOAPIC clock outputs at

16.67 MHz and two 3.3 V reference clock outputs at 14.318 MHz. All

clock outputs meet Intel’s drive strength, rise/fall time, jitter,

accuracy, and skew requirements.

The part possesses dedicated power-down, CPUSTOP

, and

PCISTOP

input pins for power management control. These inputs

are synchronized on-chip and ensure glitch-free output transitions.

When the CPUSTOP input is asserted, the CPU clock outputs and

3V66 clock outputs are driven LOW. When the PCISTOP

input is

asserted, the PCI clock outputs are driven LOW.

Finally, when the PWRDWN input pin is asserted, the internal

reference oscillator and PLLs are shut down, and all outputs are

driven LOW.

PIN CONFIGURATION

SW00892

1

2

3

4

5

6

7

8

9

10

11

12 45

46

47

48

49

50

51

52

53

54

55

56V

SS

REF1

V

DD

3V

XTAL_IN

XTAL_OUT

V

SS

PCICLK_F

PCICLK1

V

DD

3V

PCICLK2

CPUCLK0

V

SS

CPUCLK1

V

DD

3V

CPUCLK2

PCICLK3

13

14

15

16

17

18 39

40

41

42

43

44V

SS

PCICLK4

PCICLK5

V

DD

3V

PCICLK6

CPUCLK3

PCICLK7

19 38V

SS

20

21

22

23

24

25 32

33

34

35

36

37

V

DD

3V

3V66_0

3V66_1

SEL1

SEL0

V

SS

26 31

27 30

48MHz_USB

28 29SEl133/100

REF0

V

SS

3V66_2

3V66_3

V

DD

3V

V

DD

25V

APIC2

APIC1

APIC0

V

DD

25V

CPUDIV2_1

CPUDIV2_0

V

SS

V

DD

25V

V

SS

V

DD

25V

V

SS

V

SS

PCISTOP

CPUSTOP

PWRDWN

SPREAD

V

DD

3V

V

SS

ORDERING INFORMA TION

PACKAGES TEMPERATURE RANGE ORDER CODE DRAWING NUMBER

56-Pin plastic SSOP 0 to +70 °C PCK2010RADL SOT371-1

Intel and Pentium are registered trademarks of Intel Corporation.

Philips Semiconductors Product specification

PCK2010RA

CK98R (100/133MHz) RCC spread spectrum

system clock generator

2001 Apr 02

3

PIN DESCRIPTION

PIN NUMBER SYMBOL FUNCTION

2,3 REF [0–1] 3.3 V 14.318 MHz clock output

5 XTAL_IN 14.318 MHz crystal input

6 XTAL_OUT 14.318 MHz crystal output

8 PCICLK_F 3.3 V free running PCI clock

9, 11, 12, 14, 15, 17, 18 PCICLK [1–7] 3.3 V PCI clock outputs

21, 22, 25, 26 3V66 [0–3] 3.3 V fixed 66 MHz clock outputs

28 SEL133/100

Select input pin for enabling 133 MHz or 100 MHz CPU outputs.

H = 133 MHz, L = 100 MHz

30 48 MHz USB 3.3 V fixed 48 MHZ clock output

32, 33 SEL [0–1] Logic select pins. TTL levels.

34 SPREAD 3.3 V LVTTL input. Enables spread spectrum mode when held LOW .

35 PWRDWN 3.3 V LVTTL input. Device enters powerdown mode when held LOW.

36 CPUSTOP

3.3 V LVTTL input. Stops all CPU clocks and 3V66 clocks when held LOW.

CPUDIV_2 output remains on all the time.

37 PCISTOP 3.3 V LVTTL input. Stops all PCI clocks except PCICLK_F when held LOW.

41, 42, 45, 46 CPUCLK [0–3] 2.5 V CPU output. 133 MHz or 100MHz depending on state of input pin SEL133/100.

49, 50 CPUDIV_2 [0–1]

2.5 V output running at 1/2 CPU clock frequency. 66 MHz or 50 MHz depending on

state of input pin SEL133/100.

53, 54, 55 IOAPIC [0–2]

2.5 V clock outputs running divide synchronous with the CPU clock frequency.

Fixed 16.67 MHz limit.

4, 10, 16, 23, 27, 31, 39

2

V

DD3V

3.3 V power supply.

1, 7, 13, 19, 20, 24, 29,

38, 40, 44, 48, 52

V

SS

Ground

43, 47, 51, 56 V

DD25V

2.5 V power supply

NOTE:

1. V

DD3V

, V

DD25V

and V

SS

in the above table reflects a likely internal POWER and GROUND partition to reduce the effects of internal noise on

the performance of the device. In reality, the platform will be configured with the V

DD25V

pins tied to a 2.5 V supply, all remaining V

DD

pins

tied to a common 3.3 V supply and all V

SS

pins being common.

2. Pin 39 should have a pi or equivalent filter to reduce the effect of noise on the analog portions of the device.

Philips Semiconductors Product specification

PCK2010RA

CK98R (100/133MHz) RCC spread spectrum

system clock generator

2001 Apr 02

4

BLOCK DIAGRAM

PWRDWN

LOGIC

SYSPLL

USBPLL

14.318

MHZ

OSC

PWRDWN

LOGIC

DECODE

LOGIC

X

X

X

X

X

X

X

X

REF [0–1](14.318 MHz)

PWRDWN

SEL1

SPREAD

SEL133/100

XTAL_IN

XTAL_OUT

48 MHz USB

CPUCLK [0–3]

3V66 [0–3] (66MHz)

CPUDIV2 [0–1]

X

SEL0

SW00505

PWRDWN

LOGIC

X

PCICLK_F (33MHz)

PWRDWN

LOGIC

X

PWRDWN

LOGIC

X

APIC [0–2] (16.67 MHz)

PCICLK [1–7] (33 MHz)

X

STOP

LOGIC

LOGIC

X

PCISTOP

CPUSTOP

STOP

LOGIC

STOP

LOGIC

Philips Semiconductors Product specification

PCK2010RA

CK98R (100/133MHz) RCC spread spectrum

system clock generator

2001 Apr 02

5

FUNCTION TABLE

SEL

133/100

SEL1 SEL0 CPU CPUDIV2 3V66 PCI 48 MHz REF IOAPIC NOTES

0 0 0 HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z 1

0 0 1 100 MHz 50 MHz 66 MHz 33 MHz 48 MHz 14.318 MHz 16.67 MHz 2

0 1 0 100 MHz 50 MHz 66 MHz 33 MHz HI-Z 14.318 MHz 16.67 MHz 3

0 1 1 100 MHz 50 MHz 66 MHz 33 MHz 48 MHz 14.318 MHz 16.67 MHz 4, 7, 8

1 0 0 TCLK/2 TCLK/4 TCLK/4 TCLK/8 TCLK/2 TCLK TCLK/16 5, 6

1 0 1 133 MHz 66 MHz 66 MHz 33 MHz 48 MHz 14.318 MHz 16.67 MHz 2

1 1 0 133 MHz 66 MHz 66 MHz 33 MHz HI-Z 14.318 MHz 16.67 MHz 3

1 1 1 133 MHz 66 MHz 66 MHz 33 MHz 48 MHz 14.318 MHz 16.67 MHz 4, 7, 8

NOTES:

1. Required for board level “bed-of-nails” testing.

2. Philips center spread mode.

3. 48 MHz PLL disabled to reduce component jitter. 48 MHz outputs to be held Hi-Z instead of driven to LOW state.

4. “Normal” mode of operation.

5. TCLK is a test clock over driven on the XTALIN input during test mode. TCLK mode is based on 133 MHz CPU select logic.

6. Required for DC output impedance verification.

7. Frequency accuracy of 48 MHz must be +167 PPM to match USB default.

8. Range of reference frequency allowed is MIN = 14.316 MHz, NOMINAL = 14.31818 MHz, MAX = 14.32 MHz.

CLOCK OUTPUT

TARGET FREQUENCY (MHz) ACTUAL FREQUENCY (MHz) PPM

USBCLK

7

48.0 48.008 167

CLOCK ENABLE CONFIGURATION

CPUSTOP PWRDWN PCISTOP CPUCLK CPUDIV2 APIC 3V66 PCI PCI_F REF / 48 MHz OSC VCOs

X 0 X LOW LOW LOW LOW LOW LOW LOW OFF OFF

0 1 0 LOW ON ON LOW LOW ON ON ON ON

0 1 1 LOW ON ON LOW ON ON ON ON ON

1 1 0 ON ON ON ON LOW ON ON ON ON

1 1 1 ON ON ON ON ON ON ON ON ON

NOTES:

1. LOW means outputs held static LOW as per latency requirement below

2. ON means active.

3. PWRDWN

pulled LOW, impacts all outputs including REF and 48 MHz outputs.

4. All 3V66 clocks as well as CPU clocks should stop cleanly when CPUSTOP is pulled LOW.

5. CPUDIV2, IOAPIC, REF, 48 MHz signals are not controlled by the CPUSTOP functionality and are enabled all in all conditions except when

PWRDWN

is LOW.

POWER MANAGEMENT REQUIREMENTS

LATENCY

SIGNAL

SIGNAL

STATE

NO. OF RISING EDGES OF FREE RUNNING PCICLK

CPUSTOP

0 (DISABLED) 1

1 (ENABLED) 1

PCISTOP

0 (DISABLED) 1

1 (ENABLED) 1

PWRDWN

1 (NORMAL OPERATION) 3 ms

0 (POWER DOWN) 2 MAX

NOTES:

1. Clock ON/OFF latency is defined as the number of rising edges of free running PCICLKs between the clock disable goes HIGH/LOW to the

first valid clock that comes out of the device.

2. Power up latency is when PWRDWN

goes inactive (HIGH) to when the first valid clocks are driven from the device.