Philips PCK2002DGG, PCK2002DL Datasheet

INTEGRATED CIRCUITS

PCK2002

0±300 MHz I2C 1:18 clock buffer

Product data

2001 Jul 19

File under Integrated Circuits ICL03

P s

on o s

Philips Semiconductors	Product data
0±300 MHz I2C 1:18 clock buffer	PCK2002

FEATURES

•HIGH speed, LOW noise non-inverting 1±18 buffer

•Typically used to support four SDRAM DIMMs

•Multiple VDD, VSS pins for noise reduction

•3.3 V operation

•Separate 3-State pin for testing

•ESD protection exceeds 2000 V per Standard 801.2

•Optimized for 66 MHz, 100 MHz and 133 MHz operation

•Typical 175 ps skew outputs

•Available in 48-pin SSOP and TSSOP packages

•See PCK2002M for mobile (reduced pincount) 28-pin 1-10 buffer version

•Spread spectrum compliant

•Individual clock output enable/disable via I2C

DESCRIPTION

The PCK2002 is a 1±18 fanout buffer used for 133/100 MHz CPU,

66/33 MHz PCI, 14.318 MHz REF, or 133/100/66 MHz SDRAM clock distribution. 18 outputs are typically used to support up to 4 SDRAM DIMMS commonly found in desktop, workstation or server applications.

All clock outputs meet Intel's drive, rise/fall time, accuracy, and skew requirements. An I2C interface is included to allow each output to be enabled/disabled individually. An output disabled via the I2C interface will be held in the LOW state. In addition, there is an OE input which 3-States all outputs.

QUICK REFERENCE DATA

	SYMBOL	PARAMETER	CONDITIONS	TYPICAL	UNIT
	tPLH	Propagation delay	VCC = 3.3 V, CL = 30 pF	2.7	ns
	tPHL	BUF_IN to BUF_OUTn		2.9
	tr	Rise time	VCC = 3.3 V, CL = 30 pF	1.1	ns
	tf	Fall time	VCC = 3.3 V, CL = 30 pF	1.0	ns
	ICC	Total supply current	VCC = 3.465 V	35	μA

ORDERING INFORMATION

PACKAGES	TEMPERATURE RANGE	ORDER CODE	DRAWING NUMBER
48-Pin Plastic TSSOP	0 to +70 °C	PCK2002DGG	SOT362-1
48-Pin Plastic SSOP	0 to +70 °C	PCK2002DL	SOT370-1

PIN CONFIGURATION

RESERVED
		1		48	RESERVED
RESERVED		2		47	RESERVED
					VDD9
VDD0		3		46
BUF_OUT0		4		45	BUF_OUT15
BUF_OUT1		5		44	BUF_OUT14
VSS0					VSS9
		6		43
VDD1					VDD8
		7		42
BUF_OUT2		8		41	BUF_OUT13
BUF_OUT3		9		40	BUF_OUT12
VSS1					VSS8
		10		39
					OE
BUF_IN		11	PCK2002	38
VDD2					VDD7
		12		37
BUF_OUT4		13		36	BUF_OUT11
BUF_OUT5		14		35	BUF_OUT10
VSS2					VSS7
		15		34
VDD3					VDD6
		16		33
BUF_OUT6		17		32	BUF_OUT9
BUF_OUT7					BUF_OUT8
		18		31
VSS3					VSS6
		19		30
VDD4					VDD5
		20		29
					BUF_OUT17
BUF_OUT16		21		28
VSS4					VSS5
		22		27
VDDI2C					VSSI2C
		23		26
SDA		24		25	SCL
				SW00731

I2C is a trademark of Philips Semiconductors Corporation.

PIN DESCRIPTION

	PIN	I/O	SYMBOL	FUNCTION
	NUMBER	TYPE
	4, 5, 8, 9	Output	BUF_OUT (0±3)	Buffered clock outputs
	13, 14, 17, 18	Output	BUF_OUT (4±7)	Buffered clock outputs
	31, 32, 35,	Output	BUF_OUT	Buffered clock outputs
	36		(8±11)
	40, 41, 44,	Output	BUF_OUT	Buffered clock outputs
	45		(12±15)
	21, 28	Output	BUF_OUT	Buffered clock outputs
			(16±17)
	11	Input	BUF_IN	Buffered clock input
	38	Input	OE	Active high output
				enable
	24	I/O	SDA	I2C serial data
	25	Input	SCL	I2C serial clock
	3, 7, 12, 16,
	20, 29, 33,	Input	VDD (0±9)	3.3 V Power supply
	37, 42, 46
	6, 10, 15,
	19, 22,	Input	VSS (0±9)	Ground
	27, 30, 34,
	39, 43
	23	Input	VDDI2C	3.3 V I2C Power
				supply
	26	Input	V	I2C Ground
			SSI2C
	1, 2, 47, 48	n/a	RESERVED	Undefined

2001 Jul 19

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853-2267 26745

Philips Semiconductors	Product data
0±300 MHz I2C 1:18 clock buffer	PCK2002

FUNCTION TABLE

OE	BUF_IN	I2CEN	BUF_OUTn
L	X	X	Z
H	L	X	L
H	H	H	H
H	H	L	L

ABSOLUTE MAXIMUM RATINGS1, 2

In accordance with the Absolute Maximum Rating System (IEC 134)

Voltages are referenced to VSS (VSS = 0V)

SYMBOL	PARAMETER	CONDITION		LIMITS		UNIT
			MIN		MAX
VDD	DC 3.3 V supply voltage		±0.5		+4.6	V
IIK	DC input diode current	VI < 0			±50	mA
VI	DC input voltage	Note 2	±0.5		+4.6	V
IOK	DC output diode current	VO > VDD or VO < 0			±50	mA
VO	DC output voltage	Note 2	±0.5		VCC + 0.5	V
IO	DC output source or sink current	VO >= 0 to VDD			±50	mA
TSTG	Storage temperature range		±65		+150	°C
PTOT	Power dissipation per package	For temperature range: 0 to +70°C			850	mW
	plastic medium-shrink SO (SSOP)	above +55°C derate linearly with 11.3mW/K

NOTES:

1.Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under ªrecommended operating conditionsº is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

2.The input and output voltage ratings may be exceeded if the input and output current ratings are observed.

RECOMMENDED OPERATING CONDITIONS

SYMBOL	PARAMETER	CONDITIONS		LIMITS		UNIT
			MIN		MAX
VDD	DC 3.3 V supply voltage		3.135		3.465	V
CL	Capacitive load		20		30	pF
VI	DC input voltage range		0		VDD	V
VO	DC output voltage range		0		VDD	V
Tamb	Operating ambient temperature range in free air		0		+70	°C

2001 Jul 19

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Philips Semiconductors	Product data
0±300 MHz I2C 1:18 clock buffer	PCK2002

DC CHARACTERISTICS

			TEST CONDITIONS		LIMITS
SYMBOL	PARAMETER				Tamb = 0 to +70 °C		UNIT
		VDD (V)	OTHER		MIN	MAX
VIH	HIGH level input voltage	3.135 to 3.465			2.0	VDD + 0.3	V
VIL	LOW level input voltage	3.135 to 3.465			VSS ± 0.3	0.8	V
VOH	3.3V output HIGH voltage	3.135 to 3.465	IOH = ±1 mA		VCC ± 0.1	Ð	V
		3.135	IOH = ±36 mA		2.4	Ð
VOL	3.3V output LOW voltage	3.135 to 3.465	IOL= 1 mA		Ð	0.1	V
		3.135	IOL= 24 mA		Ð	0.4
IOH	Output HIGH current	3.135	VOUT = 2.0 V		±54	±126	mA
		3.465	VOUT = 3.135 V		±21	±46
IOL	Output LOW current	3.135 to 3.465	VOUT = 1.0 V		49	118	mA
		3.135 to 3.465	VOUT = 0.4 V		24	53
±II	Input leakage current	3.465			Ð	±5	μA
±IOZ	3-State output OFF-State current	3.465	VOUT = VDDor GND	IO = 0	Ð	10	μA
ICC	Quiescent supply current	3.465	VI = VDD or GND	IO = 0	Ð	100	μA
ICC	Additional quiescent supply	3.135 to 3.465	VI = VDD± 0.6V	IO = 0	Ð	500	μA
	current given per control pin

AC CHARACTERISTICS

		TEST CONDITIONS				LIMITS
SYMBOL	PARAMETER				Tamb = 0 to +70 °C				UNIT
			NOTES	MIN		TYP6		MAX
TSDRISE	SDRAM rise time		2, 4	1.5		2.0		4.0	V/ns
TSDFALL	SDRAM fall time		2, 4	1.5		2.9		4.0	V/ns
TPLH	SDRAM buffer LH propagation delay		4, 5	1.2		2.7		3.5	ns
TPHL	SDRAM buffer HL propagation delay		4, 5	1.2		2.9		3.5	ns
TPZL, TPZH	SDRAM buffer enable time		4, 5	1.0		2.6		5.0	ns
TPLZ, TPHZ	SDRAM buffer disable time		4, 5	1.0		2.7		5.0	ns
DUTY CYCLE	Output Duty Cycle	Measured at 1.5 V	3, 4, 5	45		52		55	%
TSDSKW	SDRAM Bus CLK skew		1, 4	Ð		150		250	ps
TDDSKW	Device to device skew			Ð		Ð		500	ps

NOTES:

1.Skew is measured on the rising edge at 1.5 V.

2.TSDRISE and TSDFALL are measured as a transition through the threshold region VOL = 0.4 V and VOH = 2.4 V (1mA) JEDEC specification.

3.Duty cycle should be tested with a 50/50% input.

4.Over MIN (20 pF) to MAX (30 pF) discrete load, process, voltage, and temperature.

5.Input edge rate for these tests must be faster than 1 V/ns.

6.All typical values are at VCC = 3.3 V and Tamb = 25 °C.

2001 Jul 19

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