Philips PCF2119RU-2-F1, PCF2119SU-2-F1, PCF2119U-2-F1, PCF2119VU-2-F1 Datasheet

INTEGRATED CIRCUITS

DATA SHEET

PCF2119x

LCD controllers/drivers

Product specification

1999 Mar 02

Supersedes data of 1997 Nov 21

File under Integrated Circuits, IC12

Philips Semiconductors	Product specification
LCD controllers/drivers	PCF2119x

CONTENTS

1 FEATURES

1.1Note

2APPLICATIONS

3GENERAL DESCRIPTION

4ORDERING INFORMATION

5BLOCK DIAGRAM

6PAD INFORMATION

6.1Pad functions

7	FUNCTIONAL DESCRIPTION

7.1LCD supply voltage generator

7.2Programming ranges

7.3LCD bias voltage generator

7.4Oscillator

7.5External clock

7.6Power-on reset

7.7Power-down mode

7.8Registers

7.9Busy flag

7.10Address Counter (AC)

7.11Display Data RAM (DDRAM)

7.12Character Generator ROM (CGROM)

7.13Character Generator RAM (CGRAM)

7.14Cursor control circuit

7.15Timing generator

7.16LCD row and column drivers

7.17Reset function

8 INSTRUCTIONS

8.1Clear display

8.2Return home

8.3Entry mode set

8.4Display control (and partial power-down mode)

8.5Cursor or display shift

8.6Function set

8.7Set CGRAM address

8.8Set DDRAM address

8.9Read busy flag and read address

8.10Write data to CGRAM or DDRAM

8.11Read data from CGRAM or DDRAM

9EXTENDED FUNCTION SET INSTRUCTIONS AND FEATURES

9.1New instructions

9.2Icon control

9.3IM

9.4IB

9.5Normal/icon mode operation

9.6Screen configuration

9.7Display configuration

9.8TC1 and TC2

9.9Set VLCD

9.10Reducing current consumption

10 INTERFACES TO MPU

10.1Parallel interface

10.2I2C-bus interface

11LIMITING VALUES

12HANDLING

13DC CHARACTERISTICS

14AC CHARACTERISTICS

15TIMING CHARACTERISTICS

16APPLICATION INFORMATION

16.18-bit operation, 1-line display using external reset

16.24-bit operation, 1-line display using external reset

16.38-bit operation, 2-line display

16.4I2C-bus operation, 1-line display

17BONDING PAD LOCATIONS

18DEFINITIONS

19LIFE SUPPORT APPLICATIONS

20PURCHASE OF PHILIPS I2C COMPONENTS

1999 Mar 02

2

Philips Semiconductors	Product specification
LCD controllers/drivers	PCF2119x

1 FEATURES

∙Single-chip LCD controller/driver

∙2-line display of up to 16 characters + 160 icons, or 1-line display of up to 32 characters + 160 icons

∙5 × 7 character format plus cursor; 5 × 8 for kana (Japanese) and user defined symbols

∙Icon mode: reduced current consumption while displaying icons only

∙Icon blink function

∙On-chip:

–Generation of LCD supply voltage, independent of

VDD, programmable by instruction (external supply also possible)

–Temperature compensation of on-chip generated VLCD: −8 to −12 mV/K at 5.0 V (programmable by instruction)

∙Very low current consumption (20 to 200 μA):

–Icon mode: <25 μA

–Power-down mode: <2 μA.

1.1Note

Icon mode is used to save current. When only icons are displayed, a much lower operating voltage VLCD can be used and the switching frequency of the LCD outputs is reduced. In most applications it is possible to use VDD as

VLCD.

–Generation of intermediate LCD bias voltages

–Oscillator requires no external components (external clock also possible).

∙Display Data RAM: 80 characters

∙Character Generator ROM: 240, 5 × 8 characters

∙Character Generator RAM: 16, 5 × 8 characters;

4 characters used to drive 160 icons, 8 characters used if icon blink feature is used in application

∙4 or 8-bit parallel bus and 2-wire I2C-bus interface

∙CMOS compatible

∙18 row and 80 column outputs

∙Multiplex rates 1 : 18 (for normal operation), 1 : 9 (for single line operation) and 1 : 2 (for icon only mode)

∙Uses common 11 code instruction set (extended)

∙Logic supply voltage range, VDD − VSS = 2.2 to 4.0 V (up to 5.5 V if external VLCD is used); chip may be driven with two battery cells

∙Display supply voltage range, VLCD − VSS = 2.2 to 6.5 V

4 ORDERING INFORMATION

2 APPLICATIONS

∙Telecom equipment

∙Portable instruments

∙Point-of-sale terminals.

3 GENERAL DESCRIPTION

The PCF2119x is a low power CMOS LCD controller and driver, designed to drive a dot matrix LCD display of 2-line by 16 or 1-line by 32 characters with 5 × 8 dot format.

All necessary functions for the display are provided in a single chip, including on-chip generation of LCD bias voltages, resulting in a minimum of external components and lower system current consumption. The PCF2119x interfaces to most microcontrollers via a 4 or 8-bit bus or via the 2-wire I2C-bus. The chip contains a character generator and displays alphanumeric and kana (Japanese) characters. The letter ‘x’ in PCF2119x characterizes the built-in character set. Various character sets can be manufactured on request.

TYPE		PACKAGE
NUMBER	NAME	DESCRIPTION	VERSION
PC2119RU/2	−	chip with bumps in tray	−
PC2119SU/2	−	chip with bumps in tray	−
PC2119VU/2	−	chip with bumps in tray	−

1999 Mar 02

3

Philips Semiconductors	Product specification
LCD controllers/drivers	PCF2119x

5 BLOCK DIAGRAM

					C1 to C80				R17DUP	R1 to R18
					118 to 127, 106 to 92				72	27 to 34,
					87 to 73, 71 to 57,					116 to 109,
					52 to 38, 16 to 25					26, 117
					80					18
12, 13	BIAS			COLUMN DRIVERS						ROW DRIVERS
VLCD1	VOLTAGE				80
	GENERATOR									18
				DATA LATCHES						SHIFT REGISTER 18-BIT
14, 15	VLCD				80
VLCD2	GENERATOR		SHIFT REGISTER 5 × 12 BIT
					5					OSCILLATOR	144
											OSC
			CURSOR AND DATA CONTROL
					5
1, 2
VDD1			CHARACTER			CHARACTER
3, 4			GENERATOR			GENERATOR
			RAM (128 × 5)
VDD2							ROM
			(CGRAM)			(CGROM)
8, 9		16 CHARACTERS				240 CHARACTERS				TIMING
VSS1										GENERATOR
10, 11					8
VSS2
6				DISPLAY DATA RAM
T1	7										131
7					(DDRAM)
											PD
T2			80 CHARACTERS/BYTES
129
T3						7
										7
					ADDRESS COUNTER					DISPLAY
						(AC)				ADDRESS
										COUNTER
			7			7
					INSTRUCTION
					DECODER
	DATA					8
	REGISTER		BUSY		INSTRUCTION					PCF2119x
	(DR)		FLAG		REGISTER
	8					8					130
											POR
136
DB0/SA0			I/O BUFFER
	137 to 139		140 to 143	5	134	135	128		132, 133
											MGK891
DB1 to DB3		DB4 to DB7		E	R/W	RS	SCL	SDA
					Fig.1 Block diagram.
1999 Mar 02						4

Philips Semiconductors										Product specification
LCD controllers/drivers										PCF2119x
6		PAD INFORMATION
The identification of each pad and its location is given in Chapter 17.
6.1			Pad functions
Table 1 Pad function description
SYMBOL						DESCRIPTION
VDD1				Supply voltage for all except the high voltage generator.
VDD2				Supply voltage for the high voltage generator.
VSS1				This is the ground pad for all except the high voltage generator.
VSS2				This is the ground pad for the high voltage generator.
VLCD1				This input is used for the generation of the LCD bias levels.
VLCD2				This is the VLCD output pad if VLCD is generated internally. This pad must be connected to VLCD1.
E				The data bus clock input is set HIGH to signal the start of a read or write operation; data is clocked in
				or out of the chip on the negative edge of the clock; note 1.
T1				These are three test pads. T1 and T2 must be connected to VSS1; T3 is left open-circuit and is not user
T2				accessible.
T3
R1 to R18;				LCD row driver outputs R1 to R18; these pads output the row select waveforms to the display;
R17DUP				R17 and R18 drive the icons. R17 has two pads R17 and R17DUP.
C1 to C80				LCD column driver outputs C1 to C80.
SCL				I2C-bus serial clock input; note 1.
POR				External power-on reset input.
PD				PD selects the chip power-down mode; for normal operation PD = 0.
SDA				I2C-bus serial data input/output; note 1.
R/W				This is the read/write input. R/W		selects either the read (R/W = 1) or write (R/W = 0) operation. This
				pad has an internal pull-up resistor.
RS				The RS input selects the register to be accessed for read and write. RS = 0, selects the instruction
				register for write and the busy flag and address counter for read. RS = 1, selects the data register for
				both read and write. This pad has an internal pull-up resistor.
DB0 to DB7				The 8-bit bidirectional data bus (3-state) transfers data between the system controller and the
				PCF2119x. DB7 may be used as the busy flag, signalling that internal operations are not yet
				completed. In 4-bit operations the 4 higher order lines DB7 to DB4 are used; DB3 to DB0 must be left
				open-circuit. Data bus line DB3 has an alternative function (SA0), when selected this is the I2C-bus
				address pad. Each data line has its own internal pull-up resistor; note 1.
OSC				Oscillator or external clock input. When the on-chip oscillator is used this pad must be connected to
				VDD1.

Note

1.When the I2C-bus is used, the parallel interface pad E must be at logic 0. In the I2C-bus read mode DB7 to DB0 should be connected to VDD1 or left open-circuit.

a)When the parallel bus is used, pads SCL and SDA must be connected to VSS1 or VDD1; they must not be left open-circuit.

b)If the 4-bit interface is used without reading out from the PCF2119x (i.e. R/W is set permanently to logic 0), the unused ports DB0 to DB4 can either be set to VSS1 or VDD1 instead of leaving them open-circuit.

1999 Mar 02

5

Philips Semiconductors	Product specification
LCD controllers/drivers	PCF2119x

7 FUNCTIONAL DESCRIPTION

7.1LCD supply voltage generator

The LCD supply voltage may be generated on-chip. The voltage generator is controlled by two internal 6-bit

registers: VA and VB. The nominal LCD operating voltage at room temperature is given by the relationship:

VOP(nom) = ( integer value of register × 0.082) + 1.82

7.2Programming ranges

Programmed value: 1 to 63. Voltage: 1.902 to 6.986 V. Tref = 27 °C.

Values producing more than 6.5 V at operating temperature are not allowed. Operation above this voltage may damage the device. When programming the operating voltage the VLCD temperature coefficient must be taken into account.

Values below 2.2 V are below the specified operating range of the chip and are therefore not allowed.

Value 0 for VA and VB switches the generator off (i.e. VA = 0 in character mode, VB = 0 in icon mode).

Usually register VA is programmed with the voltage for character mode and register VB with the voltage for icon mode.

When VLCD is generated on-chip the VLCD pads should be decoupled to VSS with a suitable capacitor. The generated

VLCD is independent of VDD and is temperature compensated. When the generator is switched off an

external voltage may be supplied at connected pads VLCD1,2. VLCD1,2 may be higher or lower than VDD.

The LCD supply voltage generator ensures that, as long as VDD is in the valid range (2.2 to 4 V), the required peak voltage VOP = 5.2 V can be generated at any time.

7.3LCD bias voltage generator

The intermediate bias voltages for the LCD display are also generated on-chip. This removes the need for an external resistive bias chain and significantly reduces the system current consumption. The optimum value of VLCD depends on the multiplex rate, the LCD threshold voltage (Vth) and the number of bias levels. Using a 5-level bias

scheme for 1 : 18 maximum rate allows VLCD < 5 V for most LCD liquids. The intermediate bias levels for the

different multiplex rates are shown in Table 2. These bias levels are automatically set to the given values when switching to the corresponding multiplex rate.

Table 2 Bias levels as a function of multiplex rate

	MULTIPLEX	NUMBER	V1		V2	V3	V4	V5	V6
	RATE	OF LEVELS
	1 : 18	5	V	op	3/4(1)	1/2	1/2	1/4	V
									ss
	1 : 9	5	Vop		3/4	1/2	1/2	1/4	Vss
	1 : 2	4	Vop		2/3	2/3	1/3	1/3	Vss

Note

1.The values in the above table are given relative to Vop − Vss, e.g. 3/4 means 3/4 × (Vop − Vss).

7.4Oscillator

The on-chip oscillator provides the clock signal for the display system. No external components are required and the OSC pad must be connected to VDD.

1999 Mar 02

6

fframe

Philips Semiconductors	Product specification
LCD controllers/drivers	PCF2119x

7.5External clock

If an external clock is to be used this is input at the OSC pad. The resulting display frame frequency is given by:

fOSC

= -------------

3 072

Only in the power-down state is the clock allowed to be stopped (OSC connected to VSS), otherwise the LCD is frozen in a DC state.

7.6Power-on reset

The PC2119x must be reset externally. This is an internal synchronous reset that requires 3 OSC cycles to be executed after release of the external reset signal. If no external reset is performed, the chip might start-up in an unwanted state. The external reset is active HIGH.

7.7Power-down mode

The chip can be put into power-down mode where all static currents are switched off (no internal oscillator, no bias level generation and all LCD outputs are internally connected to VSS) when PD = 1.

During power-down, information in the RAMs and the chip state are preserved. Instruction execution during power-down is possible when pad OSC is externally clocked.

7.8Registers

The PCF2119x has two 8-bit registers, an Instruction Register (IR) and a Data Register (DR). The Register Select signal (RS) determines which register will be accessed. The instruction register stores instruction codes such as ‘display clear’ and ‘cursor shift’, and address information for the Display Data RAM (DDRAM) and Character Generator RAM (CGRAM).

The instruction register can be written to but not read from by the system controller. The data register temporarily stores data to be read from the DDRAM and CGRAM.

When reading, data from the DDRAM or CGRAM corresponding to the address in the instruction register is written to the data register prior to being read by the ‘read data’ instruction.

7.9Busy flag

The busy flag indicates the internal status of the PCF2119x. A logic 1 indicates that the chip is busy and further instructions will not be accepted. The busy flag is output to pad DB7 when RS = 0 and R/W = 1. Instructions should only be written after checking that the busy flag is at logic 0 or waiting for the required number of cycles.

7.10Address Counter (AC)

The address counter assigns addresses to the DDRAM and CGRAM for reading and writing and is set by the commands ‘set CGRAM address’ and ‘set DDRAM address’. After a read/write operation the address counter is automatically incremented or decremented by 1.

The address counter contents are output to the bus (DB6 to DB0) when RS = 0 and R/W = 1.

7.11Display Data RAM (DDRAM)

The DDRAM stores up to 80 characters of display data represented by 8-bit character codes. RAM locations which are not used for storing display data can be used as general purpose RAM. The basic RAM to display addressing scheme is shown in Fig.2. With no display shift the characters represented by the codes in the first

32 RAM locations starting at address 00H in line 1 are displayed. Figures 3 and 4 show the display mapping for right and left shift respectively.

When data is written to or read from the DDRAM wrap-around occurs from the end of one line to the start of the next line. When the display is shifted each line wraps around within itself, independently of the others. Thus all lines are shifted and wrapped around together.

The address ranges and wrap-around operations for the various modes are shown in Table 3.

Table 3 Address space and wrap-around operation

MODE	1 × 32	2 ×	16	1 × 9
Address space	00 to 4F	00 to 27;	40 to 67	00 to 27
Read/write wrap-around (moves to	4F to 00	27 to 40;	67 to 00	27 to 00
next line)
Display shift wrap-around (stays within	Do not use (make sure, that 4F and 00	27 to 00;	67 to 40	27 to 00
line)	are not displayed at the same time.)

1999 Mar 02

7

Philips Semiconductors	Product specification
LCD controllers/drivers	PCF2119x

handbook, full pagewidth	display	1	2	3	4	5		30 31 32					non-displayed DDRAM addresses
	position
	DDRAM	00	01	02	03	04		1D	1E	1F	20		21						4C		4D			4E	4F
	address
	1-line display
												non-displayed DDRAM address
		1	2	3	4	5		14 15 16																line 1
		00	01	02	03	04		0D	0E	0F	10		11		24	25		26		27
	DDRAM
		1	2	3	4	5		14 15 16
	address
		40	41	42	43	44		4D	4E	4F	50		51		64	65		66		67				line 2
	2-line display/MUX 1 : 9 mode																MGK892

Fig.2 DDRAM to display mapping: no shift.

	1	2	3	4	5		14 15 16
	27	00	01	02	03		0C	0D	0E	line 1
DDRAM
	1	2	3	4	5		10 11 12
address
	67	40	41	42	43		4C	4D	4E	line 2
2-line display/MUX 1 : 9 mode										MGL536

Fig.3 DDRAM to display mapping: right shift: (For 1 × 32 only as long as 4F and 00 positions are not on display simultaneously).

display	1	2	3	4	5		30 31 32
position
DDRAM	01	02	03	04	05		1E	1F	20
address
1-line display
	1	2	3	4	5		14 15 16
	01	02	03	04	05		0E	0F	10	line 1
DDRAM
	1	2	3	4	5		14 15 16
address
	41	42	43	44	45		4E	4F	50	line 2
2-line display/MUX 1 : 9 mode										MGK894

Fig.4 DDRAM to display mapping; left shift: (For 1 × 32 only as long as 4F and 00 positions are not on display simultaneously).

1999 Mar 02

8

Philips Semiconductors	Product specification
LCD controllers/drivers	PCF2119x

7.12Character Generator ROM (CGROM)

The Character Generator ROM generates 240 character patterns in a 5 × 8 dot format from 8-bit character codes. Figure 6 shows the character set that is currently implemented.

7.13Character Generator RAM (CGRAM)

Up to 16 user defined characters may be stored in the Character Generator RAM. Some CGRAM characters (see Fig.17) are also used to drive icons (6 if icons blink and both icon rows are used in the application; 3 if no blink but both icon rows are used in the application; 0 if no icons are driven by the icon rows). The CGROM and CGRAM use a common address space, of which the first column is reserved for the CGRAM (see Fig.6). Figure 9 shows the addressing principle for the CGRAM.

7.14Cursor control circuit

The cursor control circuit generates the cursor (underline and/or cursor blink as shown in Fig.5) at the DDRAM address contained in the address counter.

When the address counter contains the CGRAM address the cursor will be inhibited.

7.15Timing generator

The timing generator produces the various signals required to drive the internal circuitry. Internal chip operation is not disturbed by operations on the data buses.

7.16LCD row and column drivers

The PCF2119x contains 18 row and 80 column drivers, which connect the appropriate LCD bias voltages in sequence to the display in accordance with the data to be displayed. R17 and R18 drive the icon rows.

The bias voltages and the timing are selected automatically when the number of lines in the display is selected. Figures 10 to 13 show typical waveforms. Unused outputs should be left unconnected.

cursor

MGA801

5 x 7 dot character font

alternating display

cursor display example blink display example

Fig.5 Cursor and blink display examples.

1999 Mar 02

9

Philips Semiconductors	Product specification

LCD controllers/drivers																PCF2119x
handbook, full pagewidth
	upper
lower	4 bits	0000	0001	0010	0011	0100	0101	0110	0111	1000	1001	1010	1011	1100	1101	1110	1111
4 bits
xxxx	0000	1
xxxx	0001	2
xxxx	0010	3
xxxx	0011	4
xxxx	0100	5
xxxx	0101	6
xxxx	0110	7
xxxx	0111	8
xxxx	1000	9
xxxx	1001	10
xxxx	1010	11
xxxx	1011	12
xxxx	1100	13
xxxx	1101	14
xxxx	1110	15
xxxx	1111	16
																	MGL535

Fig.6 Character set ‘R’ in CGROM.

1999 Mar 02

10

Philips Semiconductors	Product specification

LCD controllers/drivers																PCF2119x
	upper
lower	4 bits	0000	0001	0010	0011	0100	0101	0110	0111	1000	1001	1010	1011	1100	1101	1110	1111
4 bits
xxxx	0000	1
xxxx	0001	2
xxxx	0010	3
xxxx	0011	4
xxxx	0100	5
xxxx	0101	6
xxxx	0110	7
xxxx	0111	8
xxxx	1000	9
xxxx	1001	10
xxxx	1010	11
xxxx	1011	12
xxxx	1100	13
xxxx	1101	14
xxxx	1110	15
xxxx	1111	16
																	MGL534

Fig.7 Character set ‘S’ in CGROM.

1999 Mar 02

11

Philips Semiconductors	Product specification

LCD controllers/drivers																PCF2119x
handbook, full pagewidth
	upper
lower	4 bits	0000	0001	0010	0011	0100	0101	0110	0111	1000	1001	1010	1011	1100	1101	1110	1111
4 bits
xxxx	0000	1
xxxx	0001	2
xxxx	0010	3
xxxx	0011	4
xxxx	0100	5
xxxx	0101	6
xxxx	0110	7
xxxx	0111	8
xxxx	1000	9
xxxx	1001	10
xxxx	1010	11
xxxx	1011	12
xxxx	1100	13
xxxx	1101	14
xxxx	1110	15
xxxx	1111	16
																	MGL597

Fig.8 Character set ‘V’ in CGROM.

1999 Mar 02

12

Philips Semiconductors	Product specification
LCD controllers/drivers	PCF2119x

handbook, full pagewidthcharacter codes														CGRAM								character patterns													character code
					(DDRAM data)									address									(CGRAM data)												(CGRAM data)
7			6		5	4	3	2	1	0	6		5	4	3	2	1	0				4	3		2	1			0					4	3	2	1	0
			higher						lower				higher				lower			higher					lower
				order					order				order				order				order				order
				bits					bits				bits				bits				bits					bits
0			0		0	0	0	0	0	0	0		0	0	0	0	0	0											0					1	1	1	1	0
																0	0	1						0	0	0						character		1	0	0	0	1
																0	1	0						0	0	0								1	0	0	0	1
																0	1	1											0			pattern		1	1	1	1	0
																1	0	0						0			0		0		example 1			1	0	1	0	0
																1	0	1						0	0				0					1	0	0	1	0
																1	1	0						0	0		0						cursor	1	0	0	0	1
																1	1	1				0		0	0	0			0					0	0	0	0	0
																																	position	1	0	0	0	1
0			0		0	0	0	0	0	1	0		0	0	1	0	0	0						0	0	0
																0	0	1				0			0				0			character		0	1	0	1	0
																0	1	0																1	1	1	1	1
																0	1	1				0	0				0		0			pattern		0	0	1	0	0
																1	0	0													example 2			1	1	1	1	1
																1	0	1				0	0				0		0					0	0	1	0	0
																1	1	0				0	0				0		0					0	0	1	0	0
																1	1	1				0	0		0		0		0					0	0	0	0	0
0			0		0	0	0	0	1	0	0		0	1	0	0	0	0																			MGE995
																0	0	1
0			0		0	0	1	1	1	1	1		1	1	1	1	0	0
0			0		0	0	1	1	1	1	1		1	1	1	1	0	1
0			0		0	0	1	1	1	1	1		1	1	1	1	1	0
0			0		0	0	1	1	1	1	1		1	1	1	1	1	1

Character code bits 0 to 3 correspond to CGRAM address bits 3 to 6.

CGRAM address bits 0 to 2 designate the character pattern line position. The 8th line is the cursor position and display is performed by logical OR with the cursor. Data in the 8th position will appear in the cursor position.

Character pattern column positions correspond to CGRAM data bits 0 to 4, as shown in Fig.6.

As shown in Figs 6 and 7, CGRAM character patterns are selected when character code bits 4 to 7 are all logic 0. CGRAM data = logic 1 corresponds to selection for display.

Only bits 0 to 5 of the CGRAM address are set by the ‘set CGRAM address’ command. Bit 6 can be set using the ‘set DDRAM address’ command in the valid address range or by using the auto-increment feature during CGRAM write. All bits 0 to 6 can be read using the ‘read busy flag and address counter’ command.

Fig.9 Relationship between CGRAM addresses, data and display patterns.

1999 Mar 02

13

Philips Semiconductors	Product specification
LCD controllers/drivers	PCF2119x

frame n frame n + 1

VLCD V2

ROW 1 V3/V4 V5 VSS

VLCD

V2

ROW 9 V3/V4

V5

VSS

VLCD

V2

ROW 2 V3/V4

V5

VSS

VLCD

V2

COL1 V3/V4

V5

VSS

VLCD

V2

COL2 V3/V4

V5

VSS

VOP

0.5VOP

0.25VOP state 1 0 V

−0.25VOP

−0.5VOP

−VOP

VOP

0.5VOP

0.25VOP state 2 0 V

−0.25VOP

−0.5VOP

−VOP

MGE996

1

2

3

18

1

2

3

18

state 1 (ON)

state 2 (OFF)

R1

R2

R3

R4

R5

R6

R7

R8

R9

Fig.10 MUX 1 : 18 LCD waveforms; character mode.

1999 Mar 02

14

Philips Semiconductors	Product specification
LCD controllers/drivers	PCF2119x

handbook, full pagewidth		frame n	frame n + 1	state 1 (ON)
	VLCD			state 2 (OFF)
	V2			R1
ROW 1	V3/V4			R2
	V5			R3
	VSS			R4
				R5
	VLCD			R6
				R7
	V2			R8
ROW 2	V3/V4
	V5			R9
	VSS

VLCD

V2

ROW 3 V3/V4

V5

VSS

VLCD

V2

COL1 V3/V4

V5

VSS

VLCD

V2

COL2 V3/V4

V5

VSS

VOP

0.5VOP

0.25VOP state 1 0 V

−0.25VOP

−0.5VOP

−VOP

VOP

0.5VOP

0.25VOP

state 2 0 V

−0.25VOP

−0.5VOP

−VOP

1

9

1

9

MGK900

Fig.11 MUX 1 : 9 LCD waveforms; character mode. R10 to 18 to be left open.

1999 Mar 02

15

Philips Semiconductors	Product specification
LCD controllers/drivers	PCF2119x

frame n frame n + 1

VLCD ROW 17 2/3 1/3 VSS

VLCD ROW 18 2/3 1/3 VSS

VLCD ROW 1 to 16 2/3 1/3 VSS

VLCD

2/3 COL 1 ON/OFF 1/3

VSS

VLCD

2/3 COL 2 OFF/ON 1/3

VSS

VLCD

2/3 COL 3 ON/ON 1/3

VSS

VLCD

2/3 COL 4 OFF/OFF 1/3

VSS

only icons are driven (MUX 1 : 2)

MGE997

Fig.12 MUX 1 : 2 LCD waveforms; icon mode.

1999 Mar 02

16

Philips Semiconductors	Product specification
LCD controllers/drivers	PCF2119x

handbook, full pagewidth VPIXEL

	VOP
	2/3 VOP
state 1	1/3 VOP
COL 1 -	0
ROW 17	−1/3 VOP
	−2/3 VOP
	−VOP
	VOP
	2/3 VOP
state 2	1/3 VOP
COL 2 -	0
ROW 17	−1/3 VOP
	−2/3 VOP
	−VOP
	VOP
	2/3 VOP
state 3	1/3 VOP
COL 1 -	0
ROW 1 to 16	−1/3 VOP
	−2/3 VOP
	−VOP

frame n

frame n + 1

state 1 (ON)

state 2 (OFF)

R17

R18

R1-16

state 3 (OFF)

MGE998

VON(rms) = 0.745VOP

VOFF(rms) = 0.333VOP

VON

D = ------------- = 2.23

VOFF

Fig.13 MUX 1 : 2 LCD waveforms; icon mode.

1999 Mar 02

17

Philips Semiconductors	Product specification
LCD controllers/drivers	PCF2119x

7.17Reset function

The PCF2119x must be reset externally when power is turned on. The reset executes a ‘clear display’, requiring 165 oscillator cycles. After the reset the chip has the state shown in Table 4.

Table 4 State after reset

STEP	FUNCTION	CONTROL BIT STATE	CONDITION
1	clear display
2	entry mode set	I/D = 1	+1 (increment)
		S = 0	no shift
3	display control	D = 0	display off
		C = 0	cursor off
		B = 0	cursor character blink off
4	function set	DL = 1	8-bit interface
		M = 0	1-line display
		H = 0	normal instruction set
		SL = 0	MUX 1 : 18 mode
5	default address pointer to DDRAM; the Busy Flag (BF) indicates the busy state (BF = 1) until
	initialization ends; the busy state lasts 2 ms; the chip may also be initialized by software; see
	Tables 17 and 18
6	icon control	IM, IB = 00	icons/icon blink disabled
7	display/screen configuration	L = 0; P = 0; Q = 0	default configurations
8	VLCD temperature coefficient	TC1 = 0; TC2 = 0	default temperature coefficient
9	set VLCD	VA = 0; VB = 0 (VLCD generator off)
10	I2C-bus interface reset

1999 Mar 02

18