Philips PCF2113x Technical data
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PCF2113x
LCD controllers/drivers
Product specification
Supersedes data of 1997 Apr 04
File under Integrated Circuits, IC12
2001 Dec 19
Philips Semiconductors Product specification
LCD controllers/drivers PCF2113x
CONTENTS
1 FEATURES
1.1 Note
2 APPLICATIONS
3 GENERAL DESCRIPTION
4 ORDERING INFORMATION
5 BLOCK DIAGRAM
6 PINNING
7 FUNCTIONAL DESCRIPTION
7.1 LCD supply voltage generator
7.2 LCD bias voltage generator
7.3 Oscillator
7.4 External clock
7.5 Power-on reset
7.6 Power-down mode
7.7 Registers
7.8 Busy flag
7.9 Address Counter (AC)
7.10 Display Data RAM (DDRAM)
7.11 Character Generator ROM (CGROM)
7.12 Character Generator RAM (CGRAM)
7.13 Cursor control circuit
7.14 Timing generator
7.15 LCD row and column drivers
7.16 Reset function
8 INSTRUCTIONS
8.1 Clear display
8.2 Return home
8.3 Entry mode set
8.4 Display control (andpartial Power-down mode)
8.5 Cursor or display shift
8.6 Function set
8.7 Set CGRAM address
8.8 Set DDRAM address
8.9 Read busy flag and read address
8.10 Write data to CGRAM or DDRAM
8.11 Read data from CGRAM or DDRAM
9 EXTENDED FUNCTION SET
INSTRUCTIONS AND FEATURES
9.1 New instructions
9.2 Icon control
9.3 Bit IM
9.4 Bit IB
9.5 Direct mode
9.6 Voltage multiplier control
9.7 Screen configuration
9.8 Display configuration
9.9 Temperature control
9.10 Set V
9.11 Reducing current consumption
10 INTERFACES TO MICROCONTROLLER
10.1 Parallel interface
10.2 I2C-bus interface
11 LIMITING VALUES
12 HANDLING INSTRUCTIONS
13 DC CHARACTERISTICS
14 AC CHARACTERISTICS
15 DEVICE PROTECTION CIRCUITS
16 APPLICATION INFORMATION
16.1 General application information
16.2 4-bit operation, 1-line display using internal
16.3 8-bit operation, 1-line display using internal
16.4 8-bit operation, 2-line display
16.5 I2C-bus operation, 1-line display
17 BONDING PAD INFORMATION
18 TRAY INFORMATION
19 PACKAGE OUTLINE
20 SOLDERING
20.1 Introduction to soldering surface mount
20.2 Reflow soldering
20.3 Wave soldering
20.4 Manual soldering
20.5 Suitability of surface mount IC packages for
21 DATA SHEET STATUS
22 DEFINITIONS
23 DISCLAIMERS
24 BARE DIE DISCLAIMER
25 PURCHASE OF PHILIPS I2C COMPONENTS
LCD
reset
reset
packages
wave and reflow soldering methods
2001 Dec 19 2
Philips Semiconductors Product specification
LCD controllers/drivers PCF2113x
1 FEATURES
• Single-chip LCD controller/driver
• 2-line display of up to 12 characters + 120 icons, or
1-line display of up to 24 characters + 120 icons
• 5 × 7 character format plus cursor; 5 × 8 for kana
(Japanese) and user defined symbols
• Icon mode: reduced current consumption while
displaying
• Icon blink function
• On-chip:
– Configurable 4, 3 or 2 voltage multiplier generating
LCD supply voltage, independent of VDD,
programmable by instruction (external supply also
possible)
– Temperature compensation of on-chip generated
V
: −0.16 to −0.24 %/K (programmable by
LCD
instruction)
– Generation of intermediate LCD bias voltages
– Oscillator requires no external components
(external clock also possible).
• Display data RAM: 80 characters
• Character generator ROM: 240, 5 × 8 characters
• Character generator RAM: 16, 5 × 8 characters;
3 characters used to drive 120 icons, 6 characters used
if icon blink feature is used in application
• 4 or 8-bit parallel bus and 2-wire I2C-bus interface
• CMOS compatible
• 18 row and 60 column outputs
• Multiplex rates 1 : 18 (for normal operation), 1 : 9 (for
single line operation) and 1 : 2 (for icon only mode)
• Uses common 11 code instruction set (extended)
• Logic supply voltage range V
DD1
− V
= 1.8 to 5.5 V
SS1
(chip may be driven with two battery cells)
• V
• Display supply voltage range V
generator supply voltage range
LCD
V
DD2
− V
= 2.2 to 4.0 V
SS2
LCD
− V
= 2.2 to 6.5 V
SS2
• Direct mode to save current consumption for icon mode
and Mux 1 : 9 (depending on V
value and LCD liquid
DD2
properties)
• Very low current consumption (20 to 200 µA):
– Icon mode: <25 µA
– Power-down mode: <2 µA.
1.1 Note
Icon mode is used to save current. When only icons are
displayed, a much lower operating voltage V
LCD
can be
used and the switching frequency of the LCD outputs is
reduced. In most applications it is possible to use VDD as
V
.
LCD
2 APPLICATIONS
• Telecom equipment
• Portable instruments
• Point-of-sale terminals.
3 GENERAL DESCRIPTION
The PCF2113x is a low power CMOS LCD controller and
driver, designed to drive a dot matrix LCD display of 2-line
by 12 or 1-line by 24 characters with 5 × 8 dot format.
All necessary functions for the display are provided in a
single chip, including on-chip generation of LCD bias
voltages, resulting in a minimum of external components
and lower system current consumption. The PCF2113x
interfaces to most microcontrollers via a 4 or 8-bit bus or
via the 2-wire I2C-bus. The chip contains a character
generator and displays alphanumeric and kana
(Japanese) characters. The letter ‘x’ in PCF2113x
characterizes the built-in character set. Various character
sets can be manufactured on request.
2001 Dec 19 3
Philips Semiconductors Product specification
LCD controllers/drivers PCF2113x
4 ORDERING INFORMATION
TYPE NUMBER
NAME DESCRIPTION VERSION
PCF2113AU/10/F4 − chip on flexible film carrier −
PCF2113DU/10/F4 − chip on flexible film carrier −
PCF2113DU/F4 − chip in tray −
PCF2113DH/F4 LQFP100 plastic low profile quad flat package; 100 leads;
body 14 × 14 × 1.4 mm
PCF2113DU/2/F4 − chip with bumps in tray −
PCF2113EU/2/F4 − chip with bumps in tray −
PCF2113WU/2/F4 − chip with bumps in tray −
PACKAGE
SOT407-1
2001 Dec 19 4
Philips Semiconductors Product specification
LCD controllers/drivers PCF2113x
5 BLOCK DIAGRAM
handbook, full pagewidth
V
LCD1
V
LCDSENSE
V
LCD2
V
DD1
V
DD2
V
DD3
V
SS1
V
SS2
BIAS
VOLT AGE
GENERATOR
V
LCD
GENERATOR
SHIFT REGISTER 5 × 12 BIT
CURSOR AND DATA CONTROL
CHARACTER
GENERATOR
RAM (128 × 5)
(CGRAM)
16 CHARACTERS
C1 to C60 R1 to R18
60
COLUMN DRIVERS
60
DATA LATCHES
60
5
5
CHARACTER
GENERATOR
ROM
(CGROM)
240 CHARACTERS
8
SHIFT REGISTER 18-BIT
18
ROW DRIVERS
18
OSCILLATOR
TIMING
GENERATOR
OSC
T1
T2
T3
DB0 to DB3/SA0
7
DATA
REGISTER
(DR)
8
DB4 to DB7
DISPLAY DATA RAM
(DDRAM)
80 CHARACTERS/BYTES
ADDRESS COUNTER
BUSY
FLAG
I/O BUFFER
E
R/W
RS
Fig.1 Block diagram.
7
(AC)
77
INSTRUCTION
DECODER
8
INSTRUCTION
REGISTER(IR)
8
SCL
SDA
PD
7
DISPLAY
ADDRESS
COUNTER
PCF2113x
POWER-ON
RESET
MGE990
2001 Dec 19 5
Philips Semiconductors Product specification
LCD controllers/drivers PCF2113x
6 PINNING
SYMBOL
V
DD1
PIN
PCF2113DH
PCF2113XU
1 1 P supply voltage 1 for all except V
PAD
(1)
TYPE DESCRIPTION
generator
LCD
OSC 2 2 I oscillator/external clock input; note 2
PD 3 3 I power-down select input; for normal operation PD is LOW
T3 − 4 I test pad; open circuit and not user accessible
T1 4 5 I test pin; must be connected to V
T2 − 6 I test pad; must be connected to V
V
SS1
V
SS2
V
LCD2
V
LCDSENSE
V
LCD1
5 7 P ground 1 for all except V
6 8 P ground 2 for V
79OV
output if V
LCD
− 10 I input (V
LCD
LCD
) for voltage multiplier regulation; notes 3 and 7
LCD
LCD
generator
is generated internally; note 7
8 11 I input for generation of LCD bias levels; note 7
SS1
SS1
generator
R9 to R16 9 to 16 12 to 19 O LCD row driver outputs 9 to 16
R18 17 20 O LCD row driver output 18
C60 to C53 18 to 25 21 to 28 O LCD column driver outputs 60 to 53
dummy pad − 29 −
dummy pad − 30 −
C52 to C28 26 to 50 31 to 55 O LCD column driver outputs 52 to 28
dummy pad − 56 −
dummy pad − 57 −
C27 to C3 51 to 75 58 to 82 O LCD column driver outputs 27 to 3
dummy pad − 83 −
dummy pad − 84 −
C2 76 85 O LCD column driver output 2
C1 77 86 O LCD column driver output 1
R8 to R1 78 to 85 87 to 94 O LCD row driver outputs 8 to 1
R17 86 95 O LCD row driver output 17
SCL 87 96 I I
SDA 88 97 I/O I
2
C-bus serial clock input; note 4
2
C-bus serial data input/output; note 4
E 89 98 I data bus clock input; note 4
RS 90 99 I register select input
R/
W 91 100 I read/write input
DB7 92 101 I/O 8-bit bidirectional data bus bit 7; note 5
DB6 93 102 I/O 8-bit bidirectional data bus bit 6
DB5 94 103 I/O 8-bit bidirectional data bus bit 5
DB4 95 104 I/O 8-bit bidirectional data bus bit 4
DB3/SA0 96 105 I/O 8-bit bidirectional data bus bit 3 or I
2
C-bus address pin;
notes 4 and 5
DB2 97 106 I/O 8-bit bidirectional data bus bit 2
DB1 98 107 I/O 8-bit bidirectional data bus bit 1
2001 Dec 19 6
Philips Semiconductors Product specification
LCD controllers/drivers PCF2113x
SYMBOL
PIN
PCF2113DH
PCF2113XU
PAD
(1)
TYPE DESCRIPTION
DB0 99 108 I/O 8-bit bidirectional data bus bit 0
V
V
DD2
DD3
100 109 P supply voltage 2 for V
− 110 P supply voltage 3 for V
generator; note 6
LCD
generator; notes 3 and 6
LCD
Notes
1. Bonding pad location information is given in Chapter 17.
2. When the on-chip oscillator is used this pad must be connected to V
DD1
.
3. In the LQFP100 version this signal is connected internally and can not be accessed at any pin.
4. When the I2C-bus is used, the parallel interface pin E must be LOW. In the I2C-bus read mode DB7 to DB0 should
be connected to V
When the parallel bus is used, the pins SCL and SDA must be connected to V
or left open-circuit.
DD1
SS1
or V
; they must not be left
DD1
open-circuit.
When the 4-bit interface is used without reading out from the PCF2113x (R/W is set permanently to logic 0), the
unused ports DB0 to DB4 can either be set to V
SS1
or V
instead of leaving them open-circuit.
DD1
5. DB7 may be used as the busy flag, signalling that internal operations are not yet completed. In 4-bit operations the
four higher order lines DB7 to DB4 are used; DB3 to DB0 must be left open-circuit except for I2C-bus operations
(see note 4).
6. V
7. When V
and V
DD2
LCD
V
is supplied, pin V
LCD
should always be equal.
DD3
is generated internally, pins V
should be left open-circuit to avoid any stray current, pins V
LCD2
LCD1
, V
LCD2
and V
LCDSENSE
must be connected together. When external
LCD1
and V
LCDSENSE
must be
connected together.
2001 Dec 19 7
Philips Semiconductors Product specification
LCD controllers/drivers PCF2113x
handbook, full pagewidth
DD2
V
DB0
DB1
DB2
DB3/SA0
DB4
DB5
DB6
DB7
V
V
V
V
LCD2
V
LCD1
DD1
OSC
PD
T1
SS1
SS2
R9
R10
R11
R12
R13
R14
R15
R16
R18
C60
C59
C58
C57
C56
C55
C54
C53
R/WRSE
99989796959493929190898887868584838281
100
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
SDA
PCF2113x
SCL
R17R1R2R3R4
R5
R6R7R8C1C2
8079787776
75
C3
C4
74
C5
73
C6
72
71
C7
C8
70
C9
69
C10
68
67
C11
C12
66
C13
65
C14
64
63
C15
C16
62
C17
61
C18
60
59
C19
C20
58
C21
57
C22
56
55
C23
C24
54
C25
53
C26
52
C27
51
26
C52
C51
C50
31323334353637383940414243444546474849
C49
C47
C46
C45
C44
C43
C42
C48
C41
30
29
28
27
Fig.2 Pin configuration (LQFP100).
2001 Dec 19 8
C40
C39
C38
C37
C36
C35
C34
C33
C32
C31
C30
C29
50
C28
MGE989
Philips Semiconductors Product specification
LCD controllers/drivers PCF2113x
7 FUNCTIONAL DESCRIPTION
7.1 LCD supply voltage generator
The LCD supply voltage may be generated on-chip. The
V
generator is controlled by two internal 6-bit registers:
LCD
VAand VB. The nominal LCD operating voltage at room
temperature is given by the relationship:
V
OP(nom)
= (integer value of register × 0.08) + 1.82
7.1.1 PROGRAMMING RANGES
Programmed value: 1 to 63. Voltage: 1.90 to 6.86 V.
T
=27°C.
ref
Values producing more than 6.5 V at operating
temperature are not allowed. Operation above this
voltage may damage the device. When programming the
operating voltage the V
tolerance and temperature
LCD
coefficient must be taken into account.
Values below 2.2 V are below the specified operating
range of the chip and are therefore not allowed.
Value 0 for VAand VB switches the generator off
(i.e. VA= 0 in character mode, VB= 0 in icon mode).
Usually register VA is programmed with the voltage for
character mode and register VB with the voltage for icon
mode.
When V
is generated on-chip the V
LCD
pins should be
LCD
decoupled to VSS with a suitable capacitor.
The generated V
temperature compensated. When the V
is independent of VDD and is
LCD
LCD
generator and
the direct mode are switched off, an external voltage may
besupplied at connected pinsV
V
may be higher or lower than V
LCD2
LCD1
andV
DD2
LCD2.VLCD1
.
and
During direct mode (program DM register bit) the internal
V
generator is turned off and the V
LCD
is directly connected to V
DD2
. This reduces the current
output voltage
LCD2
consumption during icon mode and Mux 1 : 9 (depending
on V
The V
value and LCD liquid properties).
DD2
generator ensures that, as long as VDDis in the
LCD
valid range (2.2 to 4 V), the required peak voltage
VOP= 6.5 V can be generated at any time.
7.2 LCD bias voltage generator
The intermediate bias voltages for the LCD display are
also generated on-chip. This removes the need for an
external resistive bias chain and significantly reduces the
system current consumption. The optimum value of V
LCD
depends on the multiplex rate, the LCD threshold voltage
(Vth) and the number of bias levels. Using a 5-level bias
scheme for 1 : 18 maximum rate allows V
LCD
< 5 V for
most LCD liquids. The intermediate bias levels for the
different multiplex rates are shown in Table 1. These bias
levels are automatically set to the given values when
switching to the corresponding multiplex rate.
Table 1 Bias levels as a function of multiplex rate; note 1
MULTIPLEX
RATE
1:18 5 V
1:9 5 V
1:2 4 V
NUMBER
OF LEVELS
V
LCD
LCD
LCD
1
V
2
3
/
4
3
/
4
2
/
3
Note
1. The values in the table are given relative to V
− VSS, e.g.3/4means3/4× (V
LCD
2001 Dec 19 9
V
3
1
/
2
1
/
2
2
/
3
V
4
1
/
2
1
/
2
1
/
3
− VSS).
LCD
V
5
1
/
4
1
/
4
1
/
3
V
6
V
SS
V
SS
V
SS
Philips Semiconductors Product specification
LCD controllers/drivers PCF2113x
7.3 Oscillator
The on-chip oscillator provides the clock signal for the
display system. No external components are required and
the OSC pin must be connected to V
DD1
.
7.4 External clock
If an external clock is to be used this input is at the OSC
pin. The resulting display frame frequency is given by:
f
=
OSC
------------3072
f
frame
Only in the Power-down mode is the clock allowed to be
stopped (OSC connected to V
), otherwise the LCD is
SS
frozen in a DC state.
7.5 Power-on reset
The on-chip Power-on reset block initializes the chip after
power-onor power failure. This isasynchronous reset and
requires 3 oscillator cycles to be executed.
7.6 Power-down mode
Thechip can be putinto Power-down mode byapplying an
external active HIGH level to the PD pin. In Power-down
mode all static currents are switched off (no internal
oscillator, no bias level generation and all LCD outputs are
internally connected to VSS).
During power-down, information in the RAMs and the chip
state are preserved. Instruction execution during
power-down is possible when pin OSC is externally
clocked.
7.7 Registers
The PCF2113x has two 8-bit registers, an Instruction
Register (IR) and a Data Register (DR). The Register
Select (RS) signal determines which register will be
accessed.The instruction register storesinstruction codes
such as ‘display clear’, ‘cursor shift’, and address
information for the Display Data RAM (DDRAM) and
Character Generator RAM (CGRAM).The instruction
register can be written to but not read from by the system
controller.
The data register temporarily stores data to be read from
the DDRAM and CGRAM. When reading, data from the
DDRAM or CGRAM corresponding to the address in the
instruction register is written to the data register prior to
being read by the ‘read data’ instruction.
7.8 Busy flag
The busy flag indicates the internal status of the
PCF2113x. A logic 1 indicates that the chip is busy and
further instructions will not be accepted. The busy flag is
output to pin DB7 when bit RS = 0 and bit R/
W=1.
Instructions should only be written after checking that the
busy flag is at logic 0 or waiting for the required number of
cycles.
7.9 Address Counter (AC)
The address counter assigns addresses to the DDRAM
and CGRAM for reading and writing and is set by the
commands ‘set CGRAM address’ and ‘set DDRAM
address’. After a read/write operation the address counter
is automatically incremented or decremented by 1.
The address counter contents are output to the bus
(DB6 to DB0) when bit RS = 0 and bit R/W=1.
7.10 Display Data RAM (DDRAM)
The DDRAM stores up to 80 characters of display data
represented by 8-bit character codes. RAM locations
which are not used for storing display data can be used as
general purpose RAM. The basic RAM to display
addressing scheme is shown in Fig.3. With no display shift
the characters represented by the codes in the first
24 RAM locations starting at address 00H in line 1 are
displayed. Figures 4 and 5 show the display mapping for
right and left shift respectively.
When data is written to or read from the DDRAM,
wrap-around occurs from the end of one line to the start of
the next line. When the display is shifted each line wraps
around within itself, independently of the others. Thus all
lines are shifted and wrapped around together.
The address ranges and wrap-around operations for the
various modes are shown in Table 2.
Table 2 Address space and wrap-around operation
MODE 1 × 24 2 × 12 1 × 12
Address space 00 to 4F 00 to 27; 40 to 67 00 to 27
Read/write wrap-around (moves to next line) 4F to 00 27 to 40; 67 to 00 27 to 00
Display shift wrap-around (stays within line) 4F to 00 27 to 00; 67 to 40 27 to 00
2001 Dec 19 10
Philips Semiconductors Product specification
LCD controllers/drivers PCF2113x
handbook, full pagewidth
display
position
DDRAM
address
1-line display
DDRAM
address
2-line display
handbook, halfpage
12345 222324
non-displayed DDRAM addresses
00 01 02 03 04 15 16 17 18 19 4C 4D 4E 4F
non-displayed DDRAM address
12345 101112
00 01 02 03 04 09 0A 0B 0C 0D 24 25 26 27
line 1
12345 101112
64 65 66 6740 41 42 43 44 49 4A 4B 4C 4D
MGE991
line 2
Fig.3 DDRAM to display mapping; no shift.
display
position
DDRAM
address
1-line display
DDRAM
address
2-line display
1 2 3 4 5 22 23 24
4F 00 01 02 03 14 15 16
1 2 3 4 5 10 11 12
27 00 01 02 03
08 09 0A
1 2 3 4 5 10 11 12
67 40 41 42 43
48 49 4A
MGE992
line 1
line 2
Fig.4 DDRAM to display mapping; right shift.
display
handbook, halfpage
position
DDRAM
address
1 2 3 4 5 22 23 24
01 04 05
02 03 16 17 18
1-line display
1 2 3 4 5 10 11 12
02 03
DDRAM
address
01 04 05
1 2 3 4 5 10 11 12
41 42 43 44 45
2-line display
Fig.5 DDRAM to display mapping; left shift.
2001 Dec 19 11
0A 0B 0C
4A 4B 4C
MGE993
line 1
line 2
Philips Semiconductors Product specification
LCD controllers/drivers PCF2113x
7.11 Character Generator ROM (CGROM)
The CGROM generates 240 character patterns in a
5 × 8 dot format from 8-bit character codes.
Figures 7, 8, 9 and 10 show the character sets that are
currently implemented.
7.12 Character Generator RAM (CGRAM)
Up to 16 user defined characters may be stored in the
CGRAM. Some CGRAM characters (see Fig.16) are also
used to drive icons (6 if icons blink and both icon rows are
used in the application; 3 if no blink but both icon rows are
used in the application; 0 if no icons are driven by the icon
rows). The CGROM and CGRAM use a common address
space, of which the first column is reserved for the
CGRAM (see Fig.7). Figure 11 shows the addressing
principle for the CGRAM.
7.13 Cursor control circuit
The cursor control circuit generates the cursor underline
and/or cursor blink as shown in Fig.6 at the DDRAM
address contained in the address counter.
When the address counter contains the CGRAM address
the cursor will be inhibited.
7.14 Timing generator
The timing generator produces the various signals
required to drive the internal circuitry. Internal chip
operation is notdisturbed by operations on thedata buses.
7.15 LCD row and column drivers
The PCF2113x contains 18 row and 60 column drivers,
which connect the appropriate LCD bias voltages in
sequence to the display in accordance with the data to be
displayed. R17 and R18 drive the icon rows.
The bias voltages and the timing are selected
automatically when the number of lines in the display is
selected. Figures 12, 13, 14 and 15 show typical
waveforms. Unused outputs should be left unconnected.
cursor
5 x 7 dot character font alternating display
cursor display example blink display example
Fig.6 Cursor and blink display examples.
2001 Dec 19 12
MGA801
Philips Semiconductors Product specification
LCD controllers/drivers PCF2113x
handbook, full pagewidth
lower
4 bits
xxxx 0000
xxxx 0001
xxxx 0010
xxxx 0011
xxxx 0100
xxxx 0101
xxxx 0110
xxxx 0111
upper
4 bits
0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111
1
2
3
4
5
6
7
8
xxxx 1000
xxxx 1001
xxxx 1010
xxxx 1011
xxxx 1100
xxxx 1101
xxxx 1110
xxxx 1111 16
9
10
11
12
13
14
15
MGE994
Fig.7 Character set ‘A’ in CGROM.
2001 Dec 19 13
Philips Semiconductors Product specification
LCD controllers/drivers PCF2113x
handbook, full pagewidth
lower
4 bits
xxxx 0000
xxxx 0001
xxxx 0010
xxxx 0011
xxxx 0100
xxxx 0101
xxxx 0110
xxxx 0111
upper
4 bits
0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111
1
2
3
4
5
6
7
8
xxxx 1000
xxxx 1001
xxxx 1010
xxxx 1011
xxxx 1100
xxxx 1101
xxxx 1110
xxxx 1111 16
9
10
11
12
13
14
15
MGD688
Fig.8 Character set ‘D’ in CGROM.
2001 Dec 19 14
Philips Semiconductors Product specification
LCD controllers/drivers PCF2113x
handbook, full pagewidth
lower
4 bits
xxxx 0000
xxxx 0001
xxxx 0010
xxxx 0011
xxxx 0100
xxxx 0101
xxxx 0110
xxxx 0111
upper
4 bits
0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111
1
2
3
4
5
6
7
8
xxxx 1000
xxxx 1001
xxxx 1010
xxxx 1011
xxxx 1100
xxxx 1101
xxxx 1110
xxxx 1111 16
9
10
11
12
13
14
15
MGD689
Fig.9 Character set ‘E’ in CGROM.
2001 Dec 19 15
Philips Semiconductors Product specification
LCD controllers/drivers PCF2113x
handbook, full pagewidth
lower
4 bits
xxxx 0000
xxxx 0001
xxxx 0010
xxxx 0011
xxxx 0100
xxxx 0101
xxxx 0110
xxxx 0111
upper
4 bits
0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111
1
2
3
4
5
6
7
8
xxxx 1000
xxxx 1001
xxxx 1010
xxxx 1011
xxxx 1100
xxxx 1101
xxxx 1110
xxxx 1111 16
9
10
11
12
13
14
15
MGU204
Fig.10 Character set ‘W’ in CGROM.
2001 Dec 19 16
Philips Semiconductors Product specification
LCD controllers/drivers PCF2113x
handbook, full pagewidth
character codes
(DDRAM data)
76543210 6543210 43210
higher
order
bits
00000000 0000000 0
00000001 0001
00000010
00001111
00001111
00001111
00001111
lower
order
bits
CGRAM
address
higher
order
bits
010 0000
1
1
1
1
1
1
1
1
1
111
1
1
lower
order
bits
001 000
010 000
011 0
100 0 00
101 00 0
110 000
111 00000
000 000
001 0 0 0
010
100
101 00 00
110 00 00
111 00000
001
1
100
1
101
1
110
1
1
higher
order
bits
character patterns
(CGRAM data)
00 00011
lower
order
bits
character
pattern
example 1
cursor
position
character
pattern
example 2
character code
(CGRAM data)
43210
1
111
1
000
1
000
1111
0010
1
00 01
1
000
1
00
1
000
0
101
1
111
0100
1111
1
01 00
0
010
0
00
0
1
1
0
1
000
1
0
1
0
0
000
MGE995
Character code bits 0 to 3 correspond to CGRAM address bits 3 to 6.
CGRAM address bits 0 to 2 designate the character pattern line position. The 8th line is the cursor position and display is performed by logical ORwith
the cursor. Data in the 8th position will appear in the cursor position.
Character pattern column positions correspond to CGRAM data bits 0 to 4, as shown in this figure.
As shown in Figs 7 and 8, CGRAM character patterns are selected when character code bits 4 to 7 are all logic 0. CGRAM data = logic 1 corresponds
to selection for display.
Only bits 0 to 5 of the CGRAM address are set by the ‘set CGRAM address’ command. Bit 6 can be set using the ‘set DDRAM address’ command in
the valid address range or by using the auto-increment feature during CGRAM write. All bits 0 to 6 can be read using the ‘read busy flag’ and ‘address
counter’ command.
Fig.11 Relationship between CGRAM addresses, data and display patterns.
2001 Dec 19 17
Philips Semiconductors Product specification
LCD controllers/drivers PCF2113x
handbook, full pagewidth
V
LCD
V
2
ROW 1
ROW 9
ROW 2
COL1
COL2
V3/V
V
5
V
SS
V
LCD
V
2
V3/V
V
5
V
SS
V
LCD
V
2
V3/V
V
5
V
SS
V
LCD
V
2
V3/V
V
5
V
SS
V
LCD
V
2
V3/V
V
5
V
SS
frame n + 1 frame n
state 1 (ON)
state 2 (OFF)
R1
4
R2
R3
R4
R5
R6
R7
R8
4
R9
4
4
4
V
OP
0.5V
OP
0.25V
OP
0 V
state 1
−0.25V
OP
−0.5V
OP
−V
OP
V
OP
0.5V
OP
0.25V
OP
0 V
state 2
−0.25V
OP
−0.5V
OP
−V
OP
123 18123 18
Fig.12 MUX 1 : 18 LCD waveforms; character mode.
2001 Dec 19 18
MGE996
Philips Semiconductors Product specification
LCD controllers/drivers PCF2113x
handbook, full pagewidth
V
LCD
V
2
ROW 1
ROW 2
ROW 3
COL1
COL2
V3/V
V
5
V
SS
V
LCD
V
2
V3/V
V
5
V
SS
V
LCD
V
2
V3/V
V
5
V
SS
V
LCD
V
2
V3/V
V
5
V
SS
V
LCD
V
2
V3/V
V
5
V
SS
frame n + 1 frame n
state 1 (ON)
state 2 (OFF)
R1
4
R2
R3
R4
R5
R6
R7
R8
4
R9
4
4
4
V
OP
0.5V
OP
0.25V
OP
0 V
state 1
−0.25V
OP
−0.5V
OP
−V
OP
V
OP
0.5V
OP
0.25V
OP
0 V
state 2
−0.25V
OP
−0.5V
OP
−V
OP
123 9123 9
R10 to R18 to be left open.
Fig.13 MUX1:9LCD waveforms; character mode.
2001 Dec 19 19
MGU217
Philips Semiconductors Product specification
LCD controllers/drivers PCF2113x
handbook, full pagewidth
ROW 17
ROW 18
ROW 1 to 16
COL 1
ON/OFF
COL 2
OFF
/ON
V
V
V
V
V
LCD
2/3
1/3
V
SS
LCD
2/3
1/3
V
SS
LCD
2/3
1/3
V
SS
LCD
2/3
1/3
V
SS
LCD
2/3
1/3
V
SS
frame n + 1 frame n
only icons are
driven (MUX 1 : 2)
V
LCD
V
2/3
1/3
V
SS
LCD
2/3
1/3
V
SS
COL 3
COL 4
ON/ON
OFF/OFF
Fig.14 MUX 1 : 2 LCD waveforms; icon mode.
2001 Dec 19 20
MGE997
Philips Semiconductors Product specification
LCD controllers/drivers PCF2113x
handbook, full pagewidth
state 1
COL 1 -
ROW 17
state 2
COL 2 -
ROW 17
state 3
COL 1 -
ROW 1 to 16
V
PIXEL
2/3 V
1/3 V
−1/3 V
−2/3 V
−V
2/3 V
1/3 V
−1/3 V
−2/3 V
−V
2/3 V
1/3 V
−1/3 V
−2/3 V
−V
frame n + 1 frame n
state 1 (ON)
V
OP
OP
OP
0
state 2 (OFF)
R17
R18
R1-16
OP
OP
state 3 (OFF)
OP
V
OP
OP
OP
0
OP
OP
OP
V
OP
OP
OP
0
OP
OP
OP
MGE998
V
= 0.745V
ON(rms)
V
OFF(rms)
D
V
ON
------------V
OFF
= 0.333V
2.23==
OP
OP
Fig.15 MUX 1 : 2 LCD waveforms; icon mode.
2001 Dec 19 21
Philips Semiconductors Product specification
LCD controllers/drivers PCF2113x
7.16 Reset function
The PCF2113x automatically initializes (resets) when power is turned on. The chipexecutes a reset sequence, including
a ‘clear display’, requiring 165 oscillator cycles. After the reset the chip has the state shown in Table 3.
Table 3 State after reset
STEP FUNCTION CONTROL BIT STATE CONDITIONS
1 clear display
2 entry mode set I/D = 1 +1 (increment)
S = 0 no shift
3 display control D = 0 display off
C = 0 cursor off
B = 0 cursor character blink off
4 function set DL = 1 8-bit interface
M = 0 1-line display
H = 0 normal instruction set
SL = 0 MUX 1 : 18 mode
5 default address pointer to DDRAM; the Busy Flag (BF) indicates the busy state (BF = 1) until
initialization ends; the busy state lasts 2 ms; the chip may also be initialized by software;
see Tables 17 and 18
6 icon control IM = 0; IB = 0; DM = 0 icons, icon blink and direct
mode disabled
7 display/screen configuration L = 0; P = 0; Q = 0 default configurations
8V
9 set V
10 I
11 Set HVgen stages S1 = 1; S0 = 0 V
temperature coefficient TC1 = 0; TC2 = 0 default temperature coefficient
LCD
LCD
2
C-bus interface reset
VA= 0; VB=0 V
generator off
LCD
generator voltage
LCD
multiplier set at factor 4
2001 Dec 19 22
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