Philips PCF2113DU-10-F3, PCF2113DU-F2, PCF2113DU-F3, PCF2113EU-10-F2, PCF2113EU-10-F3 Datasheet

...

DATA SH EET

Product speciﬁcation Supersedes data of 1996 Oct 21 File under Integrated Circuits, IC12

1997 Apr 04

INTEGRATED CIRCUITS

PCF2113x

LCD controller/driver

1997 Apr 04 2

Philips Semiconductors Product speciﬁcation

LCD controller/driver PCF2113x

CONTENTS

1 FEATURES 2 APPLICATIONS 3 GENERAL DESCRIPTION 4 ORDERING INFORMATION 5 BLOCK DIAGRAM 6 PINNING 7 PIN FUNCTIONS 8 FUNCTIONAL DESCRIPTION

8.1 LCD supply voltage generator

8.2 Programming ranges

8.3 LCD bias voltage generator

8.4 Oscillator

8.5 External clock

8.6 Power-on reset

8.7 Power-down mode

8.8 Registers

8.9 Busy Flag

8.10 Address Counter (AC)

8.11 Display Data RAM (DDRAM)

8.12 Character Generator ROM (CGROM)

8.13 Character Generator RAM (CGRAM)

8.14 Cursor control circuit

8.15 Timing generator

8.16 LCD row and column drivers

8.17 Reset function 9 INSTRUCTIONS

9.1 Clear display

9.2 Return home

9.3 Entry mode set

9.3.1 I/D

9.3.2 S

9.4 Display control (and partial power-down mode)

9.4.1 D

9.4.2 C

9.4.3 B

9.5 Cursor/display shift

9.6 Function set

9.6.1 DL (parallel mode only)

9.6.2 M

9.6.3 H

9.7 Set CGRAM address

9.8 Set DDRAM address

9.9 Read busy flag and address

9.10 Write data to CGRAM or DDRAM

9.11 Read data from CGRAM or DDRAM 10 EXTENDED FUNCTION SET

INSTRUCTIONS AND FEATURES

10.1 New instructions

10.2 Icon control

10.3 IM

10.4 IB

10.5 Normal/Icon mode operation

10.6 Screen configuration

10.7 Display configuration

10.8 TC1, TC2

10.9 Set V

LCD

10.10 Reducing current consumption 11 INTERFACE TO MICROCONTROLLER

(PARALLEL INTERFACE)

12 INTERFACE TO MICROCONTROLLER

(I2C-BUS INTERFACE)

12.1 Characteristics of the I2C-bus

12.2 I2C-bus protocol

12.3 Definitions 13 LIMITING VALUES 14 HANDLING 15 DC CHARACTERISTICS 16 AC CHARACTERISTICS 17 TIMING CHARACTERISTICS 18 APPLICATION INFORMATION

18.1 8-bit operation, 1-line display using internal reset

18.2 4-bit operation, 1-line display using internal reset

18.3 8-bit operation, 2-line display

18.4 I2C operation, 1-line display

19 BONDING PAD LOCATIONS 20 PACKAGE OUTLINE 21 SOLDERING

21.1 Introduction

21.2 Reflow soldering

21.3 Wave soldering

21.4 Repairing soldered joints

22 DEFINITIONS 23 LIFE SUPPORT APPLICATIONS 24 PURCHASE OF PHILIPS I2C COMPONENTS

1997 Apr 04 3

Philips Semiconductors Product speciﬁcation

LCD controller/driver PCF2113x

1 FEATURES

• Single-chip LCD controller/driver

• 2-line display of up to 12 characters + 120 icons,

or 1-line display of up to 24 characters + 120 icons

• 5 × 7 character format plus cursor; 5 × 8 for kana (Japanese syllabary) and user defined symbols

• Icon mode: reduced current consumption while displaying icons only

(1)

• Icon blink function

• On-chip:

– generation of LCD supply voltage, programmable by

instruction (external supply also possible)

– temperature compensation of on-chip generated

LCD

: −8to−12 mV/K at 5.0 V

(programmable by instruction) – generation of intermediate LCD bias voltages – oscillator requires no external components

(external clock also possible)

• Display data RAM: 80 characters

• Character generator ROM: 240, 5 × 8 characters

• Character generator RAM: 16, 5 × 8 characters;

3 characters used to drive 120 icons, 6 characters used if icon-blink feature is used in application

• 4 or 8-bit parallel bus and 2-wire I2C-bus interface

• CMOS compatible

• 18 row, 60 column outputs

(1) Icon mode is used to save current. When only icons

are displayed, a much lower operating voltage V

LCD

can be used and the switching frequency of the LCD outputs is reduced. In most applications it is possible to use VDD as V

LCD

. Never use the voltage generator

in icon mode.

• MUX rates 1 : 18 (for normal operation) and 1 : 2 (for icon-only mode)

• Uses common 11 code instruction set (extended)

• Logic supply voltage range, V

− VSS= 1.8 to 4.0 V

(up to 5.5 V if external V

LCD

is used); chip may be driven

with two battery cells

• Display supply voltage range, V

LCD

− VSS= 2.2 to 6.5 V

• Very low current consumption (20 to 200 µA):

– icon mode: <25 µA – power-down mode: <2.5 µA.

2 APPLICATIONS

• Telecom equipment

• Portable instruments

• Point-of-sale terminals.

3 GENERAL DESCRIPTION

The PCF2113x is a low power CMOS LCD controller and driver, designed to drive a dot matrix LCD display of 2 line by 12 and 1 line by 24 characters with 5 × 8 dot format. All necessary functions for the display are provided in a single chip, including on-chip generation of LCD bias voltages, resulting in a minimum of external components and lower system current consumption. The PCF2113x interfaces to most microcontrollers via a 4 or 8-bit bus or via the 2-wire I

C-bus. The chip contains a character generator and displays alphanumeric and kana (Japanese) characters. Three character sets (A, D and E) are currently available (see Figs 7, 8 and 9). Various other character sets can be manufactured on request.

4 ORDERING INFORMATION

TYPE NUMBER

PACKAGE

NAME DESCRIPTION VERSION

PCF2113AU/10/F2 − chip on ﬂexible ﬁlm carrier − PCF2113DU/10/F2 − chip on ﬂexible ﬁlm carrier − PCF2113DU/F2 − chip in tray − PCF2113DH/F2 LQFP100 plastic low proﬁle quad ﬂat package; 100 leads; body

14 × 14 × 1.4 mm

SOT407-1

PCF2113EU/2/F2 − chip with bumps in tray −

1997 Apr 04 4

Philips Semiconductors Product speciﬁcation

LCD controller/driver PCF2113x

5 BLOCK DIAGRAM

Fig.1 Block diagram.

handbook, full pagewidth

MGE990

CURSOR AND DATA CONTROL

SHIFT REGISTER 5 × 12 BIT

DATA LATCHES

COLUMN DRIVERS

CHARACTER GENERATOR

RAM (128 × 5)

(CGRAM)

16 CHARACTERS

CHARACTER GENERATOR

ROM

(CGROM)

240 CHARACTERS

DISPLAY DATA RAM

(DDRAM)

80 CHARACTERS/BYTES

ADDRESS COUNTER

(AC)

INSTRUCTION

DECODER

INSTRUCTION

ROW DRIVERS

SHIFT REGISTER 18-BIT

BIAS

VOLTAGE

GENERATOR

LCD

GENERATOR

BUSY FLAG

DATA

(DR)

I/O BUFFER

OSCILLATOR

TIMING

GENERATOR

DISPLAY ADDRESS COUNTER

POWER-ON

RESET

DD1, 2

LCD2

SS1, 2

LCD1

5, 6

1, 100

C1 to C60 R1 to R18

OSC

PCF2113x

DB0 to DB3/SA0

DB4 to DB7

R/W

SCL

SDA

96 to 99

18 to 77 9 to 17

78 to 86

92 to 95 8887909189

1997 Apr 04 5

Philips Semiconductors Product speciﬁcation

LCD controller/driver PCF2113x

6 PINNING

Notes

1. This is the V

LCD

output pin, if V

LCD

is generated internally and has to be connected to V

LCD1

. If V

LCD1

is generated

externally, V

LCD2

has to be left open or connected to ground.

2. This is the voltage used for the generation of LCD bias levels.

3. This is the supply for the high voltage generator. If V

LCD

is generated externally, connect V

DD2

to VSS.

SYMBOL PIN TYPE DESCRIPTION

DD1

1 P supply voltage for all except high voltage generator OSC 2 I oscillator/external clock input PD 3 I power-down pad input T1 4 I test pad (connected to V

)

SS1

5 P ground for all except high voltage generator V

SS2

6 P ground for high voltage generator V

LCD2

7OV

LCD

output; note 1

LCD1

8IV

LCD

input; note 2 R9 to R16 9 to 16 O LCD row driver outputs 9 to 16 R18 17 O LCD row driver output 18 C60 to C1 18 to 77 O LCD column driver outputs 60 to 1 R8 to R1 78 to 85 O LCD row driver outputs 8 to 1 R17 86 O LCD row driver output 17 SCL 87 I I

C serial clock input

SDA 88 I/O I

C serial data input/output E 89 I data bus clock input RS 90 I register select input R/

W 91 I read/write input DB7 92 I/O 1 bit of 8-bit bidirectional data bus DB6 93 I/O 1 bit of 8-bit bidirectional data bus DB5 94 I/O 1 bit of 8-bit bidirectional data bus DB4 95 I/O 1 bit of 8-bit bidirectional data bus DB3/SA0 96 I/O 1 bit of 8-bit bi-directional data bus/I

C address pin DB2 97 I/O 1 bit of 8-bit bidirectional data bus DB1 98 I/O 1 bit of 8-bit bidirectional data bus DB0 99 I/O 1 bit of 8-bit bidirectional data bus V

DD2

100 P supply voltage for high voltage generator; note 3

1997 Apr 04 6

Philips Semiconductors Product speciﬁcation

LCD controller/driver PCF2113x

Fig.2 Pin configuration (LQFP100).

handbook, full pagewidth

75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52

8079787776

R6R7R8C1C2

C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19 C20 C21 C22 C23 C24 C25 C26 C27

DD1

OSC

SS1

SS2

LCD2

LCD1

R9 R10 R11 R12 R13 R14 R15 R16 R18 C60 C59 C58 C57 C56 C55 C54 C53

C47

C46

C45

C44

C43

C42

C41

C40

C39

C38

C37

C36

C35

C34

C33

C32

C31

C30

C29

C28

DD2

DB0

DB1

DB2

DB3/SA0

DB4

DB5

DB6

DB7

R/WRSE

SDA

SCL

R17R1R2R3R4

C52

C51

C50

C49

C48

100

99989796959493929190898887868584838281

31323334353637383940414243444546474849

PCF2113x

MGE989

1997 Apr 04 7

Philips Semiconductors Product speciﬁcation

LCD controller/driver PCF2113x

7 PIN FUNCTIONS

Note

1. If the 4-bit interface is used without reading out from the PCF2113x (i.e. R/

W is set permanently to logic 0), the

unused ports DB0 to DB3 can either be set to VSS or VDD instead of leaving them open.

NAME FUNCTION DESCRIPTION

RS register select RS selects the register to be accessed for read and write when the device is

controlled by the parallel interface. There is an internal pull-up on this pin.

RS = logic 0 selects the instruction register for write and the Busy Flag and Address Counter for read.

RS = logic 1 selects the data register for both read and write.

W read/write R/W selects either the read (R/W = logic 1) or write (R/W = logic 0) operation when

the device is controlled by the parallel interface. There is an internal pull-up on this pin.

E data bus clock The E pin is set HIGH to signal the start of a read or write operation when the device

is controlled by the parallel interface. Data is clocked in or out of the chip on the negative edge of the clock. Note that this pin must be tied to logic 0 (V

) when

I2C-bus control is used.

DB7 to DB0 data bus The parallel interface of the device. This bi-directional, 3-state data bus transfers

data between the system controller and the PCF2113x. There is an internal pull-up on each of the data lines.

DB7 to DB0 must be connected to V

or left open circuit when I2C-bus control is

used. Note that DB3 shares the same pin as SA0. In 4-bit operations only DB7 to DB4 are used, and DB3 to DB0 must be left open

circuit. See note 1. DB7 may be used as the Busy Flag, signalling that internal operations are not yet

completed.

C1 to C60 column driver

outputs

These pins output the data for columns.

R1 to R18 row driver

outputs

These pins output the row select waveforms to the display. R17 and R18 drive the icons.

LCD

LCD power supply

Positive power supply for the liquid crystal display. This may be generated on-chip or supplied externally.

OSC oscillator When the on-chip oscillator is used this pin must be connected to V

An external clock signal, if used, is input at this pin.

SCL serial clock line Input for the I

C-bus clock signal.

SCL must be connected to V

or VDD when the parallel interface is used.

SDA serial data line I/O for the I

C-bus data line.

SDA must be connected to V

or VDD when the parallel interface is used.

SA0 address pin The hardware sub-address line is used to program the device sub-address for two

different PCF2113xs on the same I

C bus. Note that SA0 shares the same pin as

DB3.

T1 test pad T1 must be connected to V

and is not user accessible.

PD power-down pad PD selects chip power-down mode. For normal operation PD = logic 0.

1997 Apr 04 8

Philips Semiconductors Product speciﬁcation

LCD controller/driver PCF2113x

8 FUNCTIONAL DESCRIPTION (see Fig.1)

8.1 LCD supply voltage generator

The LCD supply voltage may be generated on-chip. The voltage generator is controlled by two internal 6-bit registers, V

and VB. The nominal LCD operating voltage

at room temperature is given by the relationships:

OP(nom)

= [(integer value of register) × 0.08 + 1.9] V

8.2 Programming ranges (T

ref

=27°C)

Programmed value range: 1 to 63. Voltage range: 1.90 to 6.84 V.

Values producing more than 6.5 V at operating temperature are not allowed. Operation above this

voltage may damage the device. When programming the operating voltage the V

LCD

temperature coefficient must

be taken into account.

Values below 2.2 V are below the specified operating range of the chip and are therefore not allowed.

Value 0 for VA and VB switches the generator off.

Usually register V

is programmed with the voltage for character mode and register VB with the voltage for icon mode. VB must be programmed to FF in character mode and VA must be programmed to 00 in icon mode.

When V

LCD

is generated on-chip the V

LCD

pins should be decoupled to VSS with a suitable capacitor. The generated V

LCD

is independent of VDD and is temperature compensated. When the generator is switched off an external voltage may be supplied at connected pins V

LCD1,2

. V

LCD1,2

may be higher or lower than VDD if

external V

LCD

is used. If internally generated it must not

be lower than VDDand .

8.3 LCD bias voltage generator

The intermediate bias voltages for the LCD display are also generated on-chip. This removes the need for an external resistive bias chain and significantly reduces the system current consumption. The optimum value of V

LCD

depends on the multiplex rate, the LCD threshold voltage (Vth) and the number of bias levels and is given by the relationships given in Tables 1 and 2. Using a 5-level bias scheme for 1 : 18 maximum rate allows V

LCD

< 5 V for

most LCD liquids.

4V≤

Table 1 Optimum/maximum values for V

(off pixels start darkening; V

off=Vth

)

Table 2 Minimum values for V

(on pixels clearly visible; Von>Vth)

MUX RATE NUMBER OF LEVELS V

on/Vth

VOP/V

VOP(typical; for Vth= 1.4 V)

1 : 18 5 1.272 3.7 5.2 V 1 : 2 3 2.236 2.283 3.9 V

MUX RATE NUMBER OF LEVELS V

on/Vth

VOP/V

VOP(typical; for Vth= 1.4 V)

1 : 18 5 1.12 3.2 4.6 V 1 : 2 3 1.2 1.5 2.1 V

8.4 Oscillator

The on-chip oscillator provides the clock signal for the display system. No external components are required and the OSC pin must be connected to VDD.

8.5 External clock

If an external clock is to be used this is input at the OSC pin. The resulting display frame frequency is given by

frame

OSC

3072

-------------

Only in the power-down state is the clock allowed to be stopped (OSC connected to V

), otherwise the LCD is

frozen in a DC state.

8.6 Power-on reset

The on-chip power-on reset block initializes the chip after power-on or power failure. This is a synchronous reset and requires 3 OSC cycles to be executed.

1997 Apr 04 9

Philips Semiconductors Product speciﬁcation

LCD controller/driver PCF2113x

8.7 Power-down mode

The chip can be put into power-down mode where all static currents are switched off (no internal oscillator, no bias level generation, all LCD-outputs are internally connected to VSS) when PD = logic 1.

During power-down, the whole chip is reset and will restart with a clear display after power-down. Therefore, the whole chip has to be initialized after a power-down as after initial power- up.

The device should be put into ‘display off’ mode (instruction ‘Display control’) before putting the chip in power-down mode, otherwise the LCD output voltages are not defined.

8.8 Registers

The PCF2113x has two 8-bit registers, an Instruction Register (IR) and a Data Register (DR). The Register Select signal (RS) determines which register will be accessed. The instruction register stores instruction codes such as ‘Display clear’ and ‘Cursor shift’, and address information for the Display Data RAM (DDRAM) and Character Generator RAM (CGRAM). The instruction register can be written from but not read by the system controller. The data register temporarily stores data to be read from the DDRAM and CGRAM. When reading, data from the DDRAM or CGRAM corresponding to the address in the instruction register is written to the data register prior to being read by the ‘Read data’ instruction.

8.9 Busy Flag

The Busy Flag indicates the free/busy status of the PCF2113x. Logic 1 indicates that the chip is busy and further instructions will not be accepted. The Busy Flag is output to pin DB7 when RS = logic 0 and R/

W = logic 1. Instructions should only be written after checking that the Busy Flag is logic 0 or waiting for the required number of cycles.

8.10 Address Counter (AC)

The Address Counter assigns addresses to the DDRAM and CGRAM for reading and writing and is set by the instructions ‘Set CGRAM address’ and ‘Set DDRAM address’. After a read/write operation the Address Counter is automatically incremented or decremented by 1. The Address Counter contents are output to the bus (DB6 to DB0) when RS = logic 0 and R/

W = logic 1.

8.11 Display Data RAM (DDRAM)

The DDRAM stores up to 80 characters of display data represented by 8-bit character codes. RAM locations which are not used for storing display data can be used as general purpose RAM. The basic DDRAM-to-display mapping is shown in Fig.3. With no display shift the characters represented by the codes in the first 24 RAM locations starting at address 00 in line 1 are displayed. Figures 4 and 5 show the display mapping for right and left shift respectively.

When data is written to or read from the DDRAM wrap-around occurs from the end of one line to the start of the next line. When the display is shifted each line wraps around within itself, independently of the others. Thus all lines are shifted and wrapped around together. The address ranges and wrap- around operations for the various modes are shown in Table 3.

Table 3 Address space and wrap-around operation

8.12 Character Generator ROM (CGROM)

The Character Generator ROM (CGROM) generates 240 character patterns in 5 × 8 dot format from 8-bit character codes. Figures 7, 8 and 9 show the character sets that are currently implemented.

8.13 Character Generator RAM (CGRAM)

Up to 16 user defined characters may be stored in the Character Generator RAM (CGRAM). Some CGRAM characters (see Fig.17) are also used to drive icons (6 if icons blink and both icon rows are used in application; 3 if no blink but both icon rows are used in application; 0 if no icons are driven by the icon rows). The CGROM and CGRAM use a common address space, of which the first column is reserved for the CGRAM (see Fig.7). Figure 10 shows the addressing principle for the CGRAM.

MODE 1 × 24 2 × 12

address space 00 to 4F 00 to 27; 40 to 67 read/write wrap-around

(moves to next line)

4F to 00 27 to 40; 67 to 00

display shift wrap-around (stays within line)

4F to 00 27 to 00; 67 to 40

1997 Apr 04 10

Philips Semiconductors Product speciﬁcation

LCD controller/driver PCF2113x

8.14 Cursor control circuit

The cursor control circuit generates the cursor (underline and/or cursor blink as shown in Fig.6) at the DDRAM address contained in the Address Counter. When the Address Counter contains the CGRAM address the cursor will be inhibited.

8.15 Timing generator

The timing generator produces the various signals required to drive the internal circuitry. Internal chip operation is not disturbed by operations on the data buses.

8.16 LCD row and column drivers

The PCF2113x contains 18 row and 60 column drivers, which connect the appropriate LCD bias voltages in sequence to the display in accordance with the data to be displayed. R17 and R18 drive the icon rows.

The bias voltages and the timing are selected automatically when the number of lines in the display is selected. Figures 11, 12 and 13 show typical waveforms. Unused outputs should be left unconnected.

Fig.3 DDRAM-to-display mapping: no shift.

handbook, full pagewidth

00 01 02 03 04 15 16 17 18 19 4C 4D 4E 4F

non-displayed DDRAM addresses

64 65 66 6740 41 42 43 44 49 4A 4B 4C 4D

00 01 02 03 04 09 0A 0B 0C 0D 24 25 26 27

non-displayed DDRAM address

line 1

line 2

MGE991

DDRAM address

2-line display

12345 222324

12345 101112

display position

DDRAM address

1-line display

Fig.4 DDRAM-to-display mapping: right shift.

handbook, halfpage

MGE992

27 00 01 02 03

67 40 41 42 43

08 09 0A

48 49 4A

DDRAM address

line 1

line 2

2-line display

1 2 3 4 5 22 23 24

1 2 3 4 5 10 11 12

4F 00 01 02 03 14 15 16

display position

DDRAM address

1-line display

1997 Apr 04 11

Philips Semiconductors Product speciﬁcation

LCD controller/driver PCF2113x

Fig.5 DDRAM-to-display mapping: left shift.

handbook, halfpage

01 04 05

41 42 43 44 45

0A 0B 0C

4A 4B 4C

DDRAM address

line 1

line 2

2-line display

1 2 3 4 5 22 23 24

1 2 3 4 5 10 11 12

01 04 05

02 03

02 03 16 17 18

display position

DDRAM address

1-line display

MGE993

Fig.6 Cursor and blink display examples.

MGA801

cursor

5 x 7 dot character font alternating display

cursor display example blink display example

1997 Apr 04 12

Philips Semiconductors Product speciﬁcation

LCD controller/driver PCF2113x

Fig.7 Character set ‘A’ in CGROM: PCF2113A.

handbook, full pagewidth

MGE994

0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111

upper

4 bits

lower 4 bits

xxxx 0000

xxxx 0001

xxxx 0010

xxxx 0011

xxxx 0100

xxxx 0101

xxxx 0110

xxxx 0111

xxxx 1000

xxxx 1001

xxxx 1010

xxxx 1011

xxxx 1100

xxxx 1101

xxxx 1110

xxxx 1111 16

1997 Apr 04 13

Philips Semiconductors Product speciﬁcation

LCD controller/driver PCF2113x

Fig.8 Character set ‘D’ in CGROM: PCF2113D.

handbook, full pagewidth

MGD688

0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111

upper

4 bits

lower 4 bits

xxxx 0000

xxxx 0001

xxxx 0010

xxxx 0011

xxxx 0100

xxxx 0101

xxxx 0110

xxxx 0111

xxxx 1000

xxxx 1001

xxxx 1010

xxxx 1011

xxxx 1100

xxxx 1101

xxxx 1110

xxxx 1111 16

1997 Apr 04 14

Philips Semiconductors Product speciﬁcation

LCD controller/driver PCF2113x

Fig.9 Character set ‘E’ in CGROM: PCF2113E.

handbook, full pagewidth

MGD689

0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111

upper

4 bits

lower 4 bits

xxxx 0000

xxxx 0001

xxxx 0010

xxxx 0011

xxxx 0100

xxxx 0101

xxxx 0110

xxxx 0111

xxxx 1000

xxxx 1001

xxxx 1010

xxxx 1011

xxxx 1100

xxxx 1101

xxxx 1110

xxxx 1111 16

1997 Apr 04 15

Philips Semiconductors Product speciﬁcation

LCD controller/driver PCF2113x

Fig.10 Relationship between CGRAM addresses and data and display patterns.

Character code bits 0to 3 correspond to CGRAM address bits 3 to 6. CGRAM address bits 0 to 2 designate the character pattern line position. The 8th line is the cursor position and display is performed by logical OR with

the cursor. Data in the 8

position will appear in the cursor position. Character pattern column positions correspond to CGRAM data bits 0 to 4, as shown in this figure. CGRAM character patterns are selected when character code bits 4 to 7 are all logic 0. CGRAM data = logic 1 corresponds to selection for display. Only bits 0 to 5 of the CGRAM address are set by the ‘set CGRAM address’ instruction. Bit 6 can be set using the ‘set DDRAM address’ instruction in

the valid address range or by using the auto-increment feature during CGRAM write. All bits 0 to 6 can be read using the ‘Read busy flag and address’ instruction.

handbook, full pagewidth

MGE995

76543210 6543210 43210

higher

order

bits

lower order

bits

lower order

bits

higher

order

bits

lower order

bits

higher

order

bits

00000000 0000000 0

001 000 010 000 011 0 100 0 00 101 00 0 110 000 111 00000

000 000 001 0 0 0 010

00 00011 100 101 00 00 110 00 00 111 00000

001

00000001 0001

00000010

00001111 00001111 00001111 00001111

010 0000

100 101 110 1

1 1 1 1

1 1 1 111

character codes

(DDRAM data)

CGRAM address

character patterns

(CGRAM data)

43210

000

111 000

0 0010 00 01 000

1 1

1111

1 1 1

000

1 101

000 111

0 1111 01 00 010

1 1

0100

1 0 0

000

character code (CGRAM data)

character

pattern

example 1

cursor

position

character

pattern

example 2

1997 Apr 04 16

Philips Semiconductors Product speciﬁcation

LCD controller/driver PCF2113x

Fig.11 Typical LCD waveforms; character mode.

handbook, full pagewidth

MGE996

state 1 (ON) state 2 (OFF)

frame n + 1 frame n

123 18123 18

ROW 1

LCD

V3/V

ROW 9

LCD

V3/V

ROW 2

LCD

V3/V

COL1

LCD

V3/V

COL2

LCD

V3/V

0 V

state 1

0.5V

0.25V

−0.25V

−0.5V

−V

0 V

state 2

0.5V

0.25V

−0.25V

−0.5V

−V

R1 R2 R3 R4 R5 R6 R7 R8

1997 Apr 04 17

Philips Semiconductors Product speciﬁcation

LCD controller/driver PCF2113x

Fig.12 MUX 1 : 2 LCD waveforms; icon-mode.

handbook, full pagewidth

MGE997

frame n + 1 frame n

LCD

2/3 1/3

LCD

2/3 1/3

LCD

2/3 1/3

LCD

2/3 1/3

LCD

2/3 1/3

LCD

2/3 1/3

LCD

2/3 1/3

COL 4

OFF/OFF

COL 3

ON/ON

COL 2

OFF

/ON

COL 1

ON/OFF

ROW 1 to 16

ROW 18

ROW 17

only icons are driven (MUX 1 : 2)

1997 Apr 04 18

Philips Semiconductors Product speciﬁcation

LCD controller/driver PCF2113x

Fig.13 MUX 1 : 2 LCD waveforms; icon-mode.

ON(rms)

= 0.745VOP.

OFF(rms)

= 0.333VOP.

OFF

-------------

2.23==

handbook, full pagewidth

MGE998

frame n + 1 frame n

2/3 V

1/3 V

−1/3 V

−2/3 V

−V

2/3 V

1/3 V

−1/3 V

−2/3 V

−V

2/3 V

1/3 V

−1/3 V

−2/3 V

−V

state 3

COL 1 -

ROW 1 to 16

state 2

COL 2 -

ROW 17

state 1

COL 1 -

ROW 17

state 3 (OFF)

R17 R18 R1-16

PIXEL

state 1 (ON) state 2 (OFF)

+ 42 hidden pages