PCF2105MU-2-F1
DATA SH EET
Product specification
Supersedes data of 1997 Dec 08
File under Integrated Circuits, IC12
1998 Jul 30
INTEGRATED CIRCUITS
PCF2105
LCD controller/driver
1998 Jul 30 2
Philips Semiconductors Product specification
LCD controller/driver PCF2105
CONTENTS
1 FEATURES
2 APPLICATIONS
3 GENERAL DESCRIPTION
3.1 Packages
3.2 Available types
4 ORDERING INFORMATION
5 BLOCK DIAGRAM
6 PINNING
7 PAD FUNCTIONS
7.1 RS: Register Select (parallel control)
7.2 R/W: read/write (parallel control)
7.3 E: data bus clock (parallel control)
7.4 DB7 to DB0: data bus (parallel control)
7.5 C60 to C1: column driver outputs
7.6 R32 to R1: row driver outputs
7.7 V
LCD
: LCD power supply
7.8 OSC: oscillator
7.9 SCL: serial clock line
7.10 SDA: serial data line
7.11 SA0: address input
7.12 T1: test input
8 FUNCTIONAL DESCRIPTION
8.1 LCD bias voltage generator
8.2 Oscillator
8.3 External clock
8.4 Power-on reset
8.5 Registers
8.6 Busy flag
8.7 Address Counter (AC)
8.8 Display Data RAM (DDRAM)
8.9 Character Generator ROM (CGROM)
8.10 Character Generator RAM (CGRAM)
8.11 Cursor control circuit
8.12 Timing generator
8.13 LCD row and column drivers
8.14 Programming of the MUX rate 1 : 16
8.15 Programming of the MUX rate 1 : 32
8.16 Reset function
9 INSTRUCTIONS
9.1 Clear display
9.2 Return home
9.3 Entry mode set
9.3.1 I/D
9.3.2 S
9.4 Display control
9.4.1 D
9.4.2 C
9.4.3 B
9.5 Cursor/display shift
9.6 Function set
9.6.1 DL (parallel mode only)
9.6.2 N and M
9.7 Set CGRAM address
9.8 Set DDRAM address
9.9 Read busy flag and address
9.10 Write data to CGRAM or DDRAM
9.11 Read data from CGRAM or DDRAM
10 INTERFACE TO MICROCONTROLLER
(PARALLEL INTERFACE)
11 INTERFACE TO MICROCONTROLLER
(I
2
C-BUS INTERFACE)
11.1 Characteristics of the I
2
C-bus
11.2 Bit transfer
11.3 START and STOP conditions
11.4 System configuration
11.5 Acknowledge
11.6 I
2
C-bus protocol
12 LIMITING VALUES
13 HANDLING
14 DC CHARACTERISTICS
15 AC CHARACTERISTICS
16 TIMING DIAGRAMS
17 APPLICATION INFORMATION
17.1 4-bit operation, 2 × 12 display using internal
reset
17.2 8-bit operation, 2 × 12 display using internal
reset
17.3 8-bit operation, 2 × 24 display
17.4 I
2
C-bus operation, 2 × 12 display
17.5 Initializing by instruction
18 BONDING PAD LOCATIONS
19 DEFINITIONS
20 LIFE SUPPORT APPLICATIONS
21 PURCHASE OF PHILIPS I
2
C COMPONENTS
1998 Jul 30 3
Philips Semiconductors Product specification
LCD controller/driver PCF2105
1 FEATURES
• Single chip Liquid Crystal Display (LCD) controller/driver
• 1 or 2-line display of up to 24 characters per line, or
2 or 4-line display of up to 12 characters per line
• 5 × 7 character format plus cursor; 5 × 8 for kana
(Japanese syllabary) and user-defined symbols
• On-chip generation of intermediate LCD bias voltages
• On-chip oscillator requires no external components
(external clock also possible)
• Display data RAM: 80 characters
• Character generator ROM: 240 characters
• Character generator RAM: 16 characters
• 4 or 8-bit parallel bus or 2-wire I
2
C-bus interface
(400 kHz)
• CMOS and TTL compatible
• 32 row, 60 column outputs
• Multiplex (MUX) rates 1 : 32 and 1 : 16
• Uses common 11-code instruction set
• Logic supply voltage range: V
DD
− V
SS
= 2.5 to 6 V
• Display supply voltage range: V
DD
− V
LCD
= 3.5 to 9 V
• Low power consumption
• I
2
C-bus address selection (SA0): 011101.
2 APPLICATIONS
• Telecom equipment
• Portable instruments
• Point-of-sale terminals.
3 GENERAL DESCRIPTION
The PCF2105 integrated circuit is similar to the PCF2114x
(described in the
“PCF2116 family”
data sheet) but does
not contain the high voltage generator of that device.
Furthermore, a fast I
2
C-bus interface (400 kHz) is
provided.
The PCF2105 is optimized for chip-on-glass applications.
A specific letter code ‘M’ for a character set is programmed
in the Character Generator ROM (CGROM) (see Fig.5).
The PCF2105 is a low power CMOS LCD controller/driver,
designed to drive a split screen dot matrix LCD of
1 or 2 lines by 24 characters or 2 or 4 lines by
12 characters with a 5 × 8 dot format. All necessary
functions for the display are provided in a single chip,
including on-chip generation of LCD bias voltages which
results in a minimum of external components and lower
system power consumption. To allow partial V
DD
shutdown
the ESD protection system of the SCL and SDA pads does
not use a diode connected to V
DD
.
The chip contains a character generator and displays
alphanumeric and kana characters. The PCF2105
interfaces to most microcontrollers via a 4 or 8-bit parallel
bus, or via the 2-wire I
2
C-bus.
3.1 Packages
• PCF2105MU/2: chip with bumps in tray.
3.2 Available types
• PCF2105MU/2: character set ‘M’ in CGROM.
4 ORDERING INFORMATION
TYPE NUMBER
PACKAGE
NAME DESCRIPTION VERSION
PCF2105MU/2 − chip with bumps in tray −
1998 Jul 30 4
Philips Semiconductors Product specification
LCD controller/driver PCF2105
5 BLOCK DIAGRAM
Fig.1 Block diagram.
handbook, full pagewidth
SHIFT REGISTER
32-BIT
MGK846
V
SS
V
DD
CHARACTER
GENERATOR
RAM
(CGRAM)
16
CHARACTERS
CHARACTER
GENERATOR
ROM
(CGROM)
240
CHARACTERS
CURSOR + DATA CONTROL
5
5
SHIFT REGISTER
5 x 12-bit
60
DATA LATCHES
60
COLUMN DRIVERS
6
BIAS
VOLTAGE
GENERATOR
60
32
ROW DRIVERS
8
DISPLAY DATA RAM
(DDRAM) 80 CHARACTERS
32
ADDRESS
COUNTER (AC)
INSTRUCTION
DECODER
INSTRUCTION
REGISTER (IR)
DATA
REGISTER (DR)
BUSY
FLAG
78 8
I/O BUFFER
8
7
7
8
2
111
4
V
LCD
DISPLAY
ADDRESS
COUNTER
POWER - ON
RESET
TIMING
GENERATOR
OSCILLATOR
7
1
OSC
C60 to C1
8
102 to 109 98 100 99
DB7 to DB0 E
RS
R/W
PCF2105
97
SCL
110
SDA
3
SA0
101
T1
21 to 80
(1)
R32 to R1
(1) Pads 5 to 8 and 9 to 12 correspond with symbols R8 to R5 and R32 to R29.
Pads 13 to 20 and 81 to 88 correspond with symbols R24 to R17 and R9 to R16.
Pads 89 to 92 and 93 to 96 correspond with symbols R25 to R28 and R1 to R4.
1998 Jul 30 5
Philips Semiconductors Product specification
LCD controller/driver PCF2105
6 PINNING
SYMBOL PAD I/O DESCRIPTION
OSC 1 I oscillator/external clock input
V
DD
2 − logic supply voltage
SA0 3 I I
2
C-bus address selection input
V
SS
4 − logic ground
R8 to R5 5 to 8 O LCD row driver outputs
R32 to R29 9 to 12 O LCD row driver outputs
R24 to R17 13 to 20 O LCD row driver outputs
C60 to C1 21 to 80 O LCD column driver outputs
R9 to R16 81 to 88 O LCD row driver outputs
R25 to R28 89 to 92 O LCD row driver outputs
R1 to R4 93 to 96 O LCD row driver outputs
SCL 97 I I
2
C-bus serial clock input
E 98 I data bus clock input
RS 99 I register select input
R/
W 100 I read/write input
T1 101 I test input
DB7 to DB0 102 to 109 I/O 8-bit bidirectional data bus input/output
SDA 110 I/O I
2
C-bus serial data input/output
V
LCD
111 I LCD supply voltage input
7 PAD FUNCTIONS
7.1 RS: Register Select (parallel control)
Bit RS selects the register to be accessed for read and
write when the device is controlled by the parallel interface.
RS = 0 selects the instruction register for write and the
busy flag and address counter for read. RS = 1 selects the
data register for both read and write. There is an internal
pull-up resistor on pad RS.
7.2 R/
W: read/write (parallel control)
R/W selects either the read (R/W = 1) or write (R/W=0)
operation when control is by the parallel interface. There is
an internal pull-up resistor on pad R/W.
7.3 E: data bus clock (parallel control)
Pad E should be HIGH to signal the start of a read or write
operation when the device is controlled by the parallel
interface. Data is clocked in or out of the chip on the falling
edge of the clock. Note that pad E must be connected to
V
SS
(logic 0) when I
2
C-bus control is used.
7.4 DB7 to DB0: data bus (parallel control)
The bidirectional, 3-state data bus transfers data between
the system controller and the PCF2105. DB7 acts as the
busy flag, signalling that internal operations are not yet
completed. In 4-bit operations, DB7 to DB4 are used and
DB3 to DB0 must be left open-circuit. There is an internal
pull-up resistor on each of the data lines. Note that
pads DB7 to DB0 must be left open-circuit when I
2
C-bus
control is used.
7.5 C60 to C1: column driver outputs
Pads C60 to C1 output the data for pairs of columns.
This arrangement permits optimized Chip-On-Glass
(COG) layout for 4-line by 12 characters.
7.6 R32 to R1: row driver outputs
Pads R32 to R1 output the row select waveforms to the
left and right halves of the display.
7.7 V
LCD
: LCD power supply
Negative power supply for the liquid crystal display.
1998 Jul 30 6
Philips Semiconductors Product specification
LCD controller/driver PCF2105
7.8 OSC: oscillator
When the on-chip oscillator is used, pad OSC must be
connected to V
DD
. An external clock signal, if used, is input
at pad OSC.
7.9 SCL: serial clock line
Pad SCL is input for the I
2
C-bus clock signal.
7.10 SDA: serial data line
Pad SDA is input/output for the I
2
C-bus data line.
7.11 SA0: address input
The hardware subaddress line is used to program the
device subaddress for 2 different PCF2105s on the same
I
2
C-bus.
7.12 T1: test input
Pad T1 must be connected to V
SS
. Not user accessible.
8 FUNCTIONAL DESCRIPTION
Figure 1 shows the block diagram for the PCF2105.
Details are explained in subsequent sections.
8.1 LCD bias voltage generator
The intermediate bias voltages for the LCD are generated
on-chip. This removes the need for an external resistive
bias chain and significantly reduces the system power
consumption. The optimum levels depend on the multiplex
(MUX) rate and are selected automatically when the
number of lines in the display is defined.
The optimum value of the LCD operating voltage V
OP
depends on the MUX rate, the LCD threshold voltage V
th
and the number of bias levels. The relationships, together
with the discrimination ratio (D) are given in Table 1.
Using a 5-level bias scheme for MUX rate 1 : 16 allows
V
OP
< 5 V for most LCDs. The effect on the display
contrast is negligible.
Table 1 Optimum values for V
OP
MUX
RATE
NUMBER
OF BIAS
LEVELS
1 : 16 5 3.67 1.277
1 : 32 6 5.19 1.196
v
OP
v
th
--------- -
D
V
on
V
off
---------
=
8.2 Oscillator
The on-chip oscillator provides the clock signal for the
display system. No external components are required.
Pad OSC must be connected to V
DD
.
8.3 External clock
If an external clock is to be used, it must be input at
pad OSC. The resulting display frame frequency is given
by
A clock signal must always be present, otherwise the LCD
may be frozen in a DC state.
8.4 Power-on reset
The Power-on reset block initializes the chip after
power-on or power failure.
8.5 Registers
The PCF2105 has two 8-bit registers, an Instruction
Register (IR) and a Data Register (DR). The Register
Select (RS) signal determines which register will be
accessed.
The IR stores instruction codes such as ‘clear display’ and
‘cursor shift’, and address information for the DDRAM
and CGRAM. The system controller can write data to but
can not read data from the instruction register.
The DR temporarily stores data to be read from the
DDRAM and CGRAM. When reading, data from the
DDRAM or CGRAM (corresponding to the address in the
address counter) is written to the DR prior to being read by
the ‘read data’ instruction.
8.6 Busy flag
The Busy Flag (BF) indicates the free or busy status of the
PCF2105. Bit BF = 1 indicates that the chip is busy and
further instructions will not be accepted. The BF is output
at pad DB7 when bit RS = 0 and bit R/
W = 1. Instructions
should only be written after checking that BF = 0 or waiting
for the required number of clock cycles.
8.7 Address Counter (AC)
The AC assigns addresses to the DDRAM and CGRAM for
reading and writing and is set by the instructions ‘set
CGRAM address’ and ‘set DDRAM address’. After a
read/write operation the AC is automatically incremented
or decremented by 1. The AC contents are output to the
bus (pads DB6 to DB0) when bit RS = 0 and bit R/
W =1.
f
frame
f
osc
2304
------------ -
=
1998 Jul 30 7
Philips Semiconductors Product specification
LCD controller/driver PCF2105
8.8 Display Data RAM (DDRAM)
The DDRAM stores up to 80 characters of display data,
represented by 8-bit character codes. DDRAM locations
not used for storing display data can be used as general
purpose RAM. The basic DDRAM-to-display mapping
scheme is shown in Fig.2. With no display shift, the
characters represented by the codes in the first
12 or 24 DDRAM locations, starting at address 00 in
line 1, are displayed. Subsequent lines display data
starting at addresses 20, 40, or 60 hexadecimal (hex).
Figures 3 and 4 show the DDRAM-to-display mapping
scheme when the display is shifted.
The address range for a 1-line display is 00 to 4F; for a
2-line display from 00 to 27 (line 1) and 40 to 67 (line 2);
for a 4-line display from 00 to 13, 20 to 33, 40 to 53 and
60 to 73 for lines 1, 2, 3 and 4 respectively. For 2 and
4-line displays the end address of one line and the start
address of the next line are not successive. When the
display is shifted each line wraps around independently of
the others (see Figs 3 and 4).
When data is written to the DDRAM, wrap-around occurs
from 4F to 00 in 1-line display and from 27 to 40 and
67 to 00 in 2-line display; from 13 to 20, 33 to 40, 53 to 60
and 73 to 00 in 4-line display.
8.9 Character Generator ROM (CGROM)
The CGROM generates 240 character patterns in 5 × 8
dot format from 8-bit character codes. Figure 5 shows the
character set currently available.
8.10 Character Generator RAM (CGRAM)
Up to 16 user-defined characters may be stored in the
CGRAM. The CGROM and CGRAM use a common
address space, of which the first column is reserved for the
CGRAM (see Fig.5). Figure 6 shows the addressing
principle for the CGRAM.
8.11 Cursor control circuit
The cursor control circuit generates the cursor (underline
and/or character blink as shown in Fig.7) at the DDRAM
address contained in the address counter. When the
address counter contains the CGRAM address the cursor
will be inhibited.
8.12 Timing generator
The timing generator produces the various signals
required to drive the internal circuitry. Internal chip
operation is not disturbed by operations on the data buses.
8.13 LCD row and column drivers
The PCF2105 contains 32 row drivers and 60 column
drivers. They connect the appropriate LCD bias voltages in
sequence to the display, in accordance with the data to be
displayed. The bias voltages and the timing are selected
automatically when the number of lines in the display is
selected. Figures 8 and 9 show typical waveforms.
In the 1-line display (MUX rate 1 : 16), the row outputs are
driven in pairs, for example R1/R17 and R2/R18.
This allows the output pairs to be connected in parallel,
thereby providing greater drive capability.
Unused outputs should be left unconnected.
1998 Jul 30 8
Philips Semiconductors Product specification
LCD controller/driver PCF2105
Fig.2 DDRAM-to-display mapping; no shift.
handbook, 4 columns
123456789101112
non-displayed DDRAM addresses
DDRAM
Address
(hex)
4 line display
00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13
20 21 22 23 24 25 26 27 28 29 2A 2B 2C 2D 2E 2F 30 31 32 33
40 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4E 4F 50 51 52 53
60 61 62 63 64 65 66 67 68 69 6A 6B 6C 6D 6E 6F 70 71 72 73
line 1
line 2
line 3
line 4
MLA793
handbook, 4 columns
12345 222324
00 01 02 03 04 15 16 17 18 19 4C 4D 4E 4F
non-displayed DDRAM addresses
Display
Position
(decimal)
DDRAM
Address
(hex)
1-line display
64 65 66 6740 41 42 43 44 55 56 57 58 59
00 01 02 03 04 15 16 17 18 19
24 25 26 27
non-displayed DDRAM address
DDRAM
(hex)
Address
2-line display
line 1
line 2
MLA792
1998 Jul 30 9
Philips Semiconductors Product specification
LCD controller/driver PCF2105
Fig.3 DDRAM-to-display mapping; right shift.
27 00 01 02 03
67 40 41 42 43
14 15 16
54 55 56
DDRAM
Address
(hex)
line 1
line 2
2-line display
1 2 3 4 5 22 23 24
4F 00 01 02 03 14 15 16
Display
Position
(decimal)
DDRAM
Address
(hex)
1-line display
MLA802
13 01 02 03 04 05 06 07 08 09 0A
20 21 22 23 24 25 26 27 28 29 2A33
40 41 42 43 44 45 46 47 48 49 4A53
60 61 62 63 64 65 66 67 68 69 6A73
123456789101112
DDRAM
Address
(hex)
line 1
line 2
line 3
line 4
4-line display
00
MLA803
Fig.4 DDRAM-to-display mapping; left shift.
1 2 3 4 5 22 23 24
0501 02 03 04
16 17 18
41 42 43 44 45 56 57 58
0501 02 03 04
16 17 18
Display
Position
(decimal)
DDRAM
Address
(hex)
DDRAM
Address
(hex)
line 1
line 2
1-line display
2-line display
MLA815
01 02 03 04 05 06 07 08 09 0A 0B 0C
21 22 23 24 25 26 27 28 29 2A 2B 2C
41 42 43 44 45 46 47 48 49 4A 4B 4C
61 62 63 64 65 66 67 68 69 6A 6B 6C
123456789101112
DDRAM
Address
(hex)
line 1
line 2
line 3
line 4
4-line display
MLA816
1998 Jul 30 10
Philips Semiconductors Product specification
LCD controller/driver PCF2105
Fig.5 Character set ‘M’ in CGROM.
handbook, full pagewidth
MGK847
0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111
upper
4 bits
lower
4 bits
xxxx 0000
xxxx 0001
xxxx 0010
xxxx 0011
xxxx 0100
xxxx 0101
xxxx 0110
xxxx 0111
xxxx 1000
xxxx 1001
xxxx 1010
xxxx 1011
xxxx 1100
xxxx 1101
xxxx 1110
xxxx 1111 16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
CG
RAM 1
1998 Jul 30 11
Philips Semiconductors Product specification
LCD controller/driver PCF2105
Fig.6 Relationship between CGRAM addresses, data and display patterns.
Character code bits 0 to 3 correspond to CGRAM address bits 3 to 6.
CGRAM address bits 0 to 2 designate character pattern line position. The 8th line is the cursor position and display is performed by logical OR with the
cursor. Data in the 8th line will appear in the cursor position.
Character pattern column positions correspond to CGRAM data bits 0 to 4; bit 4 being at the left end, as shown in this figure.
CGRAM character patterns are selected when character code bits 4 to 7 are all logic 0. CGRAM data is logic 1 corresponds to selection for display.
Only bits 0 to 5 of the CGRAM address are set by the ‘set CGRAM address’ instruction. Bit 6 can be set using the ‘set DDRAM address’ instruction or
by using the auto-increment feature during CGRAM write. All bits 0 to 6 can be read using the ‘read busy flag and address’ instruction.
handbook, full pagewidth
MGA800 - 1
76543210 6543210 43210
higher
order
bits
lower
order
bits
lower
order
bits
higher
order
bits
lower
order
bits
higher
order
bits
00000000 0000000 0
001 000
010 000
011 0
100 0 00
101 00 0
110 000
111 00000
000 000
001 0 0 0
010
00 00011
100
101 00 00
110 00 00
111 00000
001
00000001 0001
00000010
00001111
00001111
00001111
00001111
010 0000
100
101
110
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
111
character codes
(DDRAM data)
CGRAM
address
character patterns
(CGRAM data)
character
pattern
example 1
cursor
position
character
pattern
example 2
1998 Jul 30 12
Philips Semiconductors Product specification
LCD controller/driver PCF2105
Fig.7 Cursor and blink display examples.
MGA801
cursor
5 x 7 dot character font alternating display
cursor display example blink display example
1998 Jul 30 13
Philips Semiconductors Product specification
LCD controller/driver PCF2105
Fig.8 Typical LCD waveforms; 1-line display.
handbook, full pagewidth
MGA802 - 1
V
DD
V
2
V
V
5
LCD
ROW 1
COL 1
state 1 (ON)
state 2 (ON)
0.25 V
OP
0 V
state 1
1-line display
(1:16)
frame n 1frame n
ROW 9
ROW 2
COL 2
state 2
123 16123 16
34
V /V
V
DD
V
2
V
V
5
LCD
34
V /V
V
DD
V
2
V
V
5
LCD
34
V /V
V
DD
V
2
V
V
5
LCD
34
V /V
V
DD
V
2
V
V
5
LCD
3
4
V /V
0.25 V
OP
0.25 V
OP
0 V
0.25 V
OP
V
OP
V
OP
V
OP
V
OP
1998 Jul 30 14
Philips Semiconductors Product specification
LCD controller/driver PCF2105
Fig.9 Typical LCD waveforms; 2-line display.
handbook, full pagewidth
MGA803 - 1
V
DD
V
2
V
V
V
V
3
4
5
LCD
ROW 1
V
DD
V
2
V
V
V
V
3
4
5
LCD
V
DD
V
2
V
V
V
V
3
4
5
LCD
COL 1
V
DD
V
2
V
V
V
V
3
4
5
LCD
state 1 (ON)
state 2 (ON)
0.15 V
OP
0 V
V
OP
V
OP
V
OP
state 1
2-line display
(1:32)
frame n 1
frame n
ROW 9
ROW 2
COL 2
V
DD
V
2
V
V
V
V
3
4
5
LCD
0.15 V
OP
0.15 V
OP
0 V
0.15 V
OP
V
OP
state 2
123 3212 3 32
1998 Jul 30 15
Philips Semiconductors Product specification
LCD controller/driver PCF2105
8.14 Programming of the MUX rate 1 : 16
With the MUX rate 1 : 16 the PCF2105 can be used in the
following ways:
• To drive a 1-line display of 24 characters
• To drive a 2-line display of 12 characters, resulting in
better contrast. The internal data flow of the chip is
optimized for this purpose.
To program the MUX rate 1 : 16, bits M and N of the
‘function set’ instruction must be set to logic 0
(see Table 3). Figures 10, 11 and 12 show the DDRAM
addresses of the display characters. The second row of
each figure corresponds to either the right half of a 1-line
display or to the second line of a 2-line display. Wrap
around of data during display shift or when writing data is
non-standard.
Fig.10 DDRAM-to-display mapping; no shift.
handbook, full pagewidth
00
01 02
03
04
05 06
07
08
09 0A
0B
1
23
4
5
67
8
9
10 11
12
MLB899
display position
DDRAM address
0C
0D 0E
0F
10
11 12
13
14
15 16
17
13
14 15
16
17
18 19
20
21
22 23
24
display position
DDRAM address
Fig.11 DDRAM-to-display mapping; right shift.
handbook, full pagewidth
4F
00 01
02
03
04 05
06
07
08 09
0A
1
23
4
5
67
8
9
10 11
12
MLB900
display position
DDRAM address
0B
0C 0D
0E
0F
10 11
12
13
14 15
16
13
14 15
16
17
18 19
20
21
22 23
24
display position
DDRAM address
Fig.12 DDRAM-to-display mapping; left shift.
handbook, full pagewidth
01
02 03
04
05
06 07
08
09
0A 0B
0C
1
23
4
5
67
8
9
10 11
12
MLB901
display position
DDRAM address
0D
0E 0F
10
11
12 13
14
15
16 17
18
13
14 15
16
17
18 19
20
21
22 23
24
display position
DDRAM address
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