Philips PCF2104CU-2, PCF2104CU-7, PCF2104LU-2, PCF2104LU-7, PCF2104NU-7 Datasheet

INTEGRATED CIRCUITS

DATA SH EET

PCF2104x

LCD controller/driver

Product specification
Supersedes data of 1997 Apr 01
File under Integrated Circuits, IC12

1997 Dec 16

Philips Semiconductors Product specification

LCD controller/driver PCF2104x

CONTENTS

1 FEATURES
2 APPLICATIONS
3 GENERAL DESCRIPTION

3.1 Packages

3.2 Available types
4 ORDERING INFORMATION
5 BLOCK DIAGRAM
6 PINNING
7 PIN FUNCTIONS

7.1 RS: register select (parallel control)

7.2 R/W: read/write (parallel control)

7.3 E: data bus clock (parallel control)

7.4 DB0 to DB7: data bus (parallel control)

7.5 C1 to C60: column driver outputs

7.6 R1 to R32: row driver outputs

7.7 VLCD: LCD power supply

7.8 OSC: oscillator

7.9 SCL: serial clock line

7.10 SDA: serial data line

7.11 SA0: address pin

7.12 T1: test pad
8 FUNCTIONAL DESCRIPTION

8.1 LCD bias voltage generator

8.2 Oscillator

8.3 External clock

8.4 Power-on reset

8.5 Registers

8.6 Busy Flag

8.7 Address Counter (AC)

8.8 Display data RAM (DDRAM)

8.9 Character generator ROM (CGROM)

8.10 Character generator RAM (CGRAM)

8.11 Cursor control circuit

8.12 Timing generator

8.13 LCD row and column drivers

8.14 Programming of MUX 1 : 16 displays with
PCF2104x

8.15 Programming of MUX 1 : 32 displays with
PCF2104x

8.16 Reset function

9 INSTRUCTIONS

9.1 Clear display

9.2 Return home

9.3 Entry mode set

9.3.1 I/D

9.3.2 S

9.4 Display on/off control

9.4.1 D

9.4.2 C

9.4.3 B

9.5 Cursor/display shift

9.6 Function set

9.6.1 DL (parallel mode only)

9.6.2 N, M

9.7 Set CGRAM address

9.8 Set DDRAM address

9.9 Read busy flag and address

9.10 Write data to CGRAM or DDRAM

9.11 Read data from CGRAM or DDRAM
10 INTERFACE TO MICROCONTROLLER

(PARALLEL INTERFACE)

11 INTERFACE TO MICROCONTROLLER

(I2C-BUS INTERFACE)

11.1 Characteristics of the I2C-bus

11.2 Bit transfer

11.3 Start and stop conditions

11.4 System configuration

11.5 Acknowledge

11.6 I2C-bus protocol
12 LIMITING VALUES
13 HANDLING
14 DC CHARACTERISTICS
15 AC CHARACTERISTICS
16 TIMING DIAGRAMS
17 APPLICATION INFORMATION

17.1 8-bit operation, 2 × 12 display using internal
reset

17.2 4-bit operation, 2 × 12 display using internal
reset

17.3 8-bit operation, 2 × 24 display

17.4 I2C operation, 2 × 12 display

17.5 Initializing by instruction

18 BONDING PAD LOCATIONS
19 DEFINITIONS
20 LIFE SUPPORT APPLICATIONS
21 PURCHASE OF PHILIPS I2C COMPONENTS

1997 Dec 16 2

Philips Semiconductors Product specification

LCD controller/driver PCF2104x

1 FEATURES

• Single chip LCD controller/driver

• 1 or 2-line display of up to 24 characters per line, or

2 or 4 lines of up to 12 characters per line

• 5 × 7 character format plus cursor; 5 × 8 for kana
(Japanese syllabary) and user-defined symbols

• On-chip:
– generation of intermediate LCD bias voltages
– oscillator requires no external components (external

clock also possible)

• Display data RAM: 80 characters

• Character generator ROM: 240 characters

• Character generator RAM: 16 characters

2

• 4 or 8-bit parallel bus or 2-wire I

C-bus interface

• CMOS/TTL compatible

• 32 row, 60 column outputs

• MUX rates 1 : 32 and 1 : 16

• Uses common 11 code instruction set

• Logic supply voltage range, VDD− VSS: 2.5 to 6 V

• Display supply voltage range, VDD− V

: 3.5 to 9 V

LCD

• Low power consumption.

• I2C-bus address: 011101 SA0.

2 APPLICATIONS

• Telecom equipment

• Portable instruments

• Point-of-sale terminals.

3 GENERAL DESCRIPTION

but does not contain the high voltage generator of that
device.

The PCF2104x is optimized for chip-on-glass applications.
The ‘x’ in ‘PCF2104x’ represents a specific letter code for
a character set in the character generator ROM (CGROM).

Two standard character sets are currently available,
specified by the letters ‘C’ and ‘L’ (see Figs 5 and 6).
Other character sets are available on request.

The PCF2104x is a low-power CMOS LCD controller and
driver, designed to drive a split screen dot matrix LCD
display of 1 or 2 lines by 24 characters or 2 or 4 lines by
12 characters with a 5 × 8 dot format. All necessary
functions for the display are provided in a single chip,
including on-chip generation of LCD bias voltages which
results in a minimum of external components and lower
system power consumption. To allow partial V

shutdown

DD

the ESD protection system of the SCL and SDA pins does
not use a diode connected to VDD.

The chip contains a character generator and displays
alphanumeric and kana characters. The PCF2104x
interfaces to most microcontrollers via a 4 or 8-bit bus, or
via the 2-wire I2C-bus.

3.1 Packages

• PCF2104xU/2; chip with bumps in tray

• PCF2104xU/7; chip with bumps on tape.

For further details see Chapter 18.

3.2 Available types

• PCF2104CU/x: character set ‘C’ in CGROM

• PCF2104LU/x: character set ‘L’ in CGROM

• PCF2104NU/x: character set ‘N’ in CGROM.

The PCF2104x integrated circuit is similar to the
PCF2114x (described in the

“PCF2116 family”

data sheet)

4 ORDERING INFORMATION

PACKAGE

TYPE NUMBER

NAME DESCRIPTION VERSION

PCF2104CU/2 − chip with bumps in tray −
PCF2104CU/7 − chip with bumps on tape −
PCF2104LU/2 − chip with bumps in tray −
PCF2104LU/7 − chip with bumps on tape −
PCF2104NU/2 − chip with bumps in tray −
PCF2104NU/7 − chip with bumps on tape −

1997 Dec 16 3

Philips Semiconductors Product specification

LCD controller/driver PCF2104x

5 BLOCK DIAGRAM

handbook, full pagewidth

V

LCD

V

DD

V

SS

T1

111

2

4

101

BIAS

VOLTAGE

GENERATOR

REGISTER (DR)

6

DATA

COLUMN DRIVERS

DATA LATCHES

SHIFT REGISTER

CURSOR + DATA CONTROL

CHARACTER
GENERATOR

RAM

(CGRAM)

16

CHARACTERS

DISPLAY DATA RAM

(DDRAM) 80 CHARACTERS

8

BUSY
FLAG

C1 to C60

80-21

60

60

60

5 x 12-bit

5

5

8

CHARACTER
GENERATOR

ROM

(CGROM)

240

CHARACTERS

7

ADDRESS

COUNTER (AC)

7

INSTRUCTION

DECODER

8

INSTRUCTION
REGISTER (IR)

R1 to R32

5-20
81-96

32

ROW DRIVERS

32

SHIFT REGISTER

32-BIT

PCF2104x

OSCILLATOR

TIMING

GENERATOR

7

DISPLAY
ADDRESS
COUNTER

POWER - ON

RESET

1

OSC

78 8

4

109-106

DB0 to DB3 DB4 to DB7 E

105-102

4

98 100 99

R/W

Fig.1 Block diagram.

1997 Dec 16 4

I/O BUFFER

RS

SCL

97

110

MGC627

SDA3SA0

Philips Semiconductors Product specification

LCD controller/driver PCF2104x

6 PINNING

SYMBOL FFC PAD TYPE DESCRIPTION

OSC 1 I oscillator/external clock input
V

DD

SA0 3 I I
V

SS

R8 to R5 5 to 8 O LCD row driver outputs
R32 to R29 9 to12 O LCD row driver outputs
R24 to R17 13 to 20 O LCD row driver outputs
C60 to C1 21 to 80 O LCD column driver outputs
R9 to R16 81 to 88 O LCD row driver outputs
R25 to R28 89 to 92 O LCD row driver outputs
R1 to R4 93 to 96 O LCD row driver outputs
SCL 97 I I
E 98 I data bus clock input
RS 99 I register select input

W 100 I read/write input

R/
T1 101 I test pad input
DB7 to DB0 102 to 109 I/O 8-bit bidirectional data bus input/output
SDA 110 I/O I
V

LCD

2 P logic supply voltage

2

C-bus address pin input

4 P ground

2

C-bus serial clock input

2

C-bus serial data input/output

111 I LCD supply voltage input

7 PIN FUNCTIONS

7.1 RS: register select (parallel control)

RS selects the register to be accessed for read and write
when the device is controlled by the parallel interface.
RS = logic 0 selects the instruction register for write and
the Busy Flag and Address Counter for read. RS = logic 1
selects the data register for both read and write. There is
an internal pull-up on pin RS.

7.2 R/

W: read/write (parallel control)

R/W selects either the read (R/W = logic 1) or write
(R/W = logic 0) operation when control is by the parallel
interface. There is an internal pull-up on this pin.

7.3 E: data bus clock (parallel control)

The E pin is set HIGH to signal the start of a read or write
operation when the device is controlled by the parallel
interface. Data is clocked in or out of the chip on the
negative edge of the clock. Note that this pin must be tied
to logic 0 (V

) when I2C-bus control is used.

SS

7.4 DB0 to DB7: data bus (parallel control)

The bidirectional, 3-state data bus transfers data between
the system controller and the PCF2104x. DB7 may be
used as the Busy Flag, signalling that internal operations
are not yet completed. In 4-bit operations the 4 higher
order lines DB4 to DB7 are used; DB0 to DB3 must be left
open circuit. There is an internal pull-up on each of the
data lines. Note that these pins must be left open circuit

2

when I

C-bus control is used.

7.5 C1 to C60: column driver outputs

These pins output the data for pairs of columns.
This arrangement permits optimized chip-on-glass (COG)
layout for 4-line by 12 characters.

7.6 R1 to R32: row driver outputs

These pins output the row select waveforms to the left and
right halves of the display.

7.7 V

: LCD power supply

LCD

Negative power supply for the liquid crystal display.

1997 Dec 16 5

Philips Semiconductors Product specification

LCD controller/driver PCF2104x

7.8 OSC: oscillator

When the on-chip oscillator is used, this pin must be
connected to VDD. An external clock signal, if used, is input
at this pin.

7.9 SCL: serial clock line

Input for the I

2

C-bus clock signal.

7.10 SDA: serial data line

Input/output for the I

2

C-bus data line.

7.11 SA0: address pin

The hardware sub-address line is used to program the
device sub-address for 2 different PCF2104xs on the

2

same I

C-bus.

7.12 T1: test pad

Must be connected to V

. Not user accessible.

SS

8 FUNCTIONAL DESCRIPTION (see Fig.1)

8.1 LCD bias voltage generator

The intermediate bias voltages for the LCD display are
also generated on-chip. This removes the need for an
external resistive bias chain and significantly reduces the
system power consumption. The optimum levels depend
on the multiplex rate and are selected automatically when
the number of lines in the display is defined.

The optimum value of V

depends on the multiplex rate,

OP

the LCD threshold voltage (Vth) and the number of bias
levels. The relationships are given in Table 1.

Using a 5-level bias scheme for 1 : 16 MUX rate allows
VOP< 5 V for most LCD liquids. The effect on the display
contrast is negligible.

Table 1 Optimum values for V

MUX

RATE

NUMBER

OF BIAS
LEVELS

VOP/V

OP

DISCRIMINATION

th

Von/V

off

1 : 16 5 3.67 1.277
1 : 32 6 5.19 1.196

8.2 Oscillator

The on-chip oscillator provides the clock signal for the
display system. No external components are required.
Pin OSC must be connected to VDD.

8.3 External clock

If an external clock is to be used, it must be input at
pin OSC. The resulting display frame frequency is given by
f

frame

=1⁄

. A clock signal must always be present,

2304fosc

otherwise the LCD may be frozen in a DC state.

8.4 Power-on reset

The Power-on reset block initializes the chip after
power-on or power failure.

8.5 Registers

The PCF2104x has two 8-bit registers, an instruction
register (IR) and a data register (DR). The register select
signal (RS) determines which register will be accessed.

The instruction register stores instruction codes such as
display clear and cursor shift, and address information for
the Display Data RAM (DDRAM) and Character Generator
RAM (CGRAM). The instruction register can be written to,
but not read from, by the system controller.

The data register temporarily stores data to be read from
the DDRAM and CGRAM. When reading, data from the
DDRAM or CGRAM (corresponding to the address in the
Address Counter) is written to the data register prior to
being read by the ‘Read data’ instruction.

8.6 Busy Flag

The Busy Flag indicates the free/busy status of the
PCF2104x. Logic 1 indicates that the chip is busy and
further instructions will not be accepted. The Busy Flag is
output at pin DB7 when RS = logic 0 and R/

W = logic 1.
Instructions should only be written after checking that the
Busy Flag is at logic 0 or waiting for the required number
of clock cycles.

1997 Dec 16 6

Philips Semiconductors Product specification

LCD controller/driver PCF2104x

8.7 Address Counter (AC)

The Address Counter assigns addresses to the DDRAM
and CGRAM for reading and writing and is set by the
instructions ‘Set CGRAM address’ and
‘Set DDRAM address’. After a read/write operation the
Address Counter is automatically incremented or
decremented by 1. The Address Counter contents are
output to the bus (DB0 to DB6) when RS = logic 0 and
R/W = logic 1.

8.8 Display data RAM (DDRAM)

The DDRAM stores up to 80 characters of display data,
represented by 8-bit character codes. DDRAM locations
not used for storing display data can be used as general
purpose RAM. The basic DDRAM-to-display mapping
scheme is shown in Fig.2. With no display shift, the
characters represented by the codes in the first 12 or 24
RAM locations, starting at address 00 in line 1, are
displayed. Subsequent lines display data starting at
addresses 20, 40, or 60 Hex. Figures 3 and 4 show the
DDRAM-to-display mapping scheme when the display is
shifted.

The address range for a 1-line display is 00 to 4F; for a
2-line display from 00 to 27 (line 1) and 40 to 67 (line 2);
for a 4-line display from 00 to 13, 20 to 33, 40 to 53 and
60 to 73 for lines 1, 2, 3 and 4 respectively. For 2 and
4-line displays the end address of one line and the start
address of the next line are not consecutive. When the
display is shifted each line wraps around independently of
the others (see Figs 3 and 4).

When data is written to the DDRAM wrap-around occurs
from 4F to 00 in 1-line mode and from 27 to 40 and
67 to 00 in 2-line mode; from 13 to 20, 33 to 40, 53 to 60
and 73 to 00 in 4-line mode.

8.10 Character generator RAM (CGRAM)

Up to 16 user-defined characters may be stored in the
character generator RAM. The CGROM and CGRAM use
a common address space, of which the first column is
reserved for the CGRAM (see Fig.5). Figure 8 shows the
addressing principle for the CGRAM.

8.11 Cursor control circuit

The cursor control circuit generates the cursor (underline
and/or character blink as shown in Fig.9) at the DDRAM
address contained in the Address Counter. When the
Address Counter contains the CGRAM address the cursor
will be inhibited.

8.12 Timing generator

The timing generator produces the various signals
required to drive the internal circuitry. Internal chip
operation is not disturbed by operations on the data buses.

8.13 LCD row and column drivers

The PCF2104x contains 32 row and 60 column drivers,
which connect the appropriate LCD bias voltages in
sequence to the display, in accordance with the data to be
displayed. The bias voltages and the timing are selected
automatically when the number of lines in the display is
selected. Figures 10 and 11 show typical waveforms.

In the 1-line mode (1 : 16) the row outputs are driven in
pairs: R1/R17, R2/R18 for example. This allows the output
pairs to be connected in parallel, thereby providing greater
drive capability.

Unused outputs should be left unconnected.

8.9 Character generator ROM (CGROM)

The character generator ROM generates 240 character
patterns in 5 × 8 dot format from 8-bit character codes.
Figures 5 and 6 show the character sets currently
available.

1997 Dec 16 7

Philips Semiconductors Product specification

LCD controller/driver PCF2104x

Display

handbook, 4 columns

Position
(decimal)

DDRAM
Address
(hex)

DDRAM
Address
(hex)

handbook, 4 columns

12345 222324

00 01 02 03 04 15 16 17 18 19 4C 4D 4E 4F

non-displayed DDRAM addresses

1-line display

non-displayed DDRAM address

00 01 02 03 04 15 16 17 18 19

2-line display

24 25 26 27

64 65 66 6740 41 42 43 44 55 56 57 58 59

MLA792

line 1

line 2

non-displayed DDRAM addresses

123456789101112

00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13

line 1

20 21 22 23 24 25 26 27 28 29 2A 2B 2C 2D 2E 2F 30 31 32 33

DDRAM
Address
(hex)

40 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4E 4F 50 51 52 53

60 61 62 63 64 65 66 67 68 69 6A 6B 6C 6D 6E 6F 70 71 72 73

4 line display

Fig.2 DDRAM-to-display mapping; no shift (PCF2104x).

1997 Dec 16 8

line 2

line 3

line 4

MLA793

Philips Semiconductors Product specification

LCD controller/driver PCF2104x

Display
Position
(decimal)

DDRAM
Address
(hex)

DDRAM
Address

(hex)

DDRAM
Address

(hex)

1 2 3 4 5 22 23 24

4F 00 01 02 03 14 15 16

1-line display

27 00 01 02 03

67 40 41 42 43

2-line display

14 15 16

54 55 56

MLA802

123456789101112

13 01 02 03 04 05 06 07 08 09 0A

00

20 21 22 23 24 25 26 27 28 29 2A33

40 41 42 43 44 45 46 47 48 49 4A53

line 1

line 2

line 1

line 2

line 3

Display
Position
(decimal)

DDRAM
Address
(hex)

DDRAM
Address

(hex)

DDRAM
Address

(hex)

1 2 3 4 5 22 23 24

0501 02 03 04

16 17 18

1-line display

0501 02 03 04

41 42 43 44 45 56 57 58

2-line display

16 17 18

MLA815

123456789101112

01 02 03 04 05 06 07 08 09 0A 0B 0C

21 22 23 24 25 26 27 28 29 2A 2B 2C

41 42 43 44 45 46 47 48 49 4A 4B 4C

line 1

line 2

line 1

line 2

line 3

60 61 62 63 64 65 66 67 68 69 6A73

4-line display

MLA803

line 4

Fig.3 DDRAM-to-display mapping; right shift

(PCF2104x).

1997 Dec 16 9

61 62 63 64 65 66 67 68 69 6A 6B 6C

4-line display

MLA816

Fig.4 DDRAM-to-display mapping; left shift

(PCF2104x).

line 4

Philips Semiconductors Product specification

LCD controller/driver PCF2104x

handbook, full pagewidth

lower
4 bits

xxxx 0000

xxxx 0001

xxxx 0010

xxxx 0011

xxxx 0100

xxxx 0101

xxxx 0110

xxxx 0111

upper
4 bits

0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111

CG
RAM 1

2

3

4

5

6

7

8

xxxx 1000

xxxx 1001

xxxx 1010

xxxx 1011

xxxx 1100

xxxx 1101

xxxx 1110

xxxx 1111 16

9

10

11

12

13

14

15

MLB895

Fig.5 Character set ‘C’ in CGROM; PCF2104C.

1997 Dec 16 10

Philips Semiconductors Product specification

LCD controller/driver PCF2104x

handbook, full pagewidth

lower
6 bits

xxxx 0000

xxxx 0001

xxxx 0010

xxxx 0011

xxxx 0100

xxxx 0101

xxxx 0110

xxxx 0111

upper
4 bits

0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111

CG
RAM 1

2

3

4

5

6

7

8

xxxx 1000

xxxx 1001

xxxx 1010

xxxx 1011

xxxx 1100

xxxx 1101

xxxx 1110

xxxx 1111 16

9

10

11

12

13

14

15

MGC629

Fig.6 Character set ‘L’ in CGROM; PCF2104L.

1997 Dec 16 11

Philips Semiconductors Product specification

LCD controller/driver PCF2104x

handbook, full pagewidth

lower
4 bits

xxxx 0000

xxxx 0001

xxxx 0010

xxxx 0011

xxxx 0100

xxxx 0101

xxxx 0110

xxxx 0111

upper
4 bits

0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 11110000

CG
RAM 1

2

3

4

5

6

7

8

xxxx 1000

xxxx 1001

xxxx 1010

xxxx 1011

xxxx 1100

xxxx 1101

xxxx 1110 15

xxxx 1111 16

9

10

11

12

13

14

MGM134

Fig.7 Character set ‘N’ in CGROM; PCF2104N.

1997 Dec 16 12

Philips Semiconductors Product specification

LCD controller/driver PCF2104x

handbook, full pagewidth

76543210 6543210 43210

00000000 0000000 0

00000001 0001

00000010

00001111
00001111
00001111
00001111

character codes

(DDRAM data)

higher

order

bits

lower
order

bits

CGRAM
address

higher

order

bits

010 0000

1

1

1

1

1

1

1

1

1

111

1

1

lower
order

bits

001 000
010 000
011 0
100 0 00
101 00 0
110 000
111 00000

000 000
001 0 0 0
010

100
101 00 00
110 00 00
111 00000

001

1

100

1

101

1

110

1

1

higher

order

bits

character patterns

(CGRAM data)

lower
order

bits

00 00011

MGA800 - 1

character

pattern

example 1

cursor

position

character

pattern

example 2

Character code bits 0to 3 correspond to CGRAM address bits 3 to 6.
CGRAM address bits 0 to 2 designate character pattern line position. The 8th line is the cursor position and display is performed by logical OR with the

cursor. Data in the 8
Character pattern column positions correspond to CGRAM data bits 0 to 4; bit 4 being at the left end, as shown in the figure.
CGRAM character patterns are selected when character code bits 4 to 7 are all logic 0. CGRAM data = logic 1 corresponds to selection for display.
Only bits 0 to 5 of the CGRAM address are set by the ‘Set CGRAM address’ instruction. Bit 6 can be set using the ‘Set DDRAM address’ instruction or

by using the auto-increment feature during CGRAM write. All bits 0 to 6 can be read using the ‘Read Busy Flag and address’ instruction.

th

line will appear in the cursor position.

Fig.8 Relationship between CGRAM addresses, data and display patterns.

1997 Dec 16 13

Philips Semiconductors Product specification

LCD controller/driver PCF2104x

cursor

5 x 7 dot character font alternating display

cursor display example blink display example

Fig.9 Cursor and blink display examples.

MGA801

1997 Dec 16 14

Philips Semiconductors Product specification

LCD controller/driver PCF2104x

handbook, full pagewidth

V

DD

V

2

ROW 1

ROW 9

ROW 2

COL 1

COL 2

V /V

34

V

5

V

LCD

V

DD

V

2

V /V

34

V

5

V

LCD

V

DD

V

2

V /V

34

V

5

V

LCD

V

DD

V

2

V /V

34

V

5

V

LCD

V

DD

V

2

V /V

3

V

5

V

LCD

frame n 1frame n

4

state 1 (ON)
state 2 (ON)

1-line display
(1:16)

V

OP

0.25 V

OP

0 V

state 1

0.25 V

OP

V

OP

V

OP

0.25 V
0 V

0.25 V

V

OP

OP

OP

123 16123 16

state 2

Fig.10 Typical LCD waveforms; 1-line mode.

1997 Dec 16 15

MGA802 - 1

Philips Semiconductors Product specification

LCD controller/driver PCF2104x

handbook, full pagewidth

ROW 1

ROW 9

ROW 2

COL 1

V
V
V
V
V
V

V
V
V
V
V
V

V
V
V
V
V
V

V
V
V
V
V
V

DD
2
3

4
5
LCD

DD
2
3
4
5
LCD

DD
2
3
4
5
LCD

DD
2
3
4
5
LCD

frame n

frame n 1

state 1 (ON)
state 2 (ON)

2-line display
(1:32)

COL 2

state 1

state 2

V
V
V
V
V
V

V

OP

0.15 V
0 V

0.15 V

V

OP

V

OP

0.15 V
0 V

0.15 V

V

OP

DD
2
3
4
5
LCD

OP
OP

OP
OP

123 3212 3 32

Fig.11 Typical LCD waveforms; 2-line mode.

MGA803 - 1

1997 Dec 16 16

Philips Semiconductors Product specification

LCD controller/driver PCF2104x

8.14 Programming of MUX 1 : 16 displays with
PCF2104x

The PCF2104x can be used in the following ways:

• 1-line mode to drive a 2-line display

• 2 × 12 characters with MUX rate 1 : 16, resulting in

better contrast. The internal data flow of the chip is
optimized for this purpose.

handbook, full pagewidth

display position
DDRAM address

display position
DDRAM address

1

00

13
0C

23

01 02

14 15
0D 0E

Fig.12 DDRAM-to-display mapping; no shift (PCF2104x).

4

03

16
0F

Using the ‘Function set’ instruction, M and N are set to 0, 0
(respectively). Figures 12, 13 and 14 show the DDRAM
addresses of the display characters. The second row of
each table corresponds to either the right half of a 1-line
display or to the second line of a 2-line display. Wrap
around of data during display shift or when writing data is
non-standard.

5

04

17
10

67

05 06

18 19
11 12

8

07

20
13

9

08

21
14

10 11
09 0A

22 23
15 16

12
0B

24
17

MLB899

handbook, full pagewidth

handbook, full pagewidth

display position
DDRAM address

display position
DDRAM address

Fig.13 DDRAM-to-display mapping; right shift (PCF2104x).

display position
DDRAM address

display position
DDRAM address

1

4F

13
0B

1

01

13
0D

23

00 01

14 15
0C 0D

23

02 03

14 15
0E 0F

4

02

16
0E

4

04

16
10

5

03

17
0F

5

05

17
11

67

04 05

18 19
10 11

67

06 07

18 19
12 13

8

06

20
12

8

08

20
14

9

07

21
13

9

09

21
15

10 11
08 09

22 23
14 15

10 11
0A 0B

22 23
16 17

12
0A

24
16

MLB900

12
0C

24
18

MLB901

Fig.14 DDRAM-to-display mapping; left shift (PCF2104x).

1997 Dec 16 17