Philips pcd5003 DATASHEETS

INTEGRATED CIRCUITS

DATA SH EET

PCD5003

Advanced POCSAG Paging Decoder

Product speciﬁcation Supersedes data of 1997 Mar 04 File under Integrated Circuits, IC17

1997 Jun 24

Philips Semiconductors Product speciﬁcation

Advanced POCSAG Paging Decoder PCD5003

FEATURES 2 APPLICATIONS 3 GENERAL DESCRIPTION 4 ORDERING INFORMATION 5 BLOCK DIAGRAM 6 PINNING 7 FUNCTIONAL DESCRIPTION

7.1 Introduction

7.2 The POCSAG paging code

7.3 Error correction

7.4 Operating states

7.5 ON status

7.6 OFF status

7.7 Reset

7.8 Bit rates

7.9 Oscillator

7.10 Input data processing

7.11 Battery saving

7.12 Synchronization strategy

7.13 Call termination

7.14 Call data output format

7.15 Sync word indication

7.16 Error type indication

7.17 Data transfer

7.18 Receiver and oscillator control

7.19 External receiver control and monitoring

7.20 Battery condition input

7.21 Synthesizer control

7.22 Serial microcontroller interface

7.23 Decoder I2C-bus access

7.24 External interrupt

7.25 Status/Control register

7.26 Pending interrupts

7.27 Out-of-Range Indication

7.28 Real time clock

7.29 Periodic interrupt

7.30 Received call delay

7.31 Alert generation

7.32 Alert cadence register (03H; write)

7.33 Acoustic alert

7.34 Vibrator alert

7.35 LED alert

7.36 Warbled alert

7.37 Direct alert control

7.38 Alert priority

7.39 Cancelling alerts

7.40 Automatic POCSAG alerts

7.41 SRAM access

7.42 RAM write address pointer (06H; read)

7.43 RAM read address pointer (08H; read/write)

7.44 RAM data output register (09H; read)

7.45 EEPROM access

7.46 EEPROM address pointer (07H; read/write)

7.47 EEPROM data I/O register (0AH; read/write)

7.48 EEPROM access limitations

7.49 EEPROM read operation

7.50 EEPROM write operation

7.51 Invalid write address

7.52 Incomplete programming sequence

7.53 Unused EEPROM locations

7.54 Special programmed function allocation

7.55 Synthesizer programming data

7.56 Identifier storage allocation

7.57 Voltage doubler

7.58 Level-shifted interface

7.59 Signal test mode 8 OPERATING INSTRUCTIONS

8.1 Reset conditions

8.2 Power-on reset circuit

8.3 Reset timing

8.4 Initial programming 9 LIMITING VALUES 10 DC CHARACTERISTICS 11 DC CHARACTERISTICS (WITH VOLTAGE

CONVERTER) 12 OSCILLATOR CHARACTERISTICS 13 EEPROM CHARACTERISTICS 14 AC CHARACTERISTICS 15 APPLICATION INFORMATION 16 PACKAGE OUTLINE 17 SOLDERING

17.1 Introduction

17.2 Reflow soldering

17.3 Wave soldering

17.4 Repairing soldered joints 18 DEFINITIONS 19 LIFE SUPPORT APPLICATIONS 20 PURCHASE OF PHILIPS I2C COMPONENTS

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Philips Semiconductors Product speciﬁcation

Advanced POCSAG Paging Decoder PCD5003

1 FEATURES

• Wide operating supply voltage range: 1.5 to 6.0 V

• EEPROM programming requires only 2.0 V supply

• Low operating current: 50 µA typ. (ON), 25 µA typ. (OFF)

• Temperature range: −25 to +70 °C

•

“CCIR Radio paging Code No. 1”

(POCSAG)

compatible

• 512, 1200 and 2400 bits/s data rates using 76.8 kHz crystal

• Built-in data filter (16-times oversampling) and bit clock recovery



• Advanced ACCESS

synchronization algorithm

• 2-bit random and (optional) 4-bit burst error correction

• Up to 6 user addresses (RICs), each with

4 functions/alert cadences

• Up to 6 user address frames, independently programmable

• Standard POCSAG sync word, plus up to 4 user programmable sync words

• Received data inversion (optional)

• Call alert via beeper, vibrator or LED

• 2-level acoustic alert using single external transistor

• Alert control: automatic (POCSAG type), via cadence

• Separate power control of receiver and RF-oscillator for battery economy

• Synthesizer set-up and control interface (3-line serial)

• On-chip EEPROM for storage of user addresses (RICs),

pager configuration and synthesizer data

• On-chip SRAM buffer for message data

• Slave I

C-bus interface to microcontroller for transfer of message data, status/control and EEPROM programming (data transfer at up to 400 kbits/s)

• Wake-up interrupt for microcontroller, programmable polarity

• Direct and I2C-bus control of operating status (ON/OFF)

• Battery-low indication (external detector)

• Out-of-range condition indication

• Real time clock reference output

• On-chip voltage doubler

• Interfaces directly to UAA2080 and UAA2082 paging

receivers.

2 APPLICATIONS

• Display pagers, basic alert-only pagers

• Information services

• Personal organizers

• Telepoint

• Telemetry/data transmission.

3 GENERAL DESCRIPTION

The PCD5003 is a very low power POCSAG decoder and pager controller. It supports data rates of 512, 1200 and 2400 bits/s using a single 76.8 kHz crystal. On-chip EEPROM is programmable using a minimum supply voltage of 2.0 V, allowing ‘over-the-air’ programming.

The PCD5003 is fast I

C-bus compatible

(maximum 400 kbits/s).

4 ORDERING INFORMATION

TYPE

NUMBER

NAME DESCRIPTION VERSION

PACKAGE

PCD5003H LQFP32 plastic low proﬁle quad ﬂat package; 32 leads; body 7 × 7 × 1.4 mm SOT358-1 PCD5003U/10 − ﬁlm-frame carrier (naked die) 32 pads −

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Philips Semiconductors Product speciﬁcation

Advanced POCSAG Paging Decoder PCD5003

5 BLOCK DIAGRAM

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30 31

15 14 13

MLC244

RST

SDA SCL

INT

BAT

VIB LED

ATL ATH

ALC

REF CCN

CCP V

ZSD ZSC

ZLE

RXE

ROE

RDI

DON

TS1 TS2

XTAL1 XTAL2

26 27

SYNTHESIZER

24 25

DATA FILTER

16 20

18 17

CONTROL

RECEIVER

CONTROL

AND

CLOCK

RECOVERY

CLOCK

CONTROL

TEST

CONTROL

EEPROM CONTROL

DECODING

DATA

CONTROL

MAIN DECODER

MASTER DIVIDER

OSCILLATOR

EEPROM

POCSAG

SYNCHRONIZATION

TIMER

REFERENCE

PCD5003

RAM

CONTROL

RAM

VDDV

RESET

SET-UP

I C-BUS

CONTROL

REGISTERS

AND

INTERRUPT

CONTROL

ALERT

GENERATION

AND

CONTROL

VOLTAGE DOUBLER

AND LEVEL

SHIFTER

12, 2911

Fig.1 Block diagram.

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Advanced POCSAG Paging Decoder PCD5003

6 PINNING

SYMBOL PIN DESCRIPTION

ATL 1 alert LOW level output ALC 2 alert control input

(normally LOW by internal pull-down)

DON 3 direct ON/OFF input

(normally LOW by internal pull-down)

REF 4 real time clock frequency reference

output INT 5 interrupt output n.c. 6 not connected RST 7 reset input

(normally LOW by internal pull-down) V

SDA 9 I SCL 10 I V

CCP 14 voltage converter shunt capacitor

CCN 15 voltage converter shunt capacitor

TS1 16 test input 1

XTAL2 17 decoder crystal oscillator output XTAL1 18 decoder crystal oscillator input n.c. 19 not connected TS2 20 test input 2

BAT 21 battery sense input n.c. 22 not connected RDI 23 received POCSAG data input RXE 24 receiver circuit enable output ROE 25 receiver oscillator enable output ZSD 26 synthesizer serial data output ZSC 27 synthesizer serial clock output ZLE 28 synthesizer latch enable output V

VIB 30 vibrator motor drive output LED 31 LED drive output ATH 32 alert HIGH level output

8 external positive voltage reference

input

C-bus serial data input/output

C-bus serial clock input 11 main positive supply voltage 12 main negative supply voltage 13 voltage converter positive output

(positive side)

(negative side)

(normally LOW by internal pull-down)

29 main negative supply voltage

LED

VIB

PCD5003H

11 DD

SCL

ZLE

ZSC

ZSD

CCP

CCN

ROE 25

TS1

24 23 22 21 20 19 18 17

MLC245

ATL

ALC

DON

REF

INT

n.c. RST V

ATH 32

1 2

3 4 5 6 7 8

SDA

Fig.2 Pin configuration for SOT358-1 (LQFP32).

RXE RDI n.c. BAT TS2 n.c. XTAL1 XTAL2

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Philips Semiconductors Product speciﬁcation

Advanced POCSAG Paging Decoder PCD5003

7 FUNCTIONAL DESCRIPTION

7.1 Introduction

The PCD5003 is a very low power decoder and pager controller specifically designed for use in new generation radio pagers. The architecture of the PCD5003 allows for flexible application in a wide variety of radio pager designs.

The PCD5003 is fully compatible with

Code No. 1”

at data rates of 512, 1200 and 2400 bits/s using a single oscillator crystal of 76.8 kHz.

In addition to the standard POCSAG sync word the PCD5003 is also capable of recognizing up to 4 User Programmable Sync Words (UPSWs). This permits the reception of both private services and POCSAG transmissions via the same radio channel.

Used together with the Philips UAA2080 or UAA2082 paging receiver, the PCD5003 offers a highly sophisticated, miniature solution for the radio paging market. Control of an RF synthesizer circuit is also provided to ease alignment and channel selection.

On-chip EEPROM provides storage for user addresses (Receiver Identity Codes or RICs) and Special Programmed Functions (SPFs), which eliminates the need for external storage devices and interconnection. For other non-volatile storage 20 bytes of general purpose EEPROM are available. The low EEPROM programming voltage makes the PCD5003 well- suited for ‘over-the-air’ programming/reprogramming.

On request from an external controlling device or automatically (by SPF programming), the PCD5003 will provide standard POCSAG alert cadences by driving a standard acoustic ‘beeper’. Non-standard alert cadences may be generated via a cadence register or a dedicated control input.

The PCD5003 can also produce a HIGH level acoustic alert as well as drive an LED indicator and a vibrator motor via external bipolar transistors.

The PCD5003 contains a low-power, high-efficiency voltage converter (doubler) designed to provide a higher voltage supply to LCD drivers or microcontrollers. In addition, an independent level shifted interface is provided allowing communication to a microcontroller operating at a higher voltage than the PCD5003.

Interface to such an external device is provided by an I2C-bus which allows received call identity and message data, data for the programming of the internal EEPROM, alert control and pager status information to be transferred

(also known as the POCSAG code) operating

“CCIR Radio paging

between the devices. Pager status includes features provided by the PCD5003 such as battery-low and out-of-range indications. A dedicated interrupt line minimizes the required microcontroller activity.

A selectable low frequency timing reference is provided for use in real time clock functions.

Data synchronization is achieved by the Philips patented ACCESS made of the POCSAG code structure particularly in fading radio signal conditions. The algorithm allows for data synchronization without preamble detection whilst minimizing battery power consumption.

Random and (optional) burst error correction techniques are applied to the received data to optimize on call success rate without increasing falsing rate beyond specified POCSAG levels.

7.2 The POCSAG paging code

A transmission using the (POCSAG code) is constructed in accordance with the following rules (see Fig.3).

The transmission is started by sending a preamble, consisting of at least 576 continuously alternating bits (10101010...). The preamble is followed by an arbitrary number of batch blocks. Only complete batches are transmitted.

Each batch comprises 17 codewords of 32 bits each. The first codeword is a synchronization codeword with a fixed pattern. The sync word is followed by 8 frames (0 to 7) of 2 codewords each, containing message information. A codeword in a frame can either be an address, message or idle codeword.

Idle codewords also have a fixed pattern and are used to fill empty frames or to separate messages.

Address codewords are identified by an MSB of logic 0 and are coded as shown in Fig.3. A user address or RIC consists of 21 bits. Only the upper 18 bits are encoded in the address codeword (bits 2 to 19). The lower 3 bits designate the frame number (0 to 7) in which the address is transmitted.

Four different call types (‘numeric’, ‘alphanumeric’ and two ‘alert only’ types) can be distinguished on each user address. The call type is determined by two function bits in the address codeword (bits 20 and 21), as shown in Table 1.



algorithm ensuring that maximum advantage is

“CCIR Radio paging Code No. 1”

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Advanced POCSAG Paging Decoder PCD5003

Alert-only calls only consist of a single address codeword. Numeric and alphanumeric calls have message codewords following the address. A message causes the frame structure to be temporarily suspended. Message codewords are sent until the message is completed, with only the sync words being transmitted in their expected positions.

Message codewords are identified by an MSB of logic 1 and are coded as shown in Fig.3. The message information is stored in a 20-bit field (bits 2 to 21). The data format is determined by the call type: 4 bits per digit for numeric messages and 7 bits per (ASCII) character for alphanumeric messages.

handbook, full pagewidth

PREAMBLE BATCH 1 BATCH 2 BATCH 3 LAST BATCH

10101 . . . 10101010

Each codeword is protected against transmission errors by 10 CRC check bits (bits 22 to 31) and an even-parity bit (bit 32). This permits correction of maximum 2 random errors or up to 3 errors in a burst of 4 bits (a 4-bit burst error) per codeword.

The POCSAG standard recommends the use of combinations of data formats and function bits, as given in Table 1. Other (non-standard) combinations will be received normally by the PCD5003. Message data is not deformatted.

SYNC | CW CW | CW CW | . . . . . | CW CW

FRAME 0 FRAME 1 FRAME 7

Address code-word

Message code-word

0 18-bit address 2 function bits 10 CRC bits P

1 20-bit message 10 CRC bits P

Fig.3 POCSAG code structure.

Table 1 POCSAG recommendedcall types and function bits

BIT 20 (MSB) BIT 21 (LSB) CALL TYPE DATA FORMAT

0 0 numeric 4-bits per digit 0 1 alert only 1 − 1 0 alert only 2 − 1 1 alphanumeric 7-bits per ASCII character

MCD456

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Advanced POCSAG Paging Decoder PCD5003

7.3 Error correction Table 2 Error correction

ITEM DESCRIPTION

Preamble 4 random errors in 31 bits Synchronization codeword 2 random errors in 32 bits Address codeword 2 random errors, plus: 4-bit burst errors (optional) Message codeword 2 random errors, plus: 4-bit burst errors (optional)

In the PCD5003 error correction methods have been implemented as shown in Table 2.

Random error correction is default for both address and message codewords. In addition, burst error correction can be enabled by SPF programming. Up to 3 erroneous bits in a 4-bit burst can be corrected.

The error type detected for each codeword is identified in the message data output to the microcontroller, allowing rejection of calls with too many errors.

7.4 Operating states

The PCD5003 has 2 operating states:

• ON status

• OFF status.

The operating state is determined by a Direct Control input (DON) and bit D4 in the control register (see Table 3).

Table 3 Truth table for decoder operating status

DON INPUT

CONTROL BIT

OPERATING

STATUS

0 0 OFF 01ON 10ON 11ON

7.5 ON status

In ON status the decoder pulses the receiver and oscillator enable outputs (respectively RXE and ROE) according to the code structure and the synchronization algorithm. Data received serially at the data input (RDI) is processed for call receipt. Reception of a valid paging call is signalled to the microcontroller by means of an interrupt signal. The received address and message data can then be read

via the I

C-bus interface.

7.6 OFF status

In OFF status the decoder will neither activate the receiver or oscillator enable outputs, nor process any data at the data input. The crystal oscillator remains active to permit communication with the microcontroller.

In both operating states an accurate timing reference is available via the REF output. By SPF programming the signal periodicity may be selected as 32.768 kHz, 50 Hz, 2 Hz or1⁄60Hz.

7.7 Reset

The decoder can be reset by applying a positive pulse on input pin RST. A power-on reset circuit consisting of an RC network can be connected to this input as well. Conditions during and after a reset are described in Chapter “Operating instructions”.

For successful reset at power-on, a HIGH level must be present on the RST pin while the device is powering-up. This can be applied by the microcontroller, or via a suitable RC power-on reset circuit connected to the RST input. Reset circuit details and conditions during and after a reset are described in Chapter 8

7.8 Bit rates

The PCD5003 can be configured for data rates of 512, 1200 or 2400 bit/s by SPF programming. These data rates are derived from a single 76.8 kHz oscillator frequency.

7.9 Oscillator

The oscillator circuit is designed to operate at 76.8 kHz. Typically, a tuning fork crystal will be used as a frequency source. Alternatively, an external clock signal can be applied to pin XTAL1 (amplitude = V

to VSS), but a

slightly higher oscillator current is consumed. A 2.2 MΩ feedback resistor connected between XTAL1 and XTAL2 is required for proper operation.

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Philips Semiconductors Product speciﬁcation

Advanced POCSAG Paging Decoder PCD5003

To allow easy oscillator adjustment (e.g. by means of a variable capacitor) a 32.768 kHz reference frequency can be selected at output REF by SPF programming.

7.10 Input data processing

Data input is binary and fully asynchronous. Input bit rates of 512, 1200 and 2400 bits/s are supported. As a programmable option, the polarity of the received data can be inverted before further processing.

The input data is noise filtered by means of a digital filter. Data is sampled at 16 times the data rate and averaged by majority decision.

The filtered data is used to synchronize an internal clock generator by monitoring transitions. The recovered clock phase can be adjusted in steps of

⁄8 or1⁄32bit period per

received bit. The larger step size is used when bit synchronization has

not been achieved, the smaller when a valid data sequence has been detected (e.g. preamble or sync word).

7.11 Battery saving

Current consumption is reduced by switching off internal decoder sections whenever the receiver is not enabled.

To further increase battery efficiency, reception and decoding of an address codeword is stopped as soon as the uncorrected address field differs by more than 3 bits from the enabled RICs. If the next codeword must be received again, the receiver is re-enabled thus observing the programmed establishment times t

RXE

and t

RDE

The current consumption of the complete pager can be minimized by separately activating the RF oscillator circuit (at output ROE) before activating the rest of the receiver. This is possible with the UAA2082 receiver which has external biasing for the oscillator circuit.

7.12 Synchronization strategy

In ON status the PCD5003 synchronizes to the POCSAG



data stream by means of the Philips ACCESS

algorithm. A flow diagram is shown in Fig.4. Where ‘sync word’ is used, this implies both the standard POCSAG sync word and any enabled User Programmable Sync Word (UPSW).

Several modes of operation can be distinguished depending on the synchronization state. Each mode uses a different method to obtain or retain data synchronization. The receiver and oscillator enable outputs (respectively RXE and ROE) are switched accordingly, with the

appropriate establishment times (respectively t t

ROON

RXON

and

Before comparing received data with preamble, an enabled sync word or programmed user addresses, the appropriate error correction is applied.

Initially, after switching to ON status, the decoder is in switch-on mode. Here the receiver will be enabled for a period up to 3 batches, testing for preamble and sync word. Failure to detect preamble or sync word will cause switching to ‘carrier off’ mode.

Detection of preamble switches to preamble receive mode, in which sync word is looked for. The receiver will remain enabled while preamble is detected. When neither sync word nor preamble is found within 1 batch duration ‘carrier off’ mode is entered.

Upon detection of a sync word the data receive mode is entered. The receiver is activated only during enabled user address frames and sync word periods. When an enabled user address has been detected, the receiver will be kept enabled for message codeword reception until the call termination criteria are met.

During call reception data bytes are stored in an internal SRAM buffer, capable of storing 2 batches of message data.

Messages are transmitted contiguously, only interrupted by sync words at the beginning of each batch. When a message extends beyond the end of a batch, no testing for sync takes place. Instead, a message data transfer will be initiated by an interrupt to the external controller. Data reception continues normally after a period corresponding to the sync word duration.

If any message codeword is found to be uncorrectable, ‘data-fail’ mode is entered and no data transfer will be attempted at the next sync word position. Instead, a test for sync word will be carried out.

In the data fail mode message reception continues normally for 1 batch duration. Upon detection of sync word at the expected position the decoder returns to ‘data receive’ mode. If sync word again fails to appear, batch synchronization is deemed lost. Call reception is then terminated and ‘fade recovery’ mode is entered.

The fade recovery mode is intended to scan for sync word and preamble over an extended window (nominal position ±8 bits).

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Advanced POCSAG Paging Decoder PCD5003

This is done for a period of up to 15 batches, allowing recovery of synchronization from long fades in the radio signal. Detection of preamble switches to ‘preamble receive’ mode, while sync word detection switches to ‘data receive’ mode. When neither is found within a period of 15 batches, the radio signal is considered lost and ‘carrier off’ mode is entered.

The purpose of carrier off mode is to detect a valid radio transmission and synchronize to it quickly and efficiently. Because transmissions may start at random, the decoder enables the receiver for 1 codeword in every 18 codewords looking for preamble or sync word. By using a buffer containing 32 bits (n bits from the current scan, 32 − n from the previous scan) effectively every batch bit position can be tested within a continuous transmission of at least 18 batches. Detection of preamble switches to ‘preamble receive’ mode, while sync word detection switches to ‘data receive’ mode.

7.13 Call termination

Call reception is terminated:

• Upon reception of any address codeword (including Idle

codeword) requiring no more than single bit error correction

• In ‘data fail’ mode, when a sync word is not found at the

expected batch position

• When a forced call termination command is received

from an external controller.

The last method permits an external controller to stop call reception depending on the number and type of errors which occurred in a call. After a forced call termination the decoder will enter ‘data fail’ mode.

The formats of a call header, a message data block and a call terminator are shown in Tables 4, 6 and 8.

A Call Header contains information on the last sync word received, the RIC which began call reception and the type of error correction performed on the address codeword.

A Message Data block contains the data bits from a message codeword plus the type of error correction performed. No deformatting is done on the data bits: numeric data appear as 4-bit groups per digit, alphanumeric data have a 7-bit ASCII representation.

The Call Terminator contains information on the last sync word received, information on the way the call was terminated (forced call termination command, loss of sync word in ‘data fail’ mode) and the type of error correction performed on the terminating codeword.

7.15 Sync word indication

The sync word recognized by the PCD5003 is shown in the call header (bits S3 to S1). The decimal value represents the identifier number in the EEPROM of the UPSW in question. A value of 7 indicates the standard POCSAG sync word.

7.16 Error type indication

Table 10 shows how the different types of detected errors are encoded in the call data output format.

A message codeword containing more than a single bit error (bit E3 = 1) may appear as an address codeword (bit M1 = 0) after error correction. In this event the codeword is processed as message data and does not cause call termination.

The type of error correction as well as the call termination conditions are indicated by status bits in the message data output.

Following call termination, transfer of the data received since the previous sync word period is initiated by means of an interrupt to the external controller.

7.14 Call data output format

POCSAG call information is stored in the decoder SRAM in blocks of 3 bytes per codeword. Each stored call consists of a call header, followed by message data blocks and concluded by a call terminator. In the event of concatenated messages the call terminator is replaced with the call header of the next message. An alert-only call only has a call header and a call terminator.

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7.17 Data transfer

Data transfer is initiated either during sync word periods or as soon as the receiver is disabled after call termination. If the SRAM buffer is full, data transfer is initiated immediately during the next codeword.

When the PCD5003 is ready to transfer received call data an external interrupt will be generated via output INT. Any message data can be read by accessing the RAM output register via the I output starting from the position indicated by the RAM read pointer.

C-bus interface. Bytes will be

Philips Semiconductors Product speciﬁcation

Advanced POCSAG Paging Decoder PCD5003

handbook, full pagewidth

no preamble or sync word

(3 batches)

no preamble or sync word

(1 batch)

sync word

OFF to ON status

switch-on

preamble receive

data receive

data fail

no preamble or sync word (1 batch)

fade recovery

no preamble or sync word (15 batches)

carrier off

preamble

sync word

no sync wordsync word

preamble

preamblesync word

MLC247

Fig.4 ACCESS synchronization algorithm.

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Table 4 Call header format

BYTE NUMBER

1 0 S3 S2 S1 R3 R2 R1 DF 2 0 S3 S2 S1 R3 R2 R1 0 3 X X F0F1E3E2E1 0

Table 5 Call header bit identiﬁcation

BITS (MSB to LSB) IDENTIFICATION

S3 to S1 identiﬁer number of sync word for current batch (7 = standard POCSAG) R3 to R1 identifier number of user address (RIC)

DF data fail mode indication (1 = data fail mode); note 1

F0 and F1 function bits of received address codeword (bits 20, 21)

E3 to E1 detected error type; see Table 10; E3 = 0 in a concatenated call header

Note

1. The DF bit in the call header is set:

a) When the sync word of the batch in which the (beginning of the) call was received, did not match the standard

POCSAG or a user-programmed sync word. The sync word identifier (bits S3 to S1) will then be made 0.

b) When any codeword of a previous call received in the same batch was uncorrectable.

Table 6 Message data format

BIT 7

(MSB)

BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1

BIT 0

(LSB)

BYTE NUMBER

1 M2M3M4M5M6M7M8M9 2 M10 M11 M12 M13 M14 M15 M16 M17 3 M18 M19 M20 M21 E3 E2 E1 M1

Table 7 Message data bit identiﬁcation

BITS (MSB to LSB) IDENTIFICATION

M2 to M21 message codeword data bits

E3 to E1 detected error type; see Table 10

M1 message codeword flag

Table 8 Call terminator format

BYTE NUMBER

1 FTS3S2S1 0 0 0 DF 2 FTS3S2S1 0 0 0 X 3 XXXXE3E2E10

BIT 7

(MSB)

BIT 7

(MSB)

BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1

BIT 0

(LSB)

BIT 0

(LSB)

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Table 9 Call terminator bit identiﬁcation

BITS (MSB to LSB) IDENTIFICATION

FT forced call termination (1 = yes)

S3 to S1 identifier number of last sync word

DF data fail mode indication (1 = data fail mode); note 1

E3 to E1 detected error type; see Table 10; E3 = 0 in a call terminator

Note

1. The DF bit in the call terminator is set:

a) When any call data codeword in the terminating batch was uncorrectable, while in ‘data receive’ mode. b) When the sync word at the start of the terminating batch did not match the standard POCSAG or a

user-programmed sync word, while in ‘data fail’ mode.

Table 10 Error type identiﬁcation (note 1)

E3 E2 E1

0 0 0 no errors - correct codeword 0 0 0 1 parity bit in error 1 0 1 0 single bit error 1 + parity 0 1 1 single bit error and parity error 1 1 0 0 not used 1 0 1 4-bit burst error and parity error 3 (e.g.1101) 1 1 0 2-bit random error 2 1 1 1 uncorrectable codeword 3 or more

Note

1. POCSAG code allows a maximum of 3 bit errors to be detected per codeword.

Successful call termination occurs by reception of a valid address codeword with less than 2 bit errors. Unsuccessful termination occurs when sync word is not detected while in ‘data fail’ mode.

It is generally possible to distinguish these two conditions using the sync word identifier number (bits S3 to S1); the identifier number will be non-zero for correct termination, and zero for sync word failure.

Only when a call is received in ‘data fail’ mode and the call is terminated before the end of the batch, is it not possible to distinguish unsuccessful from correct termination.

Reception of message data can be terminated at any time by transmitting a forced call termination command to the control register via the I2C-bus. Any call received will then be terminated immediately and ‘data fail’ mode will be entered.

ERROR TYPE

7.18 Receiver and oscillator control

A paging receiver and an RF oscillator circuit can be controlled independently via enable outputs RXE and ROE respectively. Their operating periods are optimized according to the synchronization mode of the decoder. Each enable signal has its own programmable establishment time (see Table 11).

7.19 External receiver control and monitoring

An external controller may enable the receiver control outputs continuously via an I the normal enable pattern. Data reception continues normally. This mode can be left by means of a reset or an I2C-bus command.

External monitoring of the receiver control output RXE is possible via bit D6 in the status register, when enabled via the control register (D2 = 1). Each change of state of output RXE will generate an external interrupt at output INT.

NUMBER OF ERRORS

C-bus command, overruling

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Philips Semiconductors Product speciﬁcation

Advanced POCSAG Paging Decoder PCD5003

7.20 Battery condition input

A logic signal from an external sense circuit signalling battery condition can be applied to the BAT input. This input is sampled each time the receiver is disabled (RXE ↓ 0).

When enabled via the control register (D2 = 0), the condition of input BAT is reflected in bit D6 of the status register. Each change of state of bit D6 causes an external interrupt at output INT.

When using the UAA2080 pager receiver a battery-low condition corresponds to a logic HIGH-level. With a different sense circuit the reverse polarity can be used as well, because every change of state is signalled to an external controller.

After a reset the initial condition of the battery-low indicator in the status register is zero.

Table 11 Receiver and oscillator establishment times

(note 1)

CONTROL

OUTPUT

ESTABLISHMENT TIME UNIT

RXE 5 10 15 30 ms ROE 20 30 40 50 ms

Note

1. The exact values may differ slightly from the above

values, depending on the bit rate (see Table 22).

7.21 Synthesizer control

Control of an external frequency synthesizer is possible via a dedicated 3-line serial interface (outputs ZSD, ZSC and ZLE). This interface is common to a number of available synthesizers. The synthesizer is enabled using the oscillator enable output ROE.

The frequency parameters must be programmed in EEPROM. Two blocks of maximum 24 bits each can be stored. Any unused bits must be programmed at the beginning of a block: only the last bits are used by the synthesizer.

When the function is selected by SPF programming (SPF byte 01, bit D6), data is transferred to the synthesizer each time the PCD5003 is switched from OFF to ON status. Transfer takes place serially in two blocks, starting with bit 0 (MSB) of block 1 (see Table 25).

Data bits on ZSD change on the falling flanks of ZSC. After clocking all bits into the synthesizer, a latch enable pulse

copies the data to the internal divider registers. A timing diagram is given in Fig.5.

The data output timing is synchronous, but has a pause in the bit stream of each block. This pause occurs in the 13th bit while ZSC is LOW. The nominal pause duration t depends on the programmed bit rate for data reception and is shown in Table 12. The total duration of the 13th bit is given by t

ZCL+tp

A similar pause occurs between the first and the second data block. The delay between the first latch enable pulse and the second data block is given by t

ZDL2+tp

. The complete start-up timing of the synthesizer interface is given in Fig.12.

Table 12 Synthesizer programming pause

BIT RATE (bit/s) tp (clocks) tp (µs)

512 119 1549 1200 33 430 2400 1 13

7.22 Serial microcontroller interface

The PCD5003 has an I

C-bus serial microcontroller interface capable of operating at 400 kbits/s. The PCD5003 is a slave transceiver with a 7-bit I2C-bus address 39 (bits A6 to A0 = 0100111). Together with the R/W bit the first byte of an I2C-bus message then becomes 4EH (write) or 4FH (read).

Data transmission requires 2 lines: SDA (data) and SCL (clock), each with an external pull-up resistor. The clock signal (SCL) for any data transmission must be generated by the external controlling device.

A transmission is initiated by a start condition (S: SCL = 1, SDA = ↓) and terminated by a stop condition (P: SCL = 1, SDA = ↑).

Data bits must be stable when SCL is HIGH. If there are multiple transmissions, the stop condition can be replaced with a new start condition.

Data is transferred on a byte basis, starting with a device address and a read/write indicator. Each transmitted byte must be followed by an acknowledge bit ACK (active LOW). If a receiving device is not ready to accept the next complete byte, it can force a bus wait state by holding SCL LOW.

The general I2C-bus transmission format is shown in Fig.6. Formats for master/slave communication are shown in Fig.7.

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+ 30 hidden pages

Philips pcd5003 DATASHEETS

Specifications and Main Features

Frequently Asked Questions

User Manual

CONTENTS

1 FEATURES

2 APPLICATIONS

3 GENERAL DESCRIPTION

4 ORDERING INFORMATION

5 BLOCK DIAGRAM

6 PINNING

7 FUNCTIONAL DESCRIPTION

7.1 Introduction

7.2 The POCSAG paging code

7.3 Error correction Table 2 Error correction

7.4 Operating states

7.5 ON status

7.6 OFF status

7.7 Reset

7.8 Bit rates

7.9 Oscillator

7.10 Input data processing

7.11 Battery saving

7.12 Synchronization strategy

7.13 Call termination

7.15 Sync word indication

7.16 Error type indication

7.14 Call data output format

7.17 Data transfer

7.18 Receiver and oscillator control

7.19 External receiver control and monitoring

7.20 Battery condition input

7.21 Synthesizer control

7.22 Serial microcontroller interface