Philips PCA24S08 Technical data

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PCA24S08

1024 × 8-bit CMOS EEPROM
with access protection

Product data 2004 May 10

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Philips Semiconductors Product data

PCA24S081024 × 8-bit CMOS EEPROM with access protection

DESCRIPTION

The PCA24S08 provides 8192 bits of serial electrically erasable and
programmable Read-only memory (EEPROM) organized as
1024 words of 8 bits each. Data bytes are received and transmitted
via the serial I

Access permissions limiting reads or writes are set via the I2C-bus
to isolate blocks of memory from improper access.

The PCA24S08 is intended to be pin compatible with standard
24C08 serial EEPROM devices except for pins 1, 2, and 3, which
are address pins in the standard part. Other exceptions to the
PCA24C08 serial EEPROM datasheet are noted the “Serial
EEPROM Exception” section later in this document.

All bits are sent to or read from the device, most significant bit first,
in a manner consistent with the 24C08 serial EEPROM. The bit
fields in this document are correspondingly listed with the MSB on
the left and the LSB on the right.

The EEPROM memory is broken up into 8 blocks of 1 k bits
(128 bytes) each. Within each block, the memory is physically
organized in to 8 pages of 128 bits (16 bytes) each. In addition to
these 8 k bits, there are two more 128-bit pages that are used to
store the access protection and ID information. There are a total of
8448 bits of EEPROM memory available in the PCA24S08.

Access protection (both read and write) is organized on a block
basis for blocks 1 through 7 and on a page and a block basis for
block 0. Protection information for these blocks and pages is stored
in one of the additional pages of EEPROM memory that is
addressed separately from the main data storage array. See
“Access Protection” for more details.

The ID value (see “ID Configuration”) is located in the ID page of the
EEPROM, the second of the additional 16 byte pages.

Writes from the serial interface may include from one to 16 bytes at
a time, depending on the protocol followed by the bus master. All
page accesses must be properly aligned to the internal EEPROM
page.

The EEPROM memory offers an endurance of 100,000 write cycles
per byte, with 10 year data retention. Writes to the EEPROM take
less than 5 ms to complete.

After manufacturing, all EEPROM bits will be set to a value of ‘1’.

2

C-bus.

FEATURES

• Non-volatile storage of 8 kbits organized as 8 blocks of 128 bytes

each

2

• I

C interface logic

• Compatible with 24C08 Serial EEPROM, and alternate source of

Atmel AT24RF08C without the RF interface

• Write operation:

– Byte write mode
– 16-byte page write mode

• Read operation:

– Sequential read
– Random read

• Programmable access protection to limit reads and writes

• Lock/unlock function

• Write protect feature protecting the full memory array against write

operations

• Self timed write cycle

• Internal power-on reset

• High reliability:

– Ten years non-volatile data retention time
– 100,000 write cycle endurance

• Low power CMOS technology

• Operating power supply voltage range of 2.5 V to 3.6 V

• 0 to 400 kHz clock frequency

• ESD protection exceeds 2000 V HBM per JESD22-A114,

200 V MM per JESD22-A115 and 1000 V CDM per JESD22-C101

• Latch-up testing is done to JEDEC Standard JESD78 which

exceeds 100 mA

• Packages offered: SO8, TSSOP8

ORDERING INFORMATION

PACKAGES TEMPERATURE RANGE ORDER CODE TOPSIDE MARK DRAWING NUMBER

8-pin plastic SO –40 °C to +85 °C PCA24S08D P24S08 SOT96-1

8-pin plastic TSSOP –40 °C to +85 °C PCA24S08DP PS08 SOT505-1

Standard packing quantities and other packaging data are available at www.philipslogic.com/packaging.

2004 May 10

2

Philips Semiconductors Product data

PCA24S081024 × 8-bit CMOS EEPROM with access protection

PIN CONFIGURATION

1

n.c.

2

n.c.

3

PROT

45

GND

Figure 1. 8 pin configuration

BLOCK DIAGRAM

PCA24S08

SDA

SCL

INPUT

FILTER

SW02220

BYTE

COUNTER

PIN DESCRIPTION

PIN NUMBER SYMBOL NAME AND FUNCTION

V

8

DD

7

WP

6

SCL
SDA

I2C BUS CONTROL LOGIC

1, 2 n.c. not connected

3 PROT Active-LOW protect reset input
4 GND Ground
5 SDA Serial data open drain I/O
6 SCL Serial clock open drain input
7 WP Active-HIGH write protect input
8 V

EEPROM
8 PAGES

(8 × 128 bytes each)

DD

SEQUENCER

Supply voltage

DIVIDER

WP
PROT

(÷ 128)

ACCESS

BYTE

LATCH

(8 BYTES)

V

DD

POWER-ON RESET

GND

ADDRESS

POINTER

PROTECTION

IDENTIFICATION

NUMBER

EE

CONTROL

TIMER

(÷ 16)

OSCILLATOR

SW02140

Figure 2. Block diagram

2004 May 10

3

Philips Semiconductors Product data

PCA24S081024 × 8-bit CMOS EEPROM with access protection

DEVICE ADDRESSING

Following a START condition, the bus master must output the
address of the slave it is accessing. The address of the PCA24S08
is shown in Figure 3.

10101B2B1

FIXED

SELECTABLE

Figure 3. Slave address

The last bit of the slave address defines the operation to be
performed. When set to logic 1, a read operation is selected, while

logic 0 selects a write operation. Bits B2 and B1 in the slave address

represent the 2 most significant bits of the word to be addressed.
The third device address bit in the I
matched to A
internally connected HIGH, so device addresses A8h through AFh

(pin 3) on a standard 24C08 serial EEPROM is

2

2

C protocol that is usually

(hex) are used to access the memory on the chip.

R/W

SOFTWARE

SW02221

000

BLOCK 0

000

WRITE OPERATIONS

Write operations on the device can be performed only when WP is
held LOW. When WP pin is held HIGH, content of the full memory is
protected (Block 0 to Block 7, APP Registers, ID Page), and no write
operation is allowed.

Byte/word write: Write command may be used to set the address
for a subsequent Read command. For a write operation, the
PCA24S08 requires a second address field. The address field
associated with the two software selectable bits in the slave address
is a word address providing access to the 1024 bytes of memory, as
shown in Figure 4. Upon receipt of the word address, the
PCA24S08 responds with an acknowledge and awaits the next
eight bits of data, again responding with an acknowledge. Word
address is automatically incremented. Figure 5 shows how the
memory array is addressed when the slave address byte and
address field byte are sent. The master terminates the transfer by
generating a STOP condition. After this STOP condition, the
Erase/Write (E/W) cycle starts and the I
transmission. Up to 16 bytes of data can be written in the slave
writing sequence (E/W cycle).

PAGE 0

PAGE 7

0000

BYTE 15

1111

0000

BYTE 0

BYTE 0

2

C-bus is free for another

BLOCK 7

111

10101B2B1

FIXED

BLOCK NUMBER

R/W

111

PAGE 0

000

PAGE 7

111

B0 P2 P1 P0 A3 A2 A1 A0

PAGE

NUMBER

BYTE

ADDRESS

BYTE 15

1111

BYTE 0

0000

BYTE 15

1111

BYTE 0

0000

BYTE 15

1111

SW02222

2004 May 10

Figure 4. Memory addressing

4

Philips Semiconductors Product data

PCA24S081024 × 8-bit CMOS EEPROM with access protection

The general command encoding used by the serial port for
EEPROM accesses is shown below in Device Access Examples,
where B
block and A

is the block number, P

2-0

is the byte address within the page. Bits denoted as

3-0

“x” are ignored by the device.

is the page number within the

2-0

ACKNOWLEDGE

FROM SLAVE

S

1 B21 0 B11 0

ADDRESS

0A A

R/W

WORD

WORD

ADDRESS

ACKNOWLEDGE

FROM SLAVE

A0B0 P2 P1 P0 A3 A2 A1

Figure 5. Auto-increment memory word address; two byte write

Page write: The PCA24S08 is capable of a 16-byte page write

operation. It is initiated in the same manner as the byte write
operation. The master can transit 16 data bytes within one
transmission. After receipt of each byte, the PCA24S08 will respond
with an acknowledge. The typical E/W time in this mode is 5 ms.

After the receipt of each data byte, the four low-order bits of the
word address are internally incremented. The six high-order bits of
the address remain unchanged. The slave acknowledges the
reception of each data byte with an ACK. The I
is terminated by the master after the 16

2

C-bus data transfer

th

byte of data with a STOP

condition. After a write to the last byte in a page, the internal

ACKNOWLEDGE

FROM SLAVE

ACKNOWLEDGE

FROM SLAVE

ACKNOWLEDGE

FROM SLAVE

DATA

AUTO INCREMENT
WORD ADDRESS

A

DATA A

AUTO INCREMENT
WORD ADDRESS

P

SW02103

address is wrapped around to point to the beginning of that page. If
the master transmits more than 16 bytes prior to generating the
STOP condition, no acknowledge will be given on the 17

th

(and
following) data bytes and the whole transmission will be ignored and
no programming will be done. As in the byte write operation, all
inputs are disabled until completion of the internal write cycles.

After this STOP condition, the E/W cycle starts and the I

2

C-bus is

free for another transmission.
During the E/W cycle the slave receiver does not acknowledge if

addressed via the I

2

C-bus.

ACKNOWLEDGE

FROM SLAVE

S

2004 May 10

1 B21 0 B11 0

WORD

ADDRESS

0A A

R/W

WORD

ADDRESS

A0B0 P2 P1 P0 A3 A2 A1

Figure 6. Page write operation: 16 bytes

DATA

AUTO INCREMENT
WORD ADDRESS

A

LAST BYTE

DATA + 1

DATA + 15

AUTO INCREMENT
WORD ADDRESS

AUTO INCREMENT
WORD ADDRESS

ACKNOWLEDGE

FROM SLAVE

A

A

P

A

SW02104

5