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PCA24S08
1024 × 8-bit CMOS EEPROM
with access protection
Product data 2004 May 10
Philips Semiconductors Product data
PCA24S081024 × 8-bit CMOS EEPROM with access protection
DESCRIPTION
The PCA24S08 provides 8192 bits of serial electrically erasable and
programmable Read-only memory (EEPROM) organized as
1024 words of 8 bits each. Data bytes are received and transmitted
via the serial I
Access permissions limiting reads or writes are set via the I2C-bus
to isolate blocks of memory from improper access.
The PCA24S08 is intended to be pin compatible with standard
24C08 serial EEPROM devices except for pins 1, 2, and 3, which
are address pins in the standard part. Other exceptions to the
PCA24C08 serial EEPROM datasheet are noted the “Serial
EEPROM Exception” section later in this document.
All bits are sent to or read from the device, most significant bit first,
in a manner consistent with the 24C08 serial EEPROM. The bit
fields in this document are correspondingly listed with the MSB on
the left and the LSB on the right.
The EEPROM memory is broken up into 8 blocks of 1 k bits
(128 bytes) each. Within each block, the memory is physically
organized in to 8 pages of 128 bits (16 bytes) each. In addition to
these 8 k bits, there are two more 128-bit pages that are used to
store the access protection and ID information. There are a total of
8448 bits of EEPROM memory available in the PCA24S08.
Access protection (both read and write) is organized on a block
basis for blocks 1 through 7 and on a page and a block basis for
block 0. Protection information for these blocks and pages is stored
in one of the additional pages of EEPROM memory that is
addressed separately from the main data storage array. See
“Access Protection” for more details.
The ID value (see “ID Configuration”) is located in the ID page of the
EEPROM, the second of the additional 16 byte pages.
Writes from the serial interface may include from one to 16 bytes at
a time, depending on the protocol followed by the bus master. All
page accesses must be properly aligned to the internal EEPROM
page.
The EEPROM memory offers an endurance of 100,000 write cycles
per byte, with 10 year data retention. Writes to the EEPROM take
less than 5 ms to complete.
After manufacturing, all EEPROM bits will be set to a value of ‘1’.
2
C-bus.
FEATURES
• Non-volatile storage of 8 kbits organized as 8 blocks of 128 bytes
each
2
• I
C interface logic
• Compatible with 24C08 Serial EEPROM, and alternate source of
Atmel AT24RF08C without the RF interface
• Write operation:
– Byte write mode
– 16-byte page write mode
• Read operation:
– Sequential read
– Random read
• Programmable access protection to limit reads and writes
• Lock/unlock function
• Write protect feature protecting the full memory array against write
operations
• Self timed write cycle
• Internal power-on reset
• High reliability:
– Ten years non-volatile data retention time
– 100,000 write cycle endurance
• Low power CMOS technology
• Operating power supply voltage range of 2.5 V to 3.6 V
• 0 to 400 kHz clock frequency
• ESD protection exceeds 2000 V HBM per JESD22-A114,
200 V MM per JESD22-A115 and 1000 V CDM per JESD22-C101
• Latch-up testing is done to JEDEC Standard JESD78 which
exceeds 100 mA
• Packages offered: SO8, TSSOP8
ORDERING INFORMATION
PACKAGES TEMPERATURE RANGE ORDER CODE TOPSIDE MARK DRAWING NUMBER
8-pin plastic SO –40 °C to +85 °C PCA24S08D P24S08 SOT96-1
8-pin plastic TSSOP –40 °C to +85 °C PCA24S08DP PS08 SOT505-1
Standard packing quantities and other packaging data are available at www.philipslogic.com/packaging.
2004 May 10
2
Philips Semiconductors Product data
PCA24S081024 × 8-bit CMOS EEPROM with access protection
PIN CONFIGURATION
1
n.c.
2
n.c.
3
PROT
45
GND
Figure 1. 8 pin configuration
BLOCK DIAGRAM
PCA24S08
SDA
SCL
INPUT
FILTER
SW02220
BYTE
COUNTER
PIN DESCRIPTION
PIN NUMBER SYMBOL NAME AND FUNCTION
V
8
DD
7
WP
6
SCL
SDA
I2C BUS CONTROL LOGIC
1, 2 n.c. not connected
3 PROT Active-LOW protect reset input
4 GND Ground
5 SDA Serial data open drain I/O
6 SCL Serial clock open drain input
7 WP Active-HIGH write protect input
8 V
EEPROM
8 PAGES
(8 × 128 bytes each)
DD
SEQUENCER
Supply voltage
DIVIDER
WP
PROT
(÷ 128)
ACCESS
BYTE
LATCH
(8 BYTES)
V
DD
POWER-ON RESET
GND
ADDRESS
POINTER
PROTECTION
IDENTIFICATION
NUMBER
EE
CONTROL
TIMER
(÷ 16)
OSCILLATOR
SW02140
Figure 2. Block diagram
2004 May 10
3
Philips Semiconductors Product data
PCA24S081024 × 8-bit CMOS EEPROM with access protection
DEVICE ADDRESSING
Following a START condition, the bus master must output the
address of the slave it is accessing. The address of the PCA24S08
is shown in Figure 3.
10101B2B1
FIXED
SELECTABLE
Figure 3. Slave address
The last bit of the slave address defines the operation to be
performed. When set to logic 1, a read operation is selected, while
logic 0 selects a write operation. Bits B2 and B1 in the slave address
represent the 2 most significant bits of the word to be addressed.
The third device address bit in the I
matched to A
internally connected HIGH, so device addresses A8h through AFh
(pin 3) on a standard 24C08 serial EEPROM is
2
2
C protocol that is usually
(hex) are used to access the memory on the chip.
R/W
SOFTWARE
SW02221
000
BLOCK 0
000
WRITE OPERATIONS
Write operations on the device can be performed only when WP is
held LOW. When WP pin is held HIGH, content of the full memory is
protected (Block 0 to Block 7, APP Registers, ID Page), and no write
operation is allowed.
Byte/word write: Write command may be used to set the address
for a subsequent Read command. For a write operation, the
PCA24S08 requires a second address field. The address field
associated with the two software selectable bits in the slave address
is a word address providing access to the 1024 bytes of memory, as
shown in Figure 4. Upon receipt of the word address, the
PCA24S08 responds with an acknowledge and awaits the next
eight bits of data, again responding with an acknowledge. Word
address is automatically incremented. Figure 5 shows how the
memory array is addressed when the slave address byte and
address field byte are sent. The master terminates the transfer by
generating a STOP condition. After this STOP condition, the
Erase/Write (E/W) cycle starts and the I
transmission. Up to 16 bytes of data can be written in the slave
writing sequence (E/W cycle).
PAGE 0
PAGE 7
0000
BYTE 15
1111
0000
BYTE 0
BYTE 0
2
C-bus is free for another
BLOCK 7
111
10101B2B1
FIXED
BLOCK NUMBER
R/W
111
PAGE 0
000
PAGE 7
111
B0 P2 P1 P0 A3 A2 A1 A0
PAGE
NUMBER
BYTE
ADDRESS
BYTE 15
1111
BYTE 0
0000
BYTE 15
1111
BYTE 0
0000
BYTE 15
1111
SW02222
2004 May 10
Figure 4. Memory addressing
4
Philips Semiconductors Product data
PCA24S081024 × 8-bit CMOS EEPROM with access protection
The general command encoding used by the serial port for
EEPROM accesses is shown below in Device Access Examples,
where B
block and A
is the block number, P
2-0
is the byte address within the page. Bits denoted as
3-0
“x” are ignored by the device.
is the page number within the
2-0
ACKNOWLEDGE
FROM SLAVE
S
1 B21 0 B11 0
ADDRESS
0A A
R/W
WORD
WORD
ADDRESS
ACKNOWLEDGE
FROM SLAVE
A0B0 P2 P1 P0 A3 A2 A1
Figure 5. Auto-increment memory word address; two byte write
Page write: The PCA24S08 is capable of a 16-byte page write
operation. It is initiated in the same manner as the byte write
operation. The master can transit 16 data bytes within one
transmission. After receipt of each byte, the PCA24S08 will respond
with an acknowledge. The typical E/W time in this mode is 5 ms.
After the receipt of each data byte, the four low-order bits of the
word address are internally incremented. The six high-order bits of
the address remain unchanged. The slave acknowledges the
reception of each data byte with an ACK. The I
is terminated by the master after the 16
2
C-bus data transfer
th
byte of data with a STOP
condition. After a write to the last byte in a page, the internal
ACKNOWLEDGE
FROM SLAVE
ACKNOWLEDGE
FROM SLAVE
ACKNOWLEDGE
FROM SLAVE
DATA
AUTO INCREMENT
WORD ADDRESS
A
DATA A
AUTO INCREMENT
WORD ADDRESS
P
SW02103
address is wrapped around to point to the beginning of that page. If
the master transmits more than 16 bytes prior to generating the
STOP condition, no acknowledge will be given on the 17
th
(and
following) data bytes and the whole transmission will be ignored and
no programming will be done. As in the byte write operation, all
inputs are disabled until completion of the internal write cycles.
After this STOP condition, the E/W cycle starts and the I
2
C-bus is
free for another transmission.
During the E/W cycle the slave receiver does not acknowledge if
addressed via the I
2
C-bus.
ACKNOWLEDGE
FROM SLAVE
S
2004 May 10
1 B21 0 B11 0
WORD
ADDRESS
0A A
R/W
WORD
ADDRESS
A0B0 P2 P1 P0 A3 A2 A1
Figure 6. Page write operation: 16 bytes
DATA
AUTO INCREMENT
WORD ADDRESS
A
LAST BYTE
DATA + 1
DATA + 15
AUTO INCREMENT
WORD ADDRESS
AUTO INCREMENT
WORD ADDRESS
ACKNOWLEDGE
FROM SLAVE
A
A
P
A
SW02104
5
Philips Semiconductors Product data
PCA24S081024 × 8-bit CMOS EEPROM with access protection
READ OPERATIONS
Read operations are initiated in the same manner as write
operations with the exception that the LSB of the slave address is
set to logic 1.
The lower 7 bits of the word address are incremented after each
transmission of a data byte during a read. The three MSBs of the
word address are not changed when the word counter overflows.
Thus, the word address overflows from 127 to 0, and from 255 to
128. After the read of the last byte within a block, the internal serial
address wraps around to point at the beginning of that block.
ACKNOWLEDGE
FROM SLAVE
1 B21 0 B11 0S0A A
R/W
WORD
ADDRESS
FIRST PART
WORD
ADDRESS
SECOND PART
ACKNOWLEDGE
FROM SLAVE
A0B0 P2 P1 P0 A3 A2 A1 DATA
S A A
AT THIS MOMENT MASTER
TRANSMITTER BECOMES
MASTER RECEIVER AND
EEPROM SLAVE TRANSMITTER
1 X1 X1 010
ACKNOWLEDGE
FROM MASTER
R/W
DATA
LAST BYTE
NO ACKNOWLEDGE
AUTO INCREMENT
WORD ADDRESS
n BYTES
AUTO INCREMENT
WORD ADDRESS
FROM MASTER
P
A
ACKNOWLEDGE
FROM MASTER
Figure 7. Master reads PCA24S08 slave after setting word address (write word address: read data); sequential read
ACKNOWLEDGE
FROM SLAVE
S A A
1 X1 X1 010
R/W
DATA
n BYTES
ACKNOWLEDGE
FROM MASTER
AUTO INCREMENT
WORD ADDRESS
LAST BYTES
NO ACKNOWLEDGE
FROM MASTER
AUTO INCREMENT
WORD ADDRESS
PDATA A
SW02223
2004 May 10
SW02224
Figure 8. Master read PCA24S08 immediately after first byte (read mode); current address read
6
Philips Semiconductors Product data
PCA24S081024 × 8-bit CMOS EEPROM with access protection
ACCESS PROTECTION
Write operation on the Access protection registers can be performed
when WP pin LOW. If the WP pin is HIGH all write operations are
prohibited from the serial port, although write commands may be
used to set the address for a subsequent read command.
All access protection bits are stored on a separate page of the
EEPROM that is not accesses using the normal commands of a
PCA24C08 memory . See the “Access Protection Page” section for
more detail on this information.
RFID ACCESS FIELDS (RF)
Even though the PCA24S08 does not have the RFID capability,
RFID access fields (RF) can be stored in order to keep existing
software compatibility. The fields are stored in the EEPROM and
organized as follows:
MSB
0 0 No accesses permitted from RFID port
0 1 No accesses permitted from RFID port
1 0 Read only from RFID port
1 1 No restrictions for RFID accesses
LSB FUNCTION
PROTECTION BITS (PB)
The protection bits fields in the Access Protection Page determine
what type of accesses will be permitted via the serial port for each of
the blocks on the chip. If an illegal access is attempted, the
command will be NACK’ed. The MSB, if clear, prohibits all access to
the block, and the LSB if clear prohibits writes. The fields are stored
in the EEPROM and are organized as follows:
MSB
0 0 No accesses permitted in the block
0 1 No accesses permitted in the block
1 0 Read only, writes cause a NACK
1 1 Read/write —No access constraints for
Accessed within the Access Protection Page is an individual CMOS
Sticky Bit (SB) for each of the 8 blocks on the device. When the
value of the sticky bit is ‘0’, the Protection Bits (PB) for the
corresponding block may not be changed via the software. These
bits are all set to one when power is initially applied or when the
PROT
the serial interface using the standard serial write operations.
Reading the sticky bits does not affect their state.
Because permissions are set individually for each of the blocks, all
reads via serial port will only read bytes within the block that was
specified when the current address was latched in the device (with a
write command). The block address bits (B
the write command are ignored on a read command.
When a sticky bit is cleared (programmed at 0), the byte containing
the sticky bit cannot be changed anymore. If a write operation to this
byte is attempted, it will be normally acknowledged but no change
LSB FUNCTION
data within this block
pin is LOW. These sticky bits may be written only to a ‘0’ via
or B1) that are sent with
2
will happen in the byte value. The device does not go to an E/W
cycle and can be accessed immediately.
If a block is protected and only read operation is allowed (the
corresponding APP register has its PB bits programmed to 10), a
write operation to this block is not acknowledged (Slave Address
and Register pointer only are acknowledged). The device does not
go to an E/W cycle and can be accessed immediately.
S – Addr+W – ACK – Reg Pointer – ACK – Data – NACK
This applies to:
– EEPROM Block 0 to Block 7, controlled by PB
– The last 7 bytes of the APP block (09H to 0FH) and the
ID page (10H to 1FH) controlled by PBAP
If a block is protected and neither read operation nor write operation
is allowed (the corresponding APP register has its PB bits
programmed to 00 or 01), a write operation to this block is not
acknowledged (Slave Address and Register pointer only are
acknowledged).
S – Addr+W – ACK – Reg Pointer – ACK – Data – NACK
A read operation to this block is not allowed.
S – Addr+W – ACK – Reg Point er – ACK – Sr – Addr+ R – NACK
S – Addr+W – ACK – Reg Poin ter – ACK – P – S – Addr+R – NACK
This applies to:
– EEPROM Block 0 to Block 7, controlled by PB
– The last 7 bytes of the APP block (09H to 0FH) and the
ID page (10H to 1FH) controlled by PBAP
to PB
0
to PB
0
7
7
BLOCK 0 WRITE PROTECTION BITS
The PCA24S08 provides a mechanism to divide block 0 into eight
128-bit (16 byte) pages that can be individually protected against
writes. These eight write protection (WPN) bits are stored within a
byte of the access protection page and are organized such that the
LSB protects the first 128 bits and so on. If a bit in this byte is set to
a one and the PB
page corresponding to the WPN bit. If the WPN bit is set to a 0 or
the PB0 is any value other than 11, then writes are not permitted in
that page.
The Write Protection hierarchy for serial accesses is shown in
Figure 6. In this drawing the bits within the boxes to the left of the
arrows are the only thing that determine whether or not the bit in the
box to the right of the arrow can be written. Read access control is
not shown in this diagram. Addresses listed in this diagram are for
the serial port assuming that the R/W bit in the command byte is set
to ‘0’.
For example, when SB
value by the system. When the PB
written to by the system. Note that the state of the SB
affect whether or not Block 1 can be written.
There is no individual page Write Protection for any other block
other than block 0 within the device. Within the remaining blocks on
the chip, access permissions are controlled on a block basis (BP
bits) or full chip basis (WP pin) only.
field is set to 11, then writes are permitted on the
0
is a 1, the PB1 field can be written to any
1
field is 11, Block 1 can be
1
bit does not
1
2004 May 10
7
Philips Semiconductors Product data
PCA24S081024 × 8-bit CMOS EEPROM with access protection
WRITE PROTECTION FLOW
WP
A800
A80F
A810
A81F
A870
A87F
A880
A88FF
BLOCK 0
SB
SB
SB
PB
PB
PB
0
AP
1
WPN
WPN
WPN
0
1
7
0
AP
1
Page 0
16 bytes
Page 1
16 bytes
Page 7
16 bytes
Block 1
128 bytes
SB
SB
SB
SB
SB
AE80
7
PB
7
Block 7
128 bytes
AEFF
0
SB
0
SB
SB
SB
1
7
AP
1
7
PB
PB
PB
PB
B800
0
B801
1
ACCESS
B807
7
B808
AP
PROTECTION
PAGE
B809
7 bytes
AP
PB
AP
ID Page
16 bytes
B80F
B810
B81F
SW02225
Figure 9. Write protection example
2004 May 10
8
Philips Semiconductors Product data
PCA24S081024 × 8-bit CMOS EEPROM with access protection
ACCESS PROTECTION PAGE
The serial port may be used to read and write the Access Protection
Page (APP) and ID Page using device access codes B8h and B9h
instead of the normal value of A8h through AFh (hex) that are used
to access the rest of the EEPROM memory. The second byte of
write commands (the word address) should be in the range of 00h
through 0Fh for the APP page and 10h through 1Fh for the ID page.
This coding is shown in the Access Protection Page Examples
section.
Reads and writes to these two pages may take place on a single
byte basis only. Multi-byte operations will be NACK’ed.
As an example, the bit encoding for a single byte read and write
command are shown in the Access Protection Page Examples
section.
The PCA24S08 will acknowledge all device addresses of B8h or
B9h. If the most significant three its of the word address are not all 0
(indicating an address outside the Access protection and ID pages),
the chip will NACK the access.
Bytes 0 through 7 of the APP contain 8 identical set of access
control fields (PBx and SBx) for each of the eight blocks of memory
on the chip, which operate according to the table listed in the
Access Protection section above. When the sticky bit in one of these
bytes is set, that byte can be written by the system. Once a sticky bit
is reset (written to zero) by the software, the byte containing it can
no longer be modified by the software until the next power cycle.
These bytes can always be read by the system.
Byte 8 contains another PB field (PB
additional sticky bit (SB
) as bit 7. The value of the PBAP bits
AP
controls read and write access to the last 7 bytes (9–15) of the APP
and all 16 bytes of the ID page according to the encoding listed in
the “Access Protection” section above. The value of the PB
can only be changed, a write from the serial port, when SB
HIGH. This byte can always be read by the system. Bit 0 through 6
of this byte are stored in EEPROM memory and do not change
when the power is cycled or the PROT
Byte 9 contains the 8 block 0 write protection bits (WPN) for each
page within block 0.
Byte 10 emulates a coil detection feature to keep compatibility with
existing software controlling device.
Even though the PCA24S08 does not have the RFID capability of
the AT24RF03C, it gives a “coil non detected” information when the
detection feature is initiated.
The detection feature uses the Detection Enable bit (DE) and the
Detect Coil bit (DC). At power-up, DE = 0 and DC = 1. Detection is
) as bits 0 and 1 and an
AP
pin changes state.
AP
AP
bits
is
enabled by setting DE bit at 1. Since no coil is detected, DC is then
automatically reset and equal to 0.
DE is a Read/Write bit, DC is a Read Only bit. Attempt to write to
this bit will be ignored.
Bit 0 in the same byte emulates a Tamper bit and is always equal
to 0.
TAMPER is a Read Only bit. Attempt to write a ‘1’ to this bit will be
ignored.
Bytes 11 through 14 are currently reserved and should not be used
by the system. Byte 14 may not be written by the device at any time.
Byte 11 to 13 are read/write bytes that are stored in the EEPROM.
Byte 14 is a read only byte and the returned value during a read
operation is FFh. A write on it is acknowledged but the write will be
ignored.
Device Access Examples
For Write Operations:
1 0 1 1 1 0 0 0 0 0 0 P
o A3 A2 A1 A0
P0: used to distinguish between the APP and RFID pages
P
= 0: APP pages
0
= 1: RFID pages
P
0
For Read Operations:
1 0 1 1 1 0 0 1 D
7 D6 D5 D4 D3 D2 D1 D0
Byte 15 contains device revision information stored in the EEPROM.
It is set at the wafer production facility and cannot be changed in the
field, so any write to this byte will be ignored but acknowledged. The
value of this byte is 10h.
The memory map for the access protection page is shown in the
APP Memory Map table. In this table, an X means that the value is a
don’t care upon writing and that it is undefined upon reading. The
PB fields are all two bits wide, and the Device Revision field is 8 bits
wide. All other fields are on bit wide.
With the exception of the 9 sticky bits (SB) the two coil detect bits
(DE and DC), the tamper bit (TAMPER) and bytes 14 and 15, all bits
within the Access Protection Page are stored in EEPROM memory.
Their state does not change if power is removed or when the PROT
pin is held LOW.
The following page of memory (accessed with A4 = 1) emulate the
ID field that would be transmitted by the device from the RFID port.
Bytes within it are accessed with the address byte at B8h or B9h
(write/read). Reading and writing to this page is permitted when
PB
is 11.
AP
D7 D6 D5 D4 D3 D2 D1 D
0
2004 May 10
9
Philips Semiconductors Product data
PCA24S081024 × 8-bit CMOS EEPROM with access protection
APP MEMORY MAP
ADDRESS BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
0 SB
1 SB
2 SB
3 SB
4 SB
5 SB
6 SB
7 SB
8 SB
0
1
2
3
4
5
6
7
AP
9 WPN7 WPN6 WPN5 WPN4 WPN3 WPN2 WPN1 WPN0
10 DE DC X X X X X TAMPER
11 Reserved R/W
12 Reserved R/W
13 Reserved R/W
14 Reserved R only
15 Device Revision
X RF
X RF
X RF
X RF
X RF
X RF
X RF
X RF
0
1
2
3
4
5
6
7
X X PB
X X PB
X X PB
X X PB
X X PB
X X PB
X X PB
X X PB
X X X X X PB
0
1
2
3
4
5
6
7
AP
PROT PIN
The PROT pin is used as a power good signal. When this pin is held
LOW, the serial port is held in reset and all sticky bits are set to one.
When HIGH, activity on the serial bus is permitted and sticky bits
can be set to their values.
SERIAL EEPROM EXCEPTIONS
In general, the two-wire serial interface on the PCA24S08 functions
identically to the 24C08. The following exceptions exist, as noted
elsewhere in this document.
• Pins 1, 2, and 3 have different usage.
• Access to various blocks may be restricted via the access
protection circuitry.
• The two block address bits (B2 and B1) in the command byte are
ignored with all read commands. they are set only via the write
command.
• Multi-byte reads do not cross block boundaries, but instead wrap
to the beginning of the block.
• The serial port will be reset whenever the PROT pin is LOW.
• If more than 16 bytes are written to the EEPROM with a page
write, overlapping bytes will have their values corrupted.
• If V
is 0 V, the device draws current on the SDA, SCL, WP , and
DD
pins when they are brought above 0 V .
PROT
2004 May 10
10
Philips Semiconductors Product data
PCA24S081024 × 8-bit CMOS EEPROM with access protection
ABSOLUTE MAXIMUM RATINGS
Absolute Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation under these conditions is not implied.
SYMBOL
voltage on VDD with respect to ground — 4.6 V
voltage on SDA, SCL, PROT, and WP –0.1 to V
T
stg
T
amb
storage temperature –55 +125
operating temperature –40 +85
DC ELECTRICAL CHARACTERISTICS
VDD = 2.5 V to 3.6 V; VSS = 0 V; T
SYMBOL
V
DD
I
DDR
I
DDW
I
stb
I
LIO
I
LWP
V
IL
V
IH
V
OL
C
I
C
IO
supply voltage 2.5 — 3.6 V
supply current, EEPROM reads VDD = 3.6 V; f
supply current, EEPROM writes VDD = 3.6 V; f
standby current VDD = 3.6 V; SDA, SCL = V
input/output current, PROT, SDA, SCL VIN = VDD or V
input current on WP VWP = VDD = 5.5 V — — 20 µA
LOW-level input voltage –0.1 — VDD × 0.3 V
HIGH-level input voltage VDD × 0.7 — V
LOW-level output voltage I
input capacitance SCL, PROT, WP not tested — — 6 pF
input/output capacitance SDA not tested — — 8 pF
PARAMETER CONDITIONS MIN TYP MAX UNIT
= –40 °C to +85 °C; unless otherwise specified.
amb
PARAMETER MIN MAX UNIT
DD
+0.3 V
_C
_C
= 100 kHz — 50 100 µA
SDA
= 100 kHz — 0.325 1.0 mA
SDA
SS
SS
= 2.1 mA — — 0.4 V
OL
— 11.4 15 µA
— 0.25 3.0 µA
DD
V
2004 May 10
11
Philips Semiconductors Product data
PCA24S081024 × 8-bit CMOS EEPROM with access protection
AC SPECIFICA TIONS
CL = 1 TTL gate and 100 pF, except as noted. VDD = 2.5 V to 3.6 V.
SYMBOL
f
t
t
HD;STA
t
SU;STA
t
SU;STO
t
HD;DAT
t
VD;ACK
t
VD;DAT
t
VD;DAT
t
SU;DAT
t
t
HIGH
SCL
BUF
LOW
t
F
t
R
t
SP
Operating frequency 0 100 0 400 kHz
Bus free time between STOP and ST ART conditions 4.7 — 1.3 — µs
Hold time after (repeated) STAR T condition 4.0 — 0.6 — µs
Repeated START condition setup time 4.7 — 0.6 — µs
Setup time for STOP condition 4.0 — 0.6 — µs
Data in hold time 0 — 0 — ns
Valid time for ACK condition
(L) Data out valid time
(H) Data out valid time
Data setup time 250 — 100 — ns
Clock LOW period 4.7 — 1.3 — µs
Clock HIGH period 4.0 — 0.6 — µs
Clock/Data fall time — 300 20 + 0.1 C
Clock/Data rise time — 1000 20 + 0.1 C
Pulse width of spikes that must be suppressed by the input filters — 50 — 50 ns
NOTES:
= total capacitance of one bus line in pF.
1. C
b
2. t
3. t
= time for Acknowledgement signal from SCL LOW to SDA (out) LOW.
VD;ACK
= minimum time for SDA data out to be valid following SCL LOW.
VD;DAT
3
3
PARAMETER
2
STANDARD MODE
I2C-bus
MIN MAX MIN MAX
— 600 — 600 ns
— 600 — 600 ns
— 1500 — 600 ns
FAST MODE
I2C-bus
1
b
1
b
UNITS
300 ns
300 ns
EEPROM MEMORY
NAME PARAMETER MIN TYP MAX UNIT
Retention Data retention at operating temperature 10 — — Years
Endurance Per byte 100,000 — — Cycles
SDA
t
SP
t
SU;STO
PP S
SU00645
SCL
t
BUF
t
LOW
t
HD;STA
t
R
t
HD;DAT
t
HIGH
t
F
t
SU;DAT
t
HD;STA
t
SU;STA
Sr
Figure 10. Timing diagram for serial interface AC specifications
2004 May 10
12
Philips Semiconductors Product data
PCA24S081024 × 8-bit CMOS EEPROM with access protection
SO8: plastic small outline package; 8 leads; body width 3.9 mm SOT96-1
2004 May 10
13
Philips Semiconductors Product data
PCA24S081024 × 8-bit CMOS EEPROM with access protection
TSSOP8: plastic thin shrink small outline package; 8 leads; body width 3 mm SOT505-1
2004 May 10
14
Philips Semiconductors Product data
PCA24S081024 × 8-bit CMOS EEPROM with access protection
REVISION HISTORY
Rev Date Description
_1 20040510 Product data (9397 750 13015)
2004 May 10
15
Philips Semiconductors Product data
PCA24S081024 × 8-bit CMOS EEPROM with access protection
Purchase of Philips I2C components conveys a license under the Philips’ I2C patent
to use the components in the I2C system provided the system conforms to the
I2C specifications defined by Philips. This specification can be ordered using the
code 9398 393 40011.
Data sheet status
Level
I
Data sheet status
Objective data
[1]
Product
[2] [3]
status
Development
Definitions
This data sheet contains data from the objective specification for product development.
Philips Semiconductors reserves the right to change the specification in any manner without notice.
II
III
[1] Please consult the most recently issued data sheet before initiating or completing a design.
[2] The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL
[3] For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status.
Preliminary data
Product data
http://www.semiconductors.philips.com.
Qualification
Production
This data sheet contains data from the preliminary specification. Supplementary data will be published
at a later date. Philips Semiconductors reserves the right to change the specification without notice, in
order to improve the design and supply the best possible product.
This data sheet contains data from the product specification. Philips Semiconductors reserves the
right to make changes at any time in order to improve the design, manufacturing and supply. Relevant
changes will be communicated via a Customer Product/Process Change Notification (CPCN).
Definitions
Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see
the relevant data sheet or data handbook.
Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting
values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given
in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no
representation or warranty that such applications will be suitable for the specified use without further testing or modification.
Disclaimers
Life support — These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be
expected to result in personal injury . Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree
to fully indemnify Philips Semiconductors for any damages resulting from such application.
Right to make changes — Philips Semiconductors reserves the right to make changes in the products—including circuits, standard cells, and/or software—described
or contained herein in order to improve design and/or performance. When the product is in full production (status ‘Production’), relevant changes will be communicated
via a Customer Product/Process Change Notification (CPCN). Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys
no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent,
copyright, or mask work right infringement, unless otherwise specified.
Contact information
For additional information please visit
http://www.semiconductors.philips.com . Fax: +31 40 27 24825
For sales offices addresses send e-mail to:
sales.addresses@www.semiconductors.philips.com.
Document order number: 9397 750 13015
Koninklijke Philips Electronics N.V. 2004
All rights reserved. Printed in U.S.A.
Date of release: 05-04
Philips
Semiconductors
2004 May 10
16
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